TW201611221A - 封裝體疊加堆疊式微電子結構 - Google Patents

封裝體疊加堆疊式微電子結構 Download PDF

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Publication number
TW201611221A
TW201611221A TW104118154A TW104118154A TW201611221A TW 201611221 A TW201611221 A TW 201611221A TW 104118154 A TW104118154 A TW 104118154A TW 104118154 A TW104118154 A TW 104118154A TW 201611221 A TW201611221 A TW 201611221A
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microelectronic
package
microelectronic package
substrate
stacked
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TW104118154A
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TWI590403B (zh
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特羅斯登 梅耶爾
吉拉德 歐弗納
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英特爾Ｉｐ公司
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    • H01L25/0657—Stacked arrangements of devices
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Abstract

一種封裝體疊加堆疊式微電子結構包含一對以倒裝結構方式彼此連接的微電子封裝體。在一個實施例中，該封裝體疊加堆疊式微電子結構可以包含一第一和一第二微電子封裝體，各包含一具有至少一個形成於每一微電子封裝體基體之第一表面上之封裝體連接銲墊的基體，且各具有至少一個電氣連接到每一微電子封裝體基體第一表面的微電子裝置，其中，該第一和第二微電子封裝體是以至少一個延伸在該第一微電子封裝體連接銲墊與該第二微電子封裝體連接銲墊之間的封裝體-對-封裝體互連結構來彼此連接。

Description

封裝體疊加堆疊式微電子結構 發明領域
本說明書的實施例係大致上有關於微電子封裝體製造的領域，更特別地，係有關於一種包括兩個以倒裝結構方式堆疊之微電子封裝體的微電子結構。
發明背景
微電子工業是持續地致力於生產更快且更小的微電子封裝體以供在各種電子產品中使用，包括但不限於，電腦伺服器產品和可攜帶型產器，諸如可攜帶型電腦、電子平板電腦、細胞電話、數位攝影機等等。達成這些目標的一種途徑是為堆疊式封裝體的製造。封裝體堆疊的一種類型，被稱為封裝體疊加式(PoP)堆疊，正變成需要小橫向尺寸、低封裝體高度、及在該封裝體疊加堆疊式結構之內之微電子裝置之間之高帶寬之行動與無線應用的重要解決方案。
依據本發明之一實施例，係特地提出一種封裝體疊加堆疊式微電子結構，包含：一第一微電子封裝體，包 含一具有一第一表面與至少一個形成於該微電子封裝體基體第一表面上之封裝體連接銲墊的基體，且具有至少一個電氣連接到該微電子封裝體基體第一表面的微電子裝置；一第二微電子封裝體，包含一具有一第一表面與至少一個形成於該每一微電子封裝體基體第一表面上之封裝體連接銲墊的基體，且具有至少一個電氣連接到該微電子封裝體基體第一表面的微電子裝置；及至少一個延伸在該第一微電子封裝體連接銲墊與該第二微電子封裝體連接銲墊之間的封裝體-對-封裝體互連結構。
100‧‧‧微電子封裝體
1001‧‧‧第一微電子封裝體
1002‧‧‧第二微電子封裝體
110‧‧‧封裝體基體
1101‧‧‧封裝體基體
1102‧‧‧封裝體基體
112‧‧‧第一表面
1121‧‧‧第一表面
1122‧‧‧第二表面
114‧‧‧第二表面
116‧‧‧導電路徑
122‧‧‧銲墊
1221‧‧‧銲墊
124‧‧‧銲墊
126‧‧‧銲墊
1261‧‧‧銲墊
132‧‧‧互連件
134‧‧‧凸塊
142‧‧‧微電子裝置
1421‧‧‧第一微電子裝置
1422‧‧‧第二微電子裝置
144‧‧‧主動表面
146‧‧‧銲墊
1461‧‧‧銲墊
148‧‧‧背面
1481‧‧‧背面
1482‧‧‧背面
152‧‧‧底填充材料
1521‧‧‧底填充材料
1522‧‧‧底填充材料
154‧‧‧互連結構
156‧‧‧封裝材料
158‧‧‧外部互連件
162‧‧‧微電子裝置
164‧‧‧銲墊
166‧‧‧裝置互連件
172‧‧‧銲線
174‧‧‧黏著材料
180‧‧‧封裝體疊加堆疊式微電子結構
200‧‧‧製程
202‧‧‧方塊
204‧‧‧方塊
206‧‧‧方塊
208‧‧‧方塊
210‧‧‧方塊
212‧‧‧方塊
300‧‧‧計算裝置
302‧‧‧板
304‧‧‧處理器
306A‧‧‧通訊晶片
306B‧‧‧通訊晶片
本揭露的標的在說明書的結論部份被特別地指出並清楚地主張。本揭露的上述及其他特徵將會由於後面的描述及後附的申請專利範圍，並結合該等附圖，而變得更加明顯。可以理解的是該等附圖僅描繪幾個依據本揭露的實施例而因此，不被認為是對其之範圍的限制。本揭露將會透過該等附圖的使用更具體和詳細地被描述，以致於本揭露的優點能夠更容易地確定，在其中：圖1-7描繪本說明書之一實施例之製造封裝體疊加堆疊式微電子結構之製程的橫截面圖。
圖8描繪本說明書之另一實施例之封裝體疊加堆疊式微電子結構的橫截面。
圖9描繪本說明書之又另一實施例之封裝體疊加堆疊式微電子結構的橫截面圖。
圖10描繪本說明書之再另一實施例之封裝體疊加堆疊 式微電子結構的橫截面圖。
圖11描繪本說明書之一實施例之沿著圖3之線A-A的頂視平面圖。
圖12描繪本說明書之另一實施例之沿著圖3之線A-A的頂視平面圖。
圖13是為本說明書之一實施例之製造封裝體疊加堆疊式微電子結構之製程的流程圖。
圖14描繪本說明書之一實施的計算裝置。
較佳實施例之詳細說明
在後面的詳細說明中，是參照該等以圖解方式顯示具體實施例的附圖，所要求保護的標的可以被實施在該等具體實施例中。這些實施例是足夠詳細地被描述以使熟知此項技術的人仕能夠實施該標的。應要理解的是各種實施例，雖然不同，但不一定是相互排斥的。例如，與一個實施例有關之於此中所述的一特定特徵、結構或特性在沒有離開所要求保護之標的的精神與範圍之下是能夠被實現在其他實施例之內。在這說明書之內對於”一個實施例”或”一實施例”的參照意味著與該實施例相關地作描述的一特定特徵、結構、或特性是被包括在至少一個被涵蓋在本說明書之內的實施。因此，該片語”一個實施例”或”在一實施例中”的使用不一定是指同一實施例。此外，要理解的是在每一被揭露實施例之內之個別元件的位置或配置在沒有離開所要求保護之標的的精神與範圍之下是可以被改變的。 後面的詳細說明是，因此，不應被視為具有限制意義，而且該標的的範圍是僅由被適當地解釋之後附的申請專利範圍連同該等後附之申請專利範圍所享有之等效物之全部範圍來被限定。在該等圖式中，相似的標號在若干圖式中標示相同或相似的元件或功能，而且於此中所述的該等元件不一定是彼此具有相同比例，個別的元件可以被放大或縮小俾可更易於理解在本說明書之上下文中的元件。
如於此中所使用的該等術語”之上”、”到”、”之間”及”在上面”可以是指一個層相對於其他層的相對位置。一個層”在另一個層之上”或者”在另一個層上”或被黏著”到”另一個層”可以是與該另一個層直接接觸或者可以具有一個或多個中介層。一個層”在層之間”可以是與該等層直接接觸或者可以具有一個或多個中介層。
本說明書的實施例包括一封裝體疊加堆疊式微電子結構，其包含一對以倒裝結構形式彼此連接的微電子封裝體。在一個實施例中，該封裝體疊加堆疊式微電子結構可以包含一第一和一第二微電子封裝體，各包含一具有至少一個形成於每一微電子封裝體結構之第一表面上之封裝體連接銲墊的基體，且各具有至少一個電氣連接到該每一微電子封裝體基體第一表面的微電子裝置，其中，該第一和第二微電子封裝體是以至少一個延伸在該第一微電子封裝體連接銲墊與該第二微電子封裝體連接銲墊之間的封裝體-對-封裝體互連結構來彼此連接。
圖1-7描繪本說明書的實施例，其中，一對微電 子封裝體是以倒裝結構形式彼此連接以形成一封裝體疊加堆疊式微電子結構。如在圖1中所示，一封裝體基體110可以被形成。該封裝體基體110可以是任何適當的基體，諸如一中介層等等般，具有一第一表面112和一相對第二表面114。該封裝體基體110可以具有數個形成於該封裝體基體第一表面112中或上的銲墊，包含至少一個微電子裝置連接銲墊122和至少一個封裝體-對-封裝體銲墊124，及數個形成於該封裝體基體第二表面114中或上的外部連接銲墊126。該封裝體基體110可以包含數個具有數個導電路徑116形成貫穿其間的介電層(圖中未示)，其中，該等導電路徑116可以形成在諸如該等微電子裝置連接銲墊122、該等封裝體-對-封裝體銲墊124、及/或該等外部連接銲墊126般之適當之銲墊之間的連接。
該封裝體基體110可以包含任何適合介電材料，包括，但不限於，液晶聚合物、環氧樹脂、雙馬來醯亞胺三氮雜苯樹脂、FR4、聚醯亞胺材料等等。該等導電路徑116可以是由適合的導電材料形成，包括，但不限於，銅、銀、金、鎳、及其之合金。要理解的是該封裝體基體110可以由任何數目的介電層形成，可以包含一硬核心(圖中未示)、及可以包含主動及/或被動微電子裝置(圖中未示)形成於其中。更要理解的是該等導電路徑116能夠形成任何想要的電氣路徑在該封裝體基體110之內及/或形成有額外的外部組件(圖中未示)。也要理解的是防焊層(圖中未示)能夠被利用在該封裝體基體第一表面112及/或該封裝體基體第二表面114 上，如同熟知此項技術之人仕會理解的一樣。用於形成該封裝體基體110的製程對於熟知此項技術的人仕來說是眾所周知的，而為了簡潔起見將不會於此中被描述或描繪。
如在圖2中所示，一封裝體互連材料凸塊134可以被形成在該等封裝體-對-封裝體銲墊124中的每一者上。該等封裝體互連材料凸塊134可以由任何適合材料形成，包括但不限於，可迴焊焊錫。
如在圖3中所示，一具有一主動表面144與一相對背面148的微電子裝置142能夠以數個裝置-對-基體互連件132來以一般被稱為覆晶之結構或者控制塌陷晶片連接("C4")結構來連接到對應的微電子裝置連接銲墊122以形成一微電子封裝體100。該等裝置-對-基體互連件132可以延伸在該等微電子裝置連接銲墊122與在該微電子裝置142之主動表面144上的鏡像銲墊146之間以形成一電氣連接在其間。要理解的是該等微電子裝置銲墊146可以是與在該微電子裝置142之內的積體電路(圖中未示)成電氣連通。該微電子裝置142可以是任何適合的微電子裝置，包括，但不限於微處理器、晶片組、圖形裝置、無線裝置、記憶體裝置、特殊應用積體電路裝置等等。
該裝置-對-基體互連件132可以是由任何適合材料，包括，但不限於，焊錫及導電環氧樹脂(conductive filled epoxies)。焊錫材料可以包括任何適合材料，包括但不限於，鉛/錫合金，像是63%錫/37%鉛焊錫般，或無鉛焊錫，像是純錫般或高錫含量合金(例如，90%或更高的錫)，像是錫/ 鉍、共晶錫/銀、三元錫/銀/銅、共晶錫/銅、及相類似合金般。當該微電子裝置142是以由焊錫製成的裝置-對-基體互連件132來連接到該微電子基體110時，該焊錫是以熱、壓力、及/或聲波能量來被迴焊俾使該焊錫牢固在該等微電子裝置銲墊146與該等微電子裝置連接銲墊122之間。此外，該微電子裝置142可以是連接到該基體110的銅柱基覆晶組件，如會由熟知此項技術的人仕所理解的一樣。
如在圖4中所示，一絕緣可流動材料，像是一底填充材料152般，是可以被設置在該微電子裝置142與該封裝體基體110之間，其實質上封裝該等裝置-對-基體互連件132。該底填充材料152可以被用來減低會由於在該微電子裝置142與該微電子基體110之間之熱彭脹不匹配而起的機械應力問題。該底填充材料152可以是一環氧樹脂材料，包括，但不限於環氧樹脂、氰酯、矽樹脂(silicone)、矽氧烷(siloxane)、酚醛基樹脂(phenolic based resins)，其具有足夠低的黏性俾當由一底填充材料分配器(圖中未示)引入時藉由毛細作用被芯吸在該微電子裝置142與該微電子基體110之間，其對於熟知此項技術的人仕來說會被理解。該底填充材料152可以隨後像是藉由熱或輻射般來被硬化(硬化)。該底填充材料152也可以是一鑄模材料(鑄模底膠)或者相類似的封裝材料，其是在同一時間底填充與覆蓋該微電子裝置142而且是在一鑄模步驟中被施加，如將會作討論的一樣。
如在圖5中所示，一對微電子封裝體，被描繪為 第一微電子封裝體1001和第二微電子封裝體1002，能夠被置放於一實質鏡像位置，其中該第一微電子封裝體基體第一表面1121面向該第二微電子封裝體基體第一表面1122，而該第一微電子封裝體1001與該第二微電子封裝體1002中之每一者的封裝體互連材料凸塊(見圖4的元件134)是彼此連接以形成封裝體-對-封裝體互連結構154。該等封裝體-對-封裝體互連結構154可以提供在該第一微電子封裝體1001與該第二微電子封裝體1002之間的電氣連通路徑。要注意的是關於圖1-4之組件之該第一微電子封裝體1001與該第二微電子封裝體1002的相似組件是分別以下標符號"1"和下標符號"2"標示。
該封裝體互連材料凸塊(見圖4的元件134)能夠由任何適合材料製成，包括，但不限於，焊錫和導電環氧樹脂。焊錫材料可以包括任何適合材料，包括但不限於，鉛/錫合金，像是63%錫/37%鉛焊錫般，或無鉛焊錫，像是純錫般或高錫含量合金(例如，90%或更高的錫)，像是錫/鉍、共晶錫/銀、三元錫/銀/銅、共晶錫/銅、及相類似合金般。當該第一微電子封裝體1001與該第二微電子封裝體1002是以由焊錫製成的封裝體互連材料凸塊134來彼此連接時，該焊錫是以熱、壓力、及/或聲波能量來被迴焊以致於該第一微電子封裝體1001與該第二微電子封裝體1002之對應的互連材料凸塊結合以形成封裝體-對-封裝體互連結構154。
如在圖6中所示，一封裝材料156可以被設置在該第一微電子封裝體1001與該第二微電子封裝體1002之間以 形成一封裝體疊加堆疊式微電子結構180。該封裝材料156可以是任何適合材料，像是環氧樹脂般，而且可以提供該封裝體疊加堆疊式微電子結構180結構剛性，其中該封裝材料156實質上包圍該等封裝體-對-封裝體互連結構154、該第一微電子裝置1421、和該第二微電子裝置1422。
如在圖7中所示，各種額外的組件可以是為該封裝體疊加堆疊式微電子結構180的一部份。如圖所示，外部互連件158可以被連接到用於把該封裝體疊加堆疊式微電子結構180連接到外部結構(圖中未示)，像是母板般，的該等第一微電子封裝體外部連接銲墊1261。再者，額外的微電子裝置可以是為該封裝體疊加堆疊式微電子結構180的一部份，像是由延伸在一額外微電子裝置162之銲墊164與該第二微電子封裝體外部連接銲墊1262之間之額外裝置互連件166所連接的額外微電子裝置162般。
要理解的是本說明書的標的不受限為在圖1-7中所描繪的結構。例如，如在圖8中所示，該等微電子裝置不必由覆晶式安裝所連接；而是，例如，該第一微電子裝置背面1481可以被連接到該第一微電子封裝體基體第一表面1121而且銲線172可以被形成在該等第一微電子封裝體微電子裝置銲墊1461與該等第一微電子封裝體基體微電子裝置連接銲墊1221之間。此外，在該封裝材料156是足夠低黏性來在該微電子裝置與該基體之間流動時該底填充材料(如圖7的第一底填充材料1521及/或第二底填充材料1522所示)不是必要的，像是在圖7中所示在該第二微電子封裝體 微電子裝置1422與該第二微電子封裝體基體1102之間(例如，一鑄模底填充材料)。此外，該等基體(例如元件1101與1102)中之一者可以是單面基體(例如，銲墊僅位在一個表面上)，像是一柔性基板(例如，聚醯亞胺)、一具備一重新分佈層的鑄模本體、一陶瓷材料、一疊層、或者任何其他適合的單面基體，像是在圖9中所描繪的第二微電子封裝體基體1102般。在另一實施例中，該第一微電子封裝體微電子裝置背面1481能夠在設置封裝材料156之前以黏著材料174連接到該第二微電子封裝體微電子裝置背面1482，如在圖10中所示。
如在圖11中所示，其是為沿著圖3之線A-A的頂視平面圖，該等封裝體互連材料凸塊132的配置可以是如此以致於它們實質上包圍該微電子裝置142。在圖12中所示的其他實施例中，該等封裝體互連材料凸塊134可以被配置在該微電子裝置142的相對側。要理解的是在圖11和12中之該等封裝體互連材料凸塊134的配置僅是為範例而且任何適合配置是可以被使用。
圖13是為製造本說明書之實施例之微電子結構之製程200的流程圖。如在方塊202中所陳述，一第一微電子封裝體可以被形成，包含一具有一第一表面與至少一個形成於每一微電子封裝體基體第一表面上之封裝體連接銲墊的基體。至少一個第一微電子裝置可以被電氣連接到該微電子封裝體基體第一表面，如在方塊204中所陳述。如在方塊206中所陳述，一第二微電子封裝體可以被形成，包含 一具有一第一表面與至少一個形成於每一微電子封裝體基體第一表面上之封裝體連接銲墊的基體。至少一個第二微電子裝置可以是電氣連接到該微電子封裝體基體第一表面，如在方塊208中所陳述。如在方塊210中所陳述，該第二微電子封裝體第一表面可以被定向俾面向該第一微電子封裝體第一表面。至少一個封裝體-對-封裝體互連結構可以被形成在該第一微電子封裝體連接銲墊與該第二微電子封裝體連接銲墊之間，如在方塊212中所陳述。
圖14描繪本說明書之一實施的計算裝置300。該計算裝置300容置一板302。該板302可以包括若干組件，包括但不限於一處理器304和至少一個通訊晶片306A,306B。該處理器304是物理地且電氣地耦合到該板302。在一些實施中該至少一個通訊晶片306A,306B也是物理地且電氣地耦合到該板302。在其他實施中，該通訊晶片306A,306B是為該處理器304的部份。
端視其之應用而定，該計算裝置300可以包括其他可以是或可以不是被物理地且電氣地耦合到該板302的組件。這些其他組件包括，但不限於，揮發性記憶體(例如，DRAM)、非揮發性記憶體(例如，ROM)、快閃記憶體、圖形處理器、數位訊號處理器、加密處理器、晶片組、天線、顯示器、觸碰螢幕顯示器、觸碰螢幕控制器、電池、音頻編解碼器、視頻編解碼器、功率放大器、全球定位系統(GPS)裝置、指南針、加速度計、陀螺儀、揚聲器、攝影機、及大量儲存裝置(諸如硬碟機、光碟(CD)、數位多功能碟(DVD) 等等般)。
該通訊晶片306A,306B致能用於資料至該計算裝置300之傳遞及來自該計算裝置300之傳遞的無線通訊。該名詞"無線"以及其之派生詞可以被用來描述可以經由一非固體媒介透過調制電磁輻射之使用來數據通訊的電路、裝置、系統、方法、技術、通訊通道等等。該名詞不暗示該等相關裝置不包含任何銲線，雖然在一些實施例中它們不包含。該通訊晶片306可以實施若干無線標準或協定中之任一者，包括但不限於Wi-Fi(IEEE 802.11 family)、WiMAX(IEEE 802.16 family)、IEEE 802.20、long term evolution(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽、其之衍生物、以及任何其他被指派為3G、4G、5G、更往後的無線協定。該計算裝置300可以包括數個通訊晶片306A,306B。例如，一第一通訊晶片306A可以是專注於諸如Wi-Fi與藍芽般之較短範圍無線通訊而一第二通訊晶片306B可以是專注於諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等等般之較長範圍無線通訊。
該計算裝置300的處理器304可以被包括在一封裝體疊加堆疊式微電子結構，如上所述。該名詞”處理器"可以是指處理來自暫存器及/或記憶體之電子資料俾把該電子資料轉換成其他可以被儲存於暫存器及/或記憶體內之電子資料的任何裝置或者一裝置的部份。再者，該通訊晶片306A,306B可以被包括在一封裝體疊加堆疊式微電子 結構，如上所述。
在各種實施中，該計算裝置300可以是一膝上型電腦、一上網書本型電腦、筆記本型電腦、一超輕薄筆記本型電腦、一智慧型電話、一平板電腦、一個人數位助理(PDA)、一超薄行動PC、一行動電話、一桌上型電腦、一伺服器、一印表機、一掃描器、一監視器、一機上盒、一娛樂控制單元、一數位相機、一可攜帶型音樂播放器、或者一數位錄影機。在其他實施中，該計算裝置300可以是任何其他處理資料的電子裝置。
要理解的是本說明書的標的不是必要地被限定為在圖1-14中所描繪的具體應用。該標的可以被應用到其他微電子裝置及裝置應用，以及任何合適的電子應用，如熟知此項技術之人仕會理解的一樣。
後面的例子涉及更多實施例。在該等範例中的特性可以被用在一個或更多實施例中的任何地方。
在範例1中，一封裝體疊加堆疊式微電子結構可以包含一第一微電子封裝體，包含一具有一第一表面與至少一個形成於該微電子封裝體基體第一表面上之封裝體連接銲墊的基體，及具有至少一個電氣連接到該微電子封裝體基體第一表面的微電子裝置；一第二微電子封裝體，包含一具有一第一表面與至少一個形成於每一微電子封裝體基體第一表面上之封裝體連接銲墊的基體，及具有至少一個電氣地連接到該微電子封裝體基體第一表面的微電子裝置；及至少一個延伸在該第一微電子封裝體連接銲墊與該 第二微電子封裝體連接銲墊之間的封裝體-對-封裝體互連結構。
在範例2中，範例1的標的可以選擇地包括一被設置在該第一微電子封裝體基體第一表面與該第二微電子封裝體基體第一表面之間的封裝材料。
在範例3中，範例1或2的標的能夠選擇地包括以數個在一覆晶結構中之互連件連接到其各自之基體之該第一微電子封裝體微電子裝置與該第二微電子封裝體微電子裝置中之至少一者。
在範例4中，範例3的標的能夠選擇地包括一設置在該第一微電子封裝體微電子裝置與該第一微電子封裝體基體之間的第一底填充材料，與一設置在該第二微電子封裝體微電子裝置與該第二微電子封裝體基體之間的第二底填充材料中之至少一者。
在範例5中，範例1至2的標的能夠選擇地包括以數條銲線連接到其各自之基體之該第一微電子封裝體微電子裝置與該第二微電子封裝體微電子裝置中之至少一者。
在範例6中，範例1至4中之任一者的標的能夠選擇地包括以黏著材料把該第一微電子封裝體微電子裝置的背面連接到該第二微電子封裝體微電子裝置的背面。
在範例7中，範例1至6中之任一者的標的能夠選擇地包括該包括一第二表面的第一微電子封裝體基體及該包括一第二表面的第二微電子封裝體基體，且更包括數個在該第一微電子封裝體基體第二表面與該第二微電子封裝 體基體第二表面中之至少一者中或上的外部銲墊。
在範例8中，一種形成封裝體疊加堆疊式微電子結構的方法包含形成一第一微電子封裝體，包含一具有一第一表面與至少一個形成於每一微電子封裝體基體第一表面上之封裝體連接銲墊的基體；把至少一個第一微電子裝置電氣連接到該微電子封裝體基體第一表面；形成一第二微電子封裝體，包含一具有一第一表面與至少一個形成於每一微電子封裝體基體第一表面上之封裝體連接銲墊的基體；把至少一個第二微電子裝置電氣地連接到該微電子封裝體基體第一表面；把該第二微電子封裝體第一表面定向俾面向該第一微電子封裝體第一表面；及形成至少一個延伸在該第一微電子封裝體連接銲墊與該第二微電子封裝體連接銲墊之間的封裝體-對-封裝體互連結構。
在範例9中，範例8的標的能夠選擇地包括形成至少一個封裝體-對-封裝體互連結構在該第一微電子封裝體連接銲墊與該第二微電子封裝體連接銲墊之間，包含形成一封裝體互連材料凸塊在其各自的第一微電子封裝體連接銲墊上、形成一封裝體互連材料凸塊在該第二微電子封裝體連接銲墊上、及把該第一微電子封裝體互連材料凸塊與該第二微電子封裝體互連材料凸塊連接在一起。
在範例10中，範例9的標的能夠選擇地包括形成該封裝體互連材料凸塊在其各自的第一微電子封裝體連接銲墊、形成該封裝體互連材料凸塊在該第二微電子封裝體連接銲墊上、及把該第一微電子封裝體互連材料凸塊與該 第二微電子封裝體互連材料凸塊連接在一起，包含形成一封裝體互連錫凸塊在其各自的第一微電子封裝體連接銲墊、形成該封裝體互連錫凸塊在該第二微電子封裝體互連銲墊上、及迴焊該第一微電子封裝體互連錫凸塊與該第二微電子封裝體互連錫凸塊。
在範例11中，範例8至10中之任一者的標的能夠選擇地包括設置一封裝材料在該第一微電子封裝體基體第一表面與該第二微電子封裝體基體第一表面之間。
在範例12中，範例8至11中之任一者的標的能夠選擇地包括把該第一微電子裝置電氣連接到該微電子封裝體基體第一表面，包含以數個在一覆晶結構中的互連件把該第一微電子裝置電氣連接到該第一微電子封裝體基體第一表面。
在範例13中，範例12的標的能夠選擇地包括設置一第一底填充材料在該第一微電子封裝體微電子裝置與該第一微電子封裝體基體之間。
在範例14中，範例8至13中之任一者的標的能夠選擇地包括把該第二微電子裝置電氣連接到該微電子封裝體基體第一表面，包含以數個在一覆晶結構中的互連件把該第二微電子裝置電氣連接到該第二微電子封裝體基體第一表面。
在範例15中，範例14的標的能夠選擇地包括設置一第二底填充材料在該第二微電子封裝體微電子裝置與該第二微電子封裝體基體之間。
在範例16中，範例8的標的能夠選擇地包括把該第一微電子裝置電氣連接到該微電子封裝體基體第一表面與把該第二微電子裝置電氣連接到該微電子封裝體基體中之至少一者，包含以銲線把該第一微電子裝置電氣連接到該第一微電子封裝體基體第一表面與以銲線把該第二微電子裝置電氣連接到該第二微電子封裝體基體第一表面中之至少一者。
在範例17中，範例8的標的能夠選擇地包括以黏著材料把該第一微電子封裝體微電子裝置的背面連接到該第二微電子封裝體微電子裝置的背面。
在範例18中，範例8至17中之任一者的標的能夠選擇地包括該包括一第二表面的第一微電子封裝體基體和該包括一第二表面的第二微電子封裝體基體，且更包括形成數個外部銲墊在該第一微電子封裝體基體第二表面與該第二微電子封裝體基體第二表面中之至少一者中或上。
在範例19中，一計算裝置可以包含一板；及一連接到該板的封裝體疊加堆疊式微電子結構，其中，該封裝體疊加堆疊式微電子結構包含一第一微電子封裝體，包含一具有一第一表面與至少一個形成於該微電子封裝體基體第一表面上之封裝體連接銲墊的基體，及具有至少一個電氣連接到該微電子封裝體基體第一表面的微電子裝置；一第二微電子封裝體，包含一具有一第一表面與至少一個形成於每一微電子封裝體基體第一表面上之封裝體連接銲墊的基體，及具有至少一個電氣地連接到該微電子封裝體基 體第一表面的微電子裝置；及至少一個延伸在該第一微電子封裝體連接銲墊與該第二微電子封裝體連接銲墊之間的封裝體-對-封裝體互連結構。
在範例20中，範例19的標的能夠選擇地包括一設置於該第一微電子封裝體基體第一表面與該第二微電子封裝體基體第一表面之間的封裝材料。
在範例21中，範例19或20的標的能夠選擇地包括以數個在一覆晶結構中之互連件連接到其各自之基體之該第一微電子封裝體微電子裝置與該第二微電子封裝體微電子裝置中之至少一者。
在範例22中，範例21的標的能夠選擇地包括一設置在該第一微電子封裝體微電子裝置與該第一微電子封裝體基體之的第一底填充材料，與一設置在該第二微電子封裝體微電子裝置與該第一微電子封裝體基體之間的第二底填充材料中之至少一者。
在範例23中，範例19或20的標的能夠選擇地包括以銲線連接到其各自之基體的該第一微電子封裝體微電子裝置與該第二微電子封裝體微電子裝置中之至少一者。
在範例24中，範例19的標的能夠選擇地包括以黏著材料把該第一微電子封裝體微電子裝置的背面連接到該第二微電子封裝體微電子裝置的背面。
在範例25中，範例19至24中之任一者的標的能夠選擇地包括該包括一第二表面的第一微電子封裝體基體和該包括一第二表面的第二微電子封裝體基體，且更包括數 個在該第一微電子封裝體基體第二表面與該第二微電子封裝體基體第二表面中之至少一者中或上的外部銲墊。
經過在本說明書之詳細實施例中的如此描述，會了解的是由後附申請專利範圍所界定的本說明書不受限定為在上述說明書中所陳述的特定細節，在沒有離開本說明書的精神和範疇之下，其之很多顯而易知的變化是有可能的。
110‧‧‧封裝體基體
112‧‧‧第一表面
114‧‧‧第二表面
116‧‧‧導電路徑
122‧‧‧銲墊
124‧‧‧銲墊
126‧‧‧銲墊

Claims (25)

  1. 一種封裝體疊加堆疊式微電子結構，包含：一第一微電子封裝體，包含一具有一第一表面與至少一個形成於該微電子封裝體基體第一表面上之封裝體連接銲墊的基體，且具有至少一個電氣連接到該微電子封裝體基體第一表面的微電子裝置；一第二微電子封裝體，包含一具有一第一表面與至少一個形成於該每一微電子封裝體基體第一表面上之封裝體連接銲墊的基體，且具有至少一個電氣連接到該微電子封裝體基體第一表面的微電子裝置；及至少一個延伸在該第一微電子封裝體連接銲墊與該第二微電子封裝體連接銲墊之間的封裝體-對-封裝體互連結構。
  2. 如請求項1之封裝體疊加堆疊式微電子結構，更包括一置於該第一微電子封裝體基體第一表面與該第二微電子封裝體基體第一表面之間的封裝材料。
  3. 如請求項1之封裝體疊加堆疊式微電子結構，其中，該第一微電子封裝體微電子裝置與該第二微電子封裝體微電子裝置中之至少一者是以數個在一覆晶結構中之互連件來連接到其各自的基體。
  4. 如請求項3之封裝體疊加堆疊式微電子結構，更包括設置在該第一微電子封裝體微電子裝置與該第一微電子封裝體基體之間的第一底填充材料，與設置在該第二微 電子封裝體微電子裝置與該第二微電子封裝體基體之間的第二底填充材料中之至少一者。
  5. 如請求項1之封裝體疊加堆疊式微電子結構，其中，該第一微電子封裝體微電子裝置與該第二微電子封裝體微電子裝置中之至少一者是以數條銲線連接到其各自的基體。
  6. 如請求項1之封裝體疊加堆疊式微電子結構，其中，該第一微電子封裝體微電子裝置的背面是以黏著材料連接到該第二微電子封裝體微電子裝置的背面。
  7. 如請求項1之封裝體疊加堆疊式微電子結構，其中，該第一微電子封裝體基體包括一第二表面而該第二微電子封裝體基體包括一第二表面，且更包括數個在該第一微電子封裝體基體第二表面與該第二微電子封裝體基體第二表面中之至少一者中或上的外部銲墊。
  8. 一種形成封裝體疊加堆疊式微電子結構的方法，包含：形成一第一微電子封裝體，包含一具有一第一表面與至少一個形成於該每一微電子封裝體基體第一表面上之封裝體連接銲墊的基體；把至少一個第一微電子裝置電氣連接到該微電子封裝體基體第一表面；形成一第二微電子封裝體，包含一具有一第一表面與至少一個形成於該每一微電子封裝體基體第一表面上之封裝體連接銲墊的基體；把至少一個第二微電子裝置電氣連接到該微電子封 裝體基體第一表面；把該第二微電子封裝體第一表面定向成面向該第一微電子封裝體第一表面；及形成至少一個封裝體-對-封裝體互連結構在該第一微電子封裝體連接銲墊與該第二微電子封裝體連接銲墊之間。
  9. 如請求項8之方法，其中，形成至少一個封裝體-對-封裝體互連結構在該第一微電子封裝體連接銲墊與該第二微電子封裝體連接銲墊之間包含形成一封裝體互連材料凸塊在其各自的第一微電子封裝體連接銲墊上、形成一封裝體互連材料凸塊在該第二微電子封裝體連接銲墊上、及把該第一微電子封裝體互連材料凸塊與該第二微電子封裝體互連材料凸塊連接在一起。
  10. 如請求項9所述之方法，其中，形成該封裝體互連材料凸塊於其各自的第一微電子封裝體連接銲墊上、形成該封裝體互連材料凸塊於該第二微電子封裝體連接銲墊上、及把該第一微電子封裝體互連材料凸塊與該第二微電子封裝體互連材料凸塊連接在一起包含形成一封裝體互連錫凸塊於其各自的第一微電子封裝體連接銲墊上、形成該封裝體互連錫凸塊於該第二微電子封裝體連接銲墊上、及迴焊該第一微電子封裝體互連錫凸塊與該第二微電子封裝體互連錫凸塊。
  11. 如請求項8所述之方法，更包括設置一封裝材料於該第一微電子封裝體基體第一表面與該第二微電子封裝體 基體第一表面之間。
  12. 如請求項8之方法，其中，把該第一微電子裝置電氣連接到該微電子封裝體基體第一表面包含以數個在一覆晶結構中的互連件把該第一微電子裝置電氣連接到該第一微電子封裝體基體第一表面。
  13. 如請求項12所述之方法，更包括設置一第一底填充材料在該第一微電子封裝體微電子裝置與該第一微電子封裝體基體之間。
  14. 如請求項8之方法，其中，把該第二微電子裝置電氣連接到該微電子封裝體基體第一表面包含以數個在一覆晶結構中之互連件把該第二微電子裝置電氣連接到該第二微電子封裝體基體第一表面。
  15. 如請求項14之方法，更包括設置一第二底填充材料在該第二微電子封裝體微電子裝置與該第二微電子封裝體基體之間。
  16. 如請求項8之方法，其中，把該第一微電子裝置電氣連接到該微電子封裝體基體第一表面與把該第二微電子裝置電氣連接到該微電子封裝體基體中之至少一者包含以數條銲線把該第一微電子裝置電氣連接到該第一微電子封裝體基體第一表面與以數條銲線把該第二微電子裝置電氣連接到該第二微電子封裝體基體第一表面中之至少一者。
  17. 如請求項8之方法，更包含以黏著材料把該第一微電子封裝體微電子裝置的背面連接到該第二微電子封裝體 微電子裝置的背面。
  18. 如請求項8之方法，其中，該第一微電子封裝體基體包括一第二表面且該第二微電子封裝體基體包括一第二表面，且更包括形成數個外部銲墊在該第一微電子封裝體基體第二表面與該第二微電子封裝體基體第二表面中之至少一者中或上。
  19. 一種計算裝置，包含：一板；及一連接到該板的封裝體疊加堆疊式微電子結構，其中，該封裝體疊加堆疊式微電子結構包含：一第一微電子封裝體，包含一具有一第一表面和至少一個形成於該微電子封裝體基體第一表面上之封裝體連接銲墊的基體，且具有至少一個電氣連接到該微電子封裝體基體第一表面的微電子裝置；一第二微電子封裝體，包含一具有一第一表面和至少一個形成於該每一微電子封裝體基體第一表面上之封裝體連接銲墊的基體，且具有至少一個電氣連接到該微電子封裝體基體第一表面的微電子裝置；及至少一個延伸在該第一微電子封裝體連接銲墊與該第二微電子封裝體連接銲墊之間的封裝體-對-封裝體互連結構。
  20. 如請求項19之計算裝置，更包括一設置在該第一微電子封裝體基體第一表面與該第二微電子封裝體基體第一 表面之間的封裝材料。
  21. 如請求項19之計算裝置，其中，該第一微電子封裝體微電子裝置與該第二微電子封裝體微電子裝置中之至少一者是以數個在一覆晶結構中的互連件來連接到其各自的基體。
  22. 如請求項21之計算裝置，更包括一設置於該第一微電子封裝體微電子裝置與該第一微電子封裝體基體之間的第一底填充材料，與一設置於該第二微電子封裝體微電子裝置與該第一微電子封裝體基體之間的第二底填充材料中之至少一者。
  23. 如請求項19之計算裝置，其中，該第一微電子封裝體微電子裝置與該第二微電子封裝體微電子裝置中之至少一者是以數條銲線來連接到其各自的基體。
  24. 如請求項19之計算裝置，其中，該第一微電子封裝體微電子裝置的背面是以黏著材料來連接到該第二微電子封裝體微電子裝置的背面。
  25. 如請求項19之計算裝置，其中，該第一微電子封裝體基體包括一第二表面且該第二微電子封裝體基體包括一第二表面，且更包括數個在該第一微電子封裝體基體第二表面與該第二微電子封裝體基體第二表面中之至少一者中或上的外部銲墊。
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