TW201535607A - 半導體裝置及製造半導體積體電路的方法 - Google Patents

半導體裝置及製造半導體積體電路的方法 Download PDF

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TW201535607A
TW201535607A TW103146199A TW103146199A TW201535607A TW 201535607 A TW201535607 A TW 201535607A TW 103146199 A TW103146199 A TW 103146199A TW 103146199 A TW103146199 A TW 103146199A TW 201535607 A TW201535607 A TW 201535607A
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depth
region
source
substrate
amorphous region
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Shiu-Ko Jangjian
Chun-Chieh Wang
Shih-Chieh Chang
Ying-Min Chou
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Taiwan Semiconductor Mfg Co Ltd
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Abstract

一種製造一半導體積體電路(IC)的方法被揭露。上述方法包括提供一基板。上述基板包括一閘極堆疊，位於上述基板的上方，且源/汲極區域藉由上述閘極堆疊彼此隔開。上述方法並且包括於上述源/汲極區域內的一第一深度形成具有一第一夾點的一第一位錯。於上述源/汲極區域內的一第二深度形成具有一第二夾點的一第二位錯。上述第二深度實質上小於上述第一深度。

Description

具有位錯的半導體積體電路
積體電路(IC)工業已歷經快速的成長。積體電路(IC)材料和設計的技術發展已使每一個積體電路世代的電路較前一個世代小且更複雜。在積體電路發展的過程中，當幾何尺寸(意即可利用一製程製造的最小元件(或線寬))縮小時，通常會增加功能密度(functional density)(意即每個晶片面積的相互連接元件的數量)。
這種尺寸微縮的製程通常藉由增加產率和降低相關成本而提供效益。這種尺寸微縮也增加積體電路製程和製造方法的複雜度。為了了解這些進展，積體電路製程和製造方法需要類似的發展。雖然對積體電路裝置的預期目的而言，製造積體電路裝置的存在問題已普遍滿足，但在所有方面仍未被完全令人滿意。舉例來說，需要應力效應來改善穿過電晶體通道的電荷遷移率，因而改善裝置性能。
根據以下的詳細說明並配合所附圖式做完整揭露。應注意的是，根據本產業的一般作業，圖示並未必按照比例繪製。事實上，可能任意的放大或縮小元件的尺寸，以做清楚的說明。
第1圖為依據本發明一些實施例構建之用以製造一半導體積體電路(IC)的一例示方法的一流程圖。
第2至11圖依據本發明一些實施例製程步驟構建的一積體電路裝置的剖面圖。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下的揭露內容敘述各個構件及其排列方式的特定範例，以簡化說明。當然，這些特定的範例並非用以限定。例如，若是本揭露書敘述了一第一特徵形成於一第二特徵之上或上方，即表示其可能包含上述第一特徵與上述第二特徵是直接接觸的實施例，亦可能包含了有附加特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與第二特徵可能未直接接觸的實施例。另外，以下揭露書不同範例可能重複使用相同的參考符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定所討論的不同實施例及/或結構之間有特定的關係。
此外，其與空間相關用詞。例如“在...下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用詞，係為了便於描述圖示中一個元件或特徵與另一個(些)元件或特徵之間的關係。除了在圖式中繪示的方位外，這些空間相關用詞意欲包含使用中或操作中的裝置之不同方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則在此使用的空間相關詞也可依此相同解釋。
第1圖為依據本發明一些實施例之製造一或多個 積體電路裝置的一方法100的一流程圖。上述方法100係詳細討論如後，且參照至一積體電路裝置200，為了舉例係顯示於第2至10圖中。
參考第1和2圖，上述方法開始於一步驟102，提供一基板210。上述基板210可為一塊狀矽基板。在另一實施例中，上述基板210可包括一元素半導體，例如結晶結構的矽或鍺；一化合物半導體，例如矽鍺(silicon germanium)(indium arsenide)、碳化矽(silicon carbide)、砷化鍺(gallium arsenic)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦及/或銻化銦(indium antimonide)，或前述組合。可能的基板210也包括一絕緣層上覆矽(SOI)基板。使用注氧隔離法(SIMOX)、晶片接合法及/或其他適合方法的隔離法來製造絕緣層上覆矽基板。
上述基板210依據常用的設計需求可包括多個摻雜區域。上述摻雜區域可為以p型摻質摻雜，例如硼或BF2；n型摻質，例如磷或砷；或前述組合。上述摻雜區域可直接形成於基板210上、在一P型井中、在一N型井中、在一雙井中、或使用一昇起式結構。上述基板210可更包括多個主動區，例如配置為一N型金屬-氧化物-半導體(NMOS)電晶體裝置的區域和配置為一P型金屬-氧化物-半導體(PMOS)電晶體裝置的區域。
上述基板210可包括隔絕區域212以隔絕上述基板210的主動區域。可使用常用隔絕技術形成上述隔絕區域212，例如淺溝槽隔絶(STI)，以定義和電性隔絕上述多個區域。上述 隔絕區域212包括氧化矽(silicon oxide)、氮化矽(silicon nitride)、氮氧化矽(silicon oxynitride)、一空氣間隙(an air gap)、其他適當材料、或前述組合。可利用任何適當製程形成上述隔絕區域212。在一實施例中，一淺溝槽隔絶的形成方式包括一曝光顯影製程、一蝕刻製程以於上述基板中蝕刻一溝槽(舉例來說，藉由使用一乾蝕刻及/或濕蝕刻)，和一沉積製程以使用一或多個介電材料填充上述溝槽(舉例來說，藉由使用一化學氣相沉積製程)。如目前的實施例中，可部分填充上述溝槽，其中殘留於溝槽之間的上述基板係形成一鰭狀結構。在一些實施例中，上述填充的溝槽可具有例如一熱氧化襯墊層和以氮化矽或氧化矽填充的一多層結構。
上述基板210包括位於上述基板210上方的一閘極堆疊220和沿著上述第一閘極堆疊220的側壁的一閘極間隙壁225。上述閘極堆疊220可包括一介電層和一閘極層。可藉由包括沉積製程、曝光顯影圖案化製程和蝕刻製程的一程序形成上述閘極堆疊220。上述沉積製程可包括化學氣相沉積法(CVD)、物理氣相沉積法(PVD)、原子層沉積法(ALD)、或其他適當的製程。上述曝光顯影製程可包括光阻塗佈(例如旋轉塗佈)、軟烤、光罩對準、曝光、曝光後烘烤、光阻顯影、清洗、乾燥(例如硬烤)、其他適當的製程及/或前述組合。上述蝕刻製程包括乾蝕刻法、濕蝕刻法及/或其他蝕刻法。
在目前的實施例中，上述第一閘極堆疊220為一虛設閘極堆疊且於後續製程被一高介電常數/金屬閘極(HK/MG)取代。上述虛設閘極堆疊220可包括上述介電層和上述多晶矽 層。
上述閘極間隙壁225包括例如氧化矽的一介電材料。在另一實施例中，上述閘極間隙壁225包括氮化矽、碳化矽、氮氧化矽或前述組合。可藉由於上述閘極堆疊220上方沉積一介電材料且之後非等向性蝕刻上述介電材料來形成上述閘極間隙壁225。位於上述閘極堆疊220下方的上述基板210中的一區域係視為一閘極區域230。
一旦接收上述基板210，上述基板210係於上述方法100的步驟104~120中經歷一應變記憶技術(SMT)。上述應變記憶技術係增加通過形成於閘極區域230中的一通道的電荷遷移率。前述技術藉由在一給定的通道尺寸和供應電壓下表現出較高的驅動強度而使元件性能顯著改善。簡而言之，上述應變記憶技術製程包括例如前非晶化佈植(PAI)、沉積應變記憶技術覆蓋層和高溫退火的製程。上述閘極區域230係保持由上述應變記憶技術造成的應力效應。這些保持的效應可視為應變記憶，因而命名為應變記憶技術。完成上述應變記憶技術之後，可進一步進行鰭式電晶體的製程步驟。
參考第1和3圖，進行上述方法100的步驟104，施行一第一前非晶化佈植以於上述基板210中的一源/汲極區域310內形成一第一非晶態區域320。上述源/汲極區域310為一區域，其係相鄰上述閘極堆疊220且與上述閘極堆疊220分開。上述非晶化佈植於上述源/汲極區域310的一頂部中注入原子。藉由導入例如矽(Si)、鍺(Ge)、氬(Ar)、氙(Xe)、BF2、砷(As)及/或銦(In)的能量(energetic)摻雜族群進入上述源/汲極區域 310，上述佈植會損傷分子晶格。會於上述源/汲極區域310往下至一第一深度d1的半導體材料內形成一非晶態區域320。依據設計規格決定上述第一深度d1，且可藉由第一前非晶化佈植的佈植能量、佈植族群、佈植角度及/或佈植劑量控制上述第一深度d1。上述源/汲極區域310可經歷使用多樣的能量、族群、角度及劑量的多重佈植製程。在本發明一實施例中，佈植的族群為鍺。
在本發明一些實施例中，可利用一圖案化光阻以定義上述第一非晶態區域320的形成位置和保護上述基板210的其他區域以避免佈植損傷。舉例來說，上述圖案化光阻於第一前非晶化佈植製程(形成上述第一非晶態區域320)係暴露上述源/汲極區域310，且於同時保護上述閘極堆疊220免於前非晶化佈植製程。
參考第1和4圖，進行上述方法100的步驟106，於上述基板210的上方，包括於上述第一非晶態區域320的上方形成一第一應變記憶技術覆蓋層330。在本發明一實施例中，上述第一應變記憶技術覆蓋層330係形成為一拉伸應力型薄膜。上述第一應變記憶技術覆蓋層330可包括氧化矽(silicon oxide)、氮化矽(silicon nitride)、氮氧化矽(oxynitride)、碳化矽(silicon carbide)、氧化鈦(titanium oxide)、氮化鈦(titanium nitride)、氧化鉭(tantalum oxide)、氮化鉭(tantalum nitride)或任何適合的材料。可由化學氣相沉積法(CVD)、物理氣相沉積法(PVD)或其他適當的製程上述第一應變記憶技術覆蓋層330。
參考第1和5圖，進行上述方法100的步驟108，對 上述基板210，包括對上述第一非晶態區域320施行一第一退火製程。上述第一退火製程使在非晶化佈植期間形成的上述第一非晶態區域320再結晶，而被視為一第一再結晶區域340。然而，在退火期間的一應力係妨得均勻結晶的形成。上述第一再結晶區域340會包含不規則物，例如區域為局部均一但其他區域表現出錯排。這種錯排可導致稱為位錯的缺陷。
由於在例如應變記憶技術層佈植、應變記憶技術層沉積和應變記憶技術層退火的應變記憶技術步驟期間會施加應力，上述第一再結晶區域340可在半導體晶格中包含位錯。位錯405開始於一第一夾點410。第一夾點410的深度和位置係依據設計規則設置，且與上述前非晶化佈植和退火製程相關。在本發明一實施例中，上述第一夾點410位於上述第一再結晶區域340的一底部角落，且上述第一再結晶區域340的底部角落位於第一深度d1。從上述第一夾點410，上述位錯405係沿著朝向上述源/汲極區域310的一頂面的一或多個平面傳播。
上述退火製程可為一快速高溫退火法(RTA)或例如一毫秒雷射高溫退火法的一毫秒退火法(MSA)。在本發明一實施例中，可於一快速高溫退火(RTA)工具中執行上述退火製程。在本發明另一實施例中，以範圍介於約2000℃和約1500℃之間的一退火溫度對上述基板210施行上述退火製程。在本發明另一實施例中，以範圍介於約5秒和約30秒之間的一退火持續時間對上述基板210施行上述退火製程。上述退火製程可包括一長時間預熱，其可最小化或甚至消除末端(EOR)缺陷。
參考第1和6圖，進行上述方法100的步驟110，移 除上述第一應變記憶技術覆蓋層330。上述移除製程可包括一濕蝕刻或一乾蝕刻製程。關於一實施例，利用包含磷酸的一蝕刻製程上述第一應變記憶技術覆蓋層330。關於另一實施例，利用氫氟酸(HF)或緩衝氫氟酸(buffered HF)蝕刻掉上述第一應變記憶技術覆蓋層330。
參考第1和7圖，進行上述方法100的步驟112，於上述第一再結晶區域340上方形成半導體層510。上述半導體層510包括單一元素半導體材料，例如鍺(Ge)或矽(Si)；或化合物半導體，例如砷化鎵(GaAs)、砷化鋁鎵(AlGaAs)；或半導體合金，例如矽鍺(SiGe)、磷化砷鎵(GaAsP)。可藉由一磊晶製程，例如化學氣相沉積(CVD)技術(舉例來說，氣相磊晶法(VPE)及/或超高真空化學氣相沉積法(UHV-CVD))、分子束磊晶法及/或其他適當的製程沉積上述半導體層510。在本發明一實施例中，於上述矽再結晶區域340上方選擇性形成矽鍺層510。
參考第1和8圖，進行上述方法100的步驟114，施行一第二前非晶化佈植，以於上述半導體層510中形成一第二非晶態區域520。上述第二前非晶化佈植在許多方面係類似於與第3圖相關的前述討論的上述第一前非晶化佈植。但是，相較於上述第一前非晶化佈植，係控制上述第二前非晶化佈植成為一較淺的佈植，且於上述半導體層510內往下至一第二深度d2形成上述第二非晶態區域520。依據設計規格決定上述第二深度d2，且可藉由第二前非晶化佈植的佈植能量、佈植族群、佈植角度及/或佈植劑量控制上述第二深度d2。上述源/汲極區域310可經歷使用多樣的能量、族群、角度及劑量的多重佈植 製程。上述第二深度d2實質上小於第一深度d1。在本發明一實施例中，佈植的族群為鍺(Ge)。
參考第1和9圖，進行上述方法100的步驟116，於上述基板210的上方，包括上述第二非晶態區域520的上方形成一第二應變記憶技術覆蓋層530。上述第二應變記憶技術覆蓋層530在許多方面係類似於與第4圖相關的前述討論的上述第一應變記憶技術覆蓋層330。在本發明一實施例中，上述第二應變記憶技術覆蓋層530係形成為一拉伸應力型薄膜。
參考第1和10圖，進行上述方法100的步驟118，對上述基板210，包括上述第二非晶態區域520施行一第二退火製程。上述第二退火製程在許多方面係類似於與第5圖相關的前述討論的上述第一退火製程。上述第二退火製程使在非晶化佈植期間形成的上述第二非晶態區域520再結晶，而被視為一第二再結晶區域540。在上述第二退火製程期間，第二位錯605開始位於一第二夾點610。第二夾點610的深度和位置係依據設計規則設置，且與上述第二前非晶化佈植和第二退火製程相關。在本發明一實施例中，上述第二夾點610位於上述第二再結晶區域540的一底部角落，且上述第二再結晶區域540的底部角落位於第二深度d2。從上述第二夾點610，上述位錯605係沿著朝向上述源/汲極區域310的一頂面的一或多個平面傳播。
參考第1和11圖，進行上述方法100的步驟120，移除上述第二應變記憶技術覆蓋層530。上述移除製程在許多方面係類似於與第6圖相關的前述討論的移除上述第一應變記憶技術覆蓋層330的製程。
可於上述方法100的之前、期間和之後提供額外的步驟，且可置換、去除和移動一些步驟以做為上述方法100的其他實施例。上述元件200可更經歷互補式金氧半導體(CMOS)或金氧半導體(MOS)技術製程以形成常用的多個元件和區域。
根據上述，本發明實施例提供製造積體電路裝置的方法。上述方法係採用形成雙重應變記憶技術(SMT)以提供一較高拉伸應力，以改善N型金氧半導體(NMOS)的通道遷移率。上述方法也採用使用矽鍺的優異選擇性，以易於N型金氧半導體的源極和汲極矽表面上沉積且不需額外遮罩。
本揭露係提供製造一半導體積體電路之許多不同的實施例，其提供優於其他現有方法的一或多個改善。在本發明一實施例中，一種製造一半導體積體電路(IC)的方法包括提供一基板。上述基板包括一閘極堆疊，位於上述基板的上方，且源/汲極區域藉由上述閘極堆疊彼此隔開。上述方法並且包括於上述源/汲極區域的一第一深度形成具有一第一夾點的一第一位錯，以及於上述源/汲極區域的一第二深度形成具有一第二夾點的一第二位錯。上述第二深度實質上小於上述第一深度。
在本發明另一實施例中，一種製造一半導體積體電路(IC)的方法包括提供一基板。上述基板包括一閘極堆疊，位於上述基板的上方，且源/汲極區域藉由上述閘極堆疊彼此隔開。上述方法並且包括對上述源/汲極區域施行一第一非晶化前植入製程(PAI)以形成一第一非晶態區域，且於上述基板上方，包括於上述第一非晶態區域上方形成一第一覆蓋層。上述 方法並且包括對上述第一非晶態區域施行一第一退火製程以從上述源/汲極區的一頂面的一第一深度形成具有一第一夾點的一第一位錯。上述方法並且包括移除上述第一覆蓋層，於上述第一非晶態區域上方形成一半導體層，對半導體層施行一第二非晶化前植入製程(PAI)以形成一第二非晶態區域。上述方法並且包括於上述基板上方，包括上述第二非晶態區域形成一第二覆蓋層；對上述第二非晶態區域施行一第二退火製程，其中控制上述第二退火製程以從上述源/汲極區的一頂面的一第二深度形成具有一第二夾點的一第二位錯。上述方法並且包括移除上述第二覆蓋層。
在本發明又一實施例中，一種半導體積體電路(IC)裝置包括一基板，一源極區域位於上述基板上方，一汲極區域位於上述基板上方，藉由一閘極區域與上述源極區域隔開。上述裝置並且包括一第一位錯，形成於從上述源極/汲極區域的一頂面的一第一深度的上述源極/汲極區域內。上述裝置並且包括一第二位錯，形成於從上述源極/汲極區域的上述頂面的一第二深度的上述源極/汲極區域內。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下，可 對本揭露進行各種改變、置換或修改。

Claims (20)

  1. 一種製造半導體積體電路(IC)的方法，該方法包括：提供一基板，包括；一閘極堆疊，位於該基板的上方；以及源/汲極區域，藉由該閘極堆疊彼此隔開；於該源/汲極區域的一第一深度形成具有一第一夾點的一第一位錯；以及於該源/汲極區域的一第二深度形成具有一第二夾點的一第二位錯，其中該第二深度實質上小於該第一深度。
  2. 如申請專利範圍第1項所述之方法，其中具有該第一夾點的該第一位錯包括：對該源/汲極區域施行一第一非晶化前植入製程(PAI)以形成一第一非晶態區域，其中控制該第一非晶化前植入製程以形成具有一深度的該第一非晶態區域，該深度等於該第一深度；於該基板上方，包括於該第一非晶態區域上方形成一第一覆蓋層；對該第一非晶態區域施行一第一退火製程，其中控制該第一退火製程以於該第一深度形成具有該第一夾點的該第一位錯；以及移除該第一覆蓋層。
  3. 如申請專利範圍第2項所述之方法，其中該第一非晶化前植入製程植入鍺族。
  4. 如申請專利範圍第2項所述之方法，其中該第一覆蓋層係形 成為一拉伸應力型薄膜。
  5. 如申請專利範圍第1項所述之方法，其中形成具有該第二夾點的該第二位錯包括：於該第一非晶態區域上方形成一半導體層；對半導體層施行一第二非晶化前植入製程(PAI)以形成一第二非晶態區域，其中控制該第二非晶化前植入製程以形成具有一深度的該第二非晶態區域，該深度等於該第二深度；於該基板上方，包括於該第二非晶態區域上方形成一第二覆蓋層；對該第二非晶態區域施行一第二退火製程，其中控制該第二退火製程以於該第二深度形成具有該第二夾點的該第二位錯；以及移除該第二覆蓋層。
  6. 如申請專利範圍第5項所述之方法，其中該矽鍺層係藉由一選擇沉積製程形成於該第一非晶態區域上方。
  7. 如申請專利範圍第5項所述之方法，其中該第一非晶化前植入製程植入鍺族。
  8. 如申請專利範圍第5項所述之方法，其中該第二覆蓋層係形成為一拉伸應力型薄膜。
  9. 如申請專利範圍第5項所述之方法，其中該第二非晶化前植入製程植入鍺族。
  10. 一種製造半導體積體電路(IC)的方法，該方法包括：提供一基板，包括；一閘極堆疊，位於該基板的上方；以及 源/汲極區域，藉由該閘極堆疊彼此隔開；對該源/汲極區域施行一第一非晶化前植入製程(PAI)以形成一第一非晶態區域；於該基板上方，包括於該第一非晶態區域上方形成一第一覆蓋層；對該第一非晶態區域施行一第一退火製程以從該源/汲極區的一頂面的一第一深度形成具有一第一夾點的一第一位錯；移除該第一覆蓋層；於該第一非晶態區域上方形成一半導體層；對半導體層施行一第二非晶化前植入製程(PAI)以形成一第二非晶態區域；於該基板上方，包括該第二非晶態區域形成一第二覆蓋層；對該第二非晶態區域施行一第二退火製程，其中控制該第二退火製程以從該源/汲極區的一頂面的一第二深度形成具有一第二夾點的一第二位錯；以及移除該第二覆蓋層。
  11. 如申請專利範圍第10項所述之方法，其中該第一覆蓋層係形成為一拉伸應力型薄膜。
  12. 如申請專利範圍第10項所述之方法，其中控制該第一退火製程以於該第一深度形成具有該第一夾點的該第一位錯。
  13. 如申請專利範圍第10項所述之方法，其中該第一非晶化前植入製程植入鍺族。
  14. 如申請專利範圍第10項所述之方法，其中該矽鍺層係藉由 一選擇沉積製程形成於該第一非晶態區域上方。
  15. 如申請專利範圍第10項所述之方法，其中該第二非晶化前植入製程以形成具有一深度的該第二非晶態區域，該深度等於該第二深度。
  16. 如申請專利範圍第10項所述之方法，其中該第二覆蓋層係形成為一拉伸應力型薄膜。
  17. 如申請專利範圍第10項所述之方法，其中控制該第二退火製程以於該第二深度形成具有該第二夾點的該第二位錯。
  18. 如申請專利範圍第10項所述之方法，其中該第二非晶化前植入製程植入鍺族。
  19. 一種半導體裝置，包括：一基板；一源極區域，位於該基板上方；一汲極區域，位於該基板上方，藉由一閘極區域與該源極區域隔開；一第一位錯，形成於從該源極/汲極區域的一頂面的一第一深度的該源極/汲極區域內；以及一第二位錯，形成於從該源極/汲極區域的該頂面的一第二深度的該源極/汲極區域內。
  20. 如申請專利範圍第19項所述之半導體裝置，其中該第二深度實質上小於該第一深度。
TW103146199A 2014-03-07 2014-12-30 半導體裝置及製造半導體積體電路的方法 TWI555126B (zh)

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