WO2014008691A1 - 半导体器件制造方法 - Google Patents

半导体器件制造方法 Download PDF

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Publication number
WO2014008691A1
WO2014008691A1 PCT/CN2012/079454 CN2012079454W WO2014008691A1 WO 2014008691 A1 WO2014008691 A1 WO 2014008691A1 CN 2012079454 W CN2012079454 W CN 2012079454W WO 2014008691 A1 WO2014008691 A1 WO 2014008691A1
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layer
source region
region
forming
gate
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PCT/CN2012/079454
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English (en)
French (fr)
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尹海洲
朱慧珑
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中国科学院微电子研究所
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Priority to US14/413,697 priority Critical patent/US20150171186A1/en
Publication of WO2014008691A1 publication Critical patent/WO2014008691A1/zh

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Definitions

  • the present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly to a method of fabricating a semiconductor device, particularly a method of fabricating a MOSFET having an asymmetric source-drain structure. Background technique
  • the source-drain parasitic resistance is much smaller than the channel region resistance in the long channel and can be ignored, but as the device scales down and the intrinsic resistance of the channel region decreases, the source-drain resistance, especially the contact resistance decreases with size.
  • the rapid increase causes the equivalent operating voltage to drop.
  • parasitic capacitances between the source and drain and the gate including parasitic capacitance caused by the gate electric field passing through the sidewalls and interlayer dielectrics entering the source and drain regions due to the fringe field effect. These parasitic capacitances can cause device response. The speed is degraded, reducing the high frequency performance of the device. It is therefore necessary to reduce these parasitic resistances and parasitic capacitances.
  • Measures taken in the prior art to reduce parasitic effects include forming a metal silicide in/over the source/drain regions or both increasing the source and drain while reducing the parasitic resistance of the source and drain regions, and also including precise control. Gate height, gate sidewall lines, and gate sidewall components to reduce parasitic capacitance.
  • the above processes are the same on both sides of the source and drain regions, that is, the device structure formed is symmetrical.
  • the increase of the source and drain increases the edge parasitic capacitance by reducing the distance of the power line from the gate to the source and drain through the gate.
  • the capping capacitance between the gate and the drain is a Miller capacitance that is connected between the input gate and the output drain, which is amplified by the amplifier in the inverting amplifier circuit. Therefore, the capacitance equivalent to the input terminal is expanded by 1+K times (K is the voltage amplification factor of the amplification circuit of the stage), so the drain side parasitic capacitance has a greater influence on the device performance than the source due to the Mi ller effect.
  • the source-side parasitic resistance changes the source-side voltage when the device is turned on, thereby changing the gate-source voltage, the gate-source voltage is lowered for the NMOS, and the absolute value of the gate-source voltage is lowered for the PM0S. This will increase the channel resistance and reduce the channel charge, thereby reducing the drive current and affecting device performance.
  • the influence of the parasitic resistance of the drain terminal on the drain terminal voltage does not affect the gate-source voltage, which has little effect on device performance. Therefore, in general, the parasitic resistance on the source side has a greater influence on the device performance than the parasitic resistance on the drain side.
  • the MOSFET having a symmetrical structure in the prior art does not take into account the difference in parasitic effects between the source and drain regions described above, and further restricts device performance. Summary of the invention
  • an object of the present invention is to provide a method for fabricating a semiconductor device, particularly a method for fabricating a MOSFET having an asymmetric source/drain structure, to reduce parasitic resistance on the source side and drain side parasitization in a targeted manner. capacitance.
  • the above object of the present invention is to provide a semiconductor device manufacturing method including: forming a gate stack structure and a gate spacer on a substrate, and a gate stack structure and a gate side wall A source region and a drain region are respectively formed in the bottom; a barrier layer is selectively formed on the drain region, wherein the barrier layer covers the drain region and exposes the source region; an elevated source region is epitaxially formed on the exposed source region; and the barrier layer is removed.
  • barrier material is different from the substrate material.
  • the step of selectively forming the barrier layer on the drain region further comprises: forming a barrier material layer over the entire device; forming a photoresist pattern on the barrier material layer, covering the barrier material layer on the drain region and exposing a barrier material layer on the source region; etching the barrier material layer on the exposed source region leaving only a portion of the barrier material layer on the drain region to form a barrier layer; removing the photoresist pattern.
  • the boost source region includes S i , S iGe , S i : C, and a combination thereof.
  • the doping is performed in situ while forming the elevated source region, or the doping is implanted after forming the elevated source region, such that the elevated source region and the source region are of the same conductivity type.
  • the method further comprises: forming a metal silicide on the drain region and the lift source region; forming an interlayer dielectric layer on the entire device; etching the interlayer dielectric layer until the metal silicide is exposed, forming a source Leakage contact hole; depositing source and drain contact plugs in the source and drain contact holes.
  • the gate stack structure is a dummy gate stack structure, including a pad oxide layer of silicon oxide and a dummy gate fill layer of polysilicon, amorphous silicon, silicon oxide.
  • the method further comprises: planarizing the interlayer dielectric layer and the dummy gate stack structure until the gate filling layer is exposed; removing the gate filling layer to form a gate a trench; a success function adjustment layer and a resistance adjustment layer in the gate trench.
  • the source region and/or the drain region comprise a lightly doped extension region and a heavily doped region.
  • the lift source region is selectively formed only on one side of the source region to constitute an asymmetric device structure, and the parasitic resistance on the source region side and the parasitic capacitance on the drain side are reduced in a targeted manner. Effectively improve device performance.
  • FIG. 1 is a flow chart of a method of fabricating a semiconductor device in accordance with the present invention
  • a gate stack structure and a gate spacer are formed on the substrate, and a source region and a drain region are respectively formed in the gate stack structure and the substrate bottom sides of the gate sidewall.
  • the substrate 1 is provided, and the material thereof may be (body) S i (for example, single crystal Si wafer), S0I, GeOI (Ge on insulator), or other compound semiconductors such as GaAs, S iGe, GeSn, InP, InSb, GaN, etc.
  • the substrate 1 is selected from a body S i or SOI for compatibility with a CMOS process.
  • the etched substrate 1 is formed into a shallow trench and then deposited with an insulating material such as silicon oxide to form a shallow trench isolation (STI) 1A, and the substrate 1 region surrounded by the STI 1A constitutes an active region of the device.
  • STI shallow trench isolation
  • a conventional deposition method such as LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputtering, etc., sequentially depositing on the active region and then etching to form the gate insulating layer 2A, the gate filling layer 2B, and A gate cap layer 2C is preferred.
  • the dummy gate insulating layer 2 A is a pad oxide layer of silicon oxide
  • the dummy gate filling layer 2B is polysilicon, amorphous silicon, or even Is a silicon oxide
  • the gate insulating layer 2A is a high-k material including, but not limited to, nitrides (eg, SiN, A1N, TiN), metal oxides (mainly sub-group and lanthanide metal element oxides such as A1 2 0 3 , Ta 2 0 5 , Ti0 2 , Zn0, Zr0 2 , Hf0 2 , Ce0 2 , Y 2 0 3 , La 2 0 3 ), perovs
  • a gate insulating layer surrounds the bottom and sides of the gate fill layer (not shown). It should be noted that although the following embodiment of the present invention is directed to the back gate process, that is, the gate stack structure in FIG. 2 is a dummy gate stack structure, the present invention may also employ a front gate process.
  • the front gate process gate stack structure differs from the fill metal species and the back gate process. Since the current mainstream process is a back gate process, it will not be described in detail here.
  • the first source/drain implantation is performed symmetrically in the village substrate 1 on both sides of the gate stack structure 2 composed of the gate insulating layer 2A, the gate filling layer 2B, and the gate cap layer 2C.
  • Low energy and dose injection of impurities such as B, P, Ga, Al, N, etc. form a lightly doped source region 3LS and a lightly doped drain region 3LD (these lightly doped source and drain regions, ie, source and drain extension regions)
  • the LDD structure can suppress the thermoelectric effect).
  • the implant dose and energy are reasonably set according to the depth of the junction and the type and concentration of conductivity. Annealing may be employed to activate the implanted impurities.
  • silicon nitride, silicon oxide, silicon oxynitride, and the like are formed by post-deposition etching.
  • a second source-drain implantation symmetrically implanting the same conductivity type with higher energy and dose in the village 1 (source region 3LS, drain region 3LD) on both sides of the gate spacer 4
  • the impurities form a heavily doped source region 3HS and a heavily doped drain region 3HD.
  • Annealing can be employed again to activate the implanted impurities.
  • a barrier layer is selectively formed on the drain region, covering one side of the drain region and exposing the source region side.
  • a barrier material layer 5 is deposited over the entire device.
  • the barrier material layer 5 is deposited on the STI 1A, the source region 3HS, the gate spacer 4, the gate cap layer 2C, and the drain region 3HD by a conventional method such as LPCVD PECVD HDPCVD or MBE ALD.
  • the material of the barrier material layer 5 includes silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, and may be a single layer or a composite laminated structure of these materials.
  • the barrier material can be any material that is different from the source and drain regions.
  • the barrier material layer 5 may be silicon oxide or silicon oxynitride.
  • the barrier material layer 5 serves as a barrier material for subsequent epitaxial formation of the lift source region, and the substrate/source/drain region material cannot be epitaxially grown on the region covered by the barrier layer.
  • the thickness of the barrier material layer 5 is set according to the needs of the epitaxial process, for example, 5 ⁇ 30
  • a mask pattern 6 on the side of the barrier material layer on which the source region is exposed is formed.
  • the barrier material layer 5 spin coating, spraying, screen printing, for example, a soft mask pattern of the photoresist, after exposure and development, the photoresist on the source side is removed, and only the side of the drain region remains.
  • Photoresist pattern 6 wherein (photoresist) mask pattern 6 can occupy exactly half of the drain region and half of the gate stack structure with the center axis of the device as shown in FIG. 4, but other forms can also be adopted.
  • the left boundary of the photoresist pattern 6 is located to the right of the left side surface of the left gate side wall 4 and is located at the right side of the right gate side wall 4
  • the right border of the photoresist pattern 6 is located to the right of the right side of the drain region 3HD.
  • the exposed barrier material layer 5 is etched until the source region 3HS is exposed (and the gate side is dry etching or wet etching. Dry etching includes plasma etching, reactive ions)
  • the etching gas may be a fluorine-based gas (a fluorocarbon-based gas such as CF 4 CHF 3 CH 3 F CH 2 F 2 ; NF 3 ; SF 6 ), C 1 2 /HC K Br 2 /HBr, oxygen, The rare gas (Ar He ) and combinations thereof.
  • the wet etching etching solution may include HF HF: ⁇ 4 FH 2 0 2 H 2 S0 4 HN0 3 and combinations thereof.
  • the etching may also be dry etching and wet etching. a combination of etching, such as a dry first wet method, or a different dry etching combination, wet etching combination, or dry and wet etching for the stacked barrier material layer 5. Hehe. As described above, the material of the barrier material 5 is different from that of the spacer 4 and the etch stop layer 2C, so that the sidewall 4 and the etch stop layer 2C are not etched during the etching.
  • the mask pattern 6 is removed, and a barrier layer 5D is left on the side of the drain region 3HD.
  • the method of removing the photoresist may be organic solvent dissolution, inorganic solvent oxidation, or oxygen plasma ashing.
  • an elevation source region is epitaxially grown on the source region.
  • the source region 3RS is epitaxially grown on the exposed source region 3HS by methods such as MBE, ALD, and MOCVD. Since the STI 1A and the gate side extension occur only on the source region 3HS, they are also referred to as selective extension.
  • Enhance the source area 3RS material including S i, S iGe, S i: C and combinations thereof.
  • S iGe, S i: C is employed to apply stress to the channel region and increase carrier mobility in the channel region.
  • in-situ doping causes the lift source region 3RS to have the same conductivity type as the source region 3HS.
  • doping ion implantation is performed again and then annealed to activate the impurity so that the lift source region 3RS has the same conductivity type as the source region 3HS.
  • the barrier layer 5D no lift drain region is formed on the drain region 3HD, so the power line of the gate 2B does not additionally penetrate into the lift drain region to cause an increase in parasitic capacitance, that is, no lift drain region is formed.
  • the parasitic capacitance on the side of the drain region is reduced.
  • the boost source region 3RS on the source side increases the source region area, increases the doping concentration, and reduces the parasitic resistance, thereby further improving device performance.
  • the barrier layer 5D is removed. According to the material of the barrier layer 5D, the remaining barrier layer 5D is removed by the same process as that shown in FIG. Subsequently, a subsequent MOSFET fabrication process (not shown) can be completed, for example, including forming a metal silicide on the elevated source region 3RS and the drain region 3HD to further lower the contact resistance, forming an interlayer dielectric layer (ILD) over the entire device, The ILD is etched until a metal silicide is exposed to form a source/drain contact hole, and a metal/metal nitride is deposited in the source/drain contact hole to form a source/drain contact plug or the like.
  • a subsequent MOSFET fabrication process (not shown) can be completed, for example, including forming a metal silicide on the elevated source region 3RS and the drain region 3HD to further lower the contact resistance, forming an interlayer dielectric layer (ILD) over the entire device, The ILD is etched until a metal silicide is exposed to
  • the method further includes: planarizing the interlayer dielectric layer and the dummy gate stack structure until the gate filling layer is exposed; removing the gate filling layer Forming a gate trench; forming a success function adjustment layer and a resistance adjustment layer in the gate trench.
  • the work function adjusting layer and the resistance adjusting layer metal are as described above.
  • the lift source region is selectively formed only on one side of the source region to constitute an asymmetric device structure, and the parasitic resistance on the source region side and the parasitic capacitance on the drain side are reduced in a targeted manner. Effectively improve device performance.

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Abstract

提供一种半导体器件制造方法，包括：在衬底（1）上形成栅极堆叠结构（2）以及栅极侧墙（4），在栅极堆叠结构（2）以及栅极侧墙（4）两侧衬底（1）中分别形成源区（3LS，3HS）和漏区（3LD，3HD）；在漏区上选择性形成阻挡层（5），其中阻挡层（5）覆盖漏区（3LD，3HD）并且暴露源区（3LS，3HS）；在暴露的源区（3LS，3HS）上外延形成提升源区（3RS）；去除阻挡层（5D）。该半导体器件制造方法，选择性地仅在源区一侧形成提升源区从而构成非对称器件结构，针对性减小源区一侧寄生电阻以及漏极一侧寄生电容，有效提高了器件性能。

Description

半导体器件制造方法
[0001] 本申请要求了 2012年 7月 11日提交的、 申请号为 201210239480. 8、 发 明名称为 "半导体器件制造方法" 的中国专利申请的优先权， 其全部内容 通过引用结合在本申请中。 技术领域
[0002] 本发明涉及半导体集成电路制造领域， 更具体地， 涉及一种半导体 器件制造方法尤其是具有非对称源漏结构的 M0SFET的制造方法。 背景技术
[0003] 随着集成电路工艺持续发展， 特别是器件尺寸不断等比例缩减， 传 统的 M0SFET中各种寄生效应变得越来越突出。 例如源漏寄生电阻在长沟道 时远小于沟道区电阻而可以忽略， 但是随着器件等比例缩小、 沟道区本征 电阻减小， 源漏区电阻特别是接触电阻随着尺寸减小而迅速增加， 使得等 效工作电压下降。 此外， 源漏与栅极之间还存在寄生电容， 其中包括由于 边缘电场效应， 栅极电力线穿过侧墙、 层间介质等进入源漏区而引起的寄 生电容， 这些寄生电容可以导致器件响应速度恶化， 降低器件高频性能。 因此需要减小上述这些寄生电阻和寄生电容。
[0004] 现有技术中对于减小寄生效应采取的措施包括在源漏区中 /上均形 成金属硅化物或者均提升源漏来同时减小源区、 漏区的寄生电阻， 还包括 精确控制栅极高度、 栅极侧墙线条、 栅极侧墙组分以减少寄生电容。
[0005] 然而上述这些方法在源区和漏区两侧上处理工艺都是相同的， 也即 形成的器件结构是对称的。 并且， 提升源漏由于减少了电力线由栅极穿过 侧墙至源漏的距离， 会增加边缘寄生电容。 实际上， 栅极与漏极之间的覆 盖电容是跨接在输入端栅极与输出端漏极之间的密勒 （Mi l l er ) 电容， 在 反相放大电路中会因为放大器的放大作用而使得等效到输入端的电容值会 扩大 1+K倍（K是该级放大电路电压放大倍数）， 因此由于这种 Mi l ler效应使 得漏极一侧寄生电容对于器件性能的影响要大于源极一侧寄生电容的影 响。 此外， 由于在器件开启情况下， 源端寄生电阻使源端电压发生变化， 从而改变栅源电压， 对丽 OS来说降低了栅源电压， 对 PM0S来说降低了栅源 电压的绝对值。 这将增大沟道电阻、 减少沟道电荷， 从而降低驱动电流、 影响器件性能。 相对的， 漏端寄生电阻对漏端电压的影响不会影响到栅源 电压， 对器件性能影响较小。 因此总的来说， 在源极一侧寄生电阻对于器 件性能的影响则要大于漏极一侧寄生电阻的影响。
[0006] 因此， 现有技术中具有对称结构的 M0SFET并未考虑到上述源、 漏区 之间寄生效应的差异， 制约器件性能进一步提高。 发明内容
[0007] 有鉴于此， 本发明的目的在于提供一种半导体器件制造方法尤其是 具有非对称源漏结构的 M0SFET的制造方法， 以针对性减小源区一侧寄生电 阻以及漏极一侧寄生电容。
[0008] 实现本发明的上述目的， 是通过提供一种半导体器件制造方法， 包 括： 在村底上形成栅极堆叠结构以及栅极侧墙， 在栅极堆叠结构以及栅极 侧墙两侧村底中分别形成源区和漏区； 在漏区上选择性形成阻挡层， 其中 阻挡层覆盖漏区并且暴露源区； 在暴露的源区上外延形成提升源区； 去除 阻挡层。
[ 0009] 其中， 阻挡层材料与村底材料不同。
[001 0] 其中， 在漏区上选择性形成阻挡层的步骤进一步包括： 在整个器件 上形成阻挡材料层； 在阻挡材料层上形成光刻胶图形， 覆盖漏区上的阻挡 材料层并且暴露源区上的阻挡材料层； 刻蚀暴露的源区上的阻挡材料层， 仅留下漏区上的部分阻挡材料层而构成阻挡层； 去除光刻胶图形。
[001 1 ] 其中， 提升源区包括 S i、 S iGe、 S i : C及其组合。
[0012] 其中， 在形成提升源区的同时原位掺杂， 或者在形成提升源区之后 注入掺杂， 使得提升源区与源区导电类型相同。
[001 3] 其中， 去除阻挡层之后还包括： 在漏区和提升源区上形成金属硅化 物； 在整个器件上形成层间介质层； 刻蚀层间介质层直至暴露金属硅化物， 形成源漏接触孔； 在源漏接触孔中沉积形成源漏接触塞。 [0014] 其中， 栅极堆叠结构为假栅极堆叠结构， 包括氧化硅的垫氧化层以 及多晶硅、 非晶硅、 氧化硅的假栅极填充层。
[0015] 其中， 在形成层间介质之后， 刻蚀层间介质之前还可包括： 平坦化 层间介质层以及假栅极堆叠结构直至暴露栅极填充层； 去除栅极填充层， 形成栅极沟槽； 栅极沟槽中形成功函数调节层和电阻调节层。
[0016] 其中， 源区和 /或漏区包括轻掺杂的延伸区以及重掺杂区。
[0017] 其中， 源区与漏区对称。
[0018] 依照本发明的半导体器件制造方法， 选择性地仅在源区一侧形成提 升源区从而构成非对称器件结构， 针对性减小源区一侧寄生电阻以及漏极 一侧寄生电容， 有效提高了器件性能。 附图说明
[0019] 以下参照附图来详细说明本发明的技术方案， 其中：
[0020] 图 1为根据本发明的半导体器件制造方法的流程图； 以及
具体实施方式
[0022] 以下参照附图并结合示意性的实施例来详细说明本发明技术方案的 特征及其技术效果。 需要指出的是， 类似的附图标记表示类似的结构， 本 申请中所用的术语 "第一"、 "第二"、 "上"、 "下"、 "厚"、 "薄" 等等可用 于修饰各种器件结构。 这些修饰除非特别说明并非暗示所修饰器件结构的 空间、 次序或层级关系。
[0023] 参照图 1以及图 2 , 在村底上形成栅极堆叠结构以及栅极侧墙， 在栅 极堆叠结构以及栅极侧墙两侧村底中分别形成源区和漏区。
[0024] 提供村底 1 , 其材质可以是（体） S i (例如单晶 S i晶片）、 S0I、 GeOI (绝缘体上 Ge ),也可以是其他化合物半导体，例如 GaAs、 S iGe、 GeSn、 InP、 InSb、 GaN等等。 优选地， 村底 1选用体 S i或 SOI , 以便与 CMOS工艺兼容。 优 选地，刻蚀村底 1形成浅沟槽并随后沉积填充氧化硅等绝缘材料而形成浅沟 槽隔离 （STI ) 1A, STI 1A包围的村底 1区域构成器件的有源区。 [0025] 采用 LPCVD、 PECVD、 HDPCVD, M0CVD、 MBE、 ALD、 蒸发、 溅射等常规 沉积方法， 在有源区上依次沉积并且随后刻蚀形成栅极绝缘层 2A、 栅极填 充层 2B、 以及优选地栅极盖层 2C。 当栅极堆叠结构采用后栅工艺时， 也即 用作假栅极堆叠结构， 假栅极绝缘层 2 A是氧化硅的垫氧化层， 假栅极填充 层 2B是多晶硅、 非晶硅、 甚至可以是氧化硅， 随后工艺中刻蚀去除假栅极 堆叠结构形成栅极沟槽，在栅极沟槽中依次填充高 k材料的栅极绝缘层以及 金属材料的栅极填充层，栅极绝缘层 2A是高 k材料，包括但不限于氮化物（例 如 SiN、 A1N、 TiN)、 金属氧化物 （主要为副族和镧系金属元素氧化物， 例 如 A1203、 Ta205、 Ti02、 Zn0、 Zr02、 Hf02、 Ce02、 Y203、 La203 )、 钙钛矿相氧化 物 （例如 PbZrxTihO; ( PZT)、 Ba.Sri-JiOs ( BST ) ); 栅极填充层 2B是金属、 金属氮化物及其组合， 其中金属包括 Al、 Ti、 Cu、 Mo、 W、 Ta以用作栅极填 充层（电阻调节层）， 金属氮化物包括 TiN、 TaN以用作功函数调节层； 栅极 盖层 2C是氮化硅， 用作栅极刻蚀的硬掩模。 栅极绝缘层包围了栅极填充层 的底部以及侧面（未示出）。 值得注意的是， 虽然以下本发明实施例中针对 的是后栅工艺也即图 2中的栅极堆叠结构是假栅极堆叠结构，但是本发明也 可以采用前栅工艺。 前栅工艺栅极堆栈结构与填充金属种类与后栅工艺不 同。 由于目前主流工艺是后栅工艺， 此处不详细描述。
[0026] 可选地， 执行第一次源漏注入， 在栅极绝缘层 2A、 栅极填充层 2B、 栅极盖层 2C构成的栅极堆叠结构 2两侧的村底 1中对称地以较低能量和剂量 注入 B、 P、 Ga、 Al、 N等及其组合的杂质形成轻掺杂源区 3LS以及轻掺杂漏 区 3LD (这些轻掺杂源漏区也即源漏延伸区构成 LDD结构， 可以抑制热电子 效应）。 注入剂量和能量依照结深以及导电类型和浓度大小需要而合理设 定。 可以采用退火以激活注入的杂质。
[0027] 在栅极绝缘层 2A、 栅极填充层 2B、 栅极盖层 2C构成的栅极堆叠结构 2 的两侧通过沉积后刻蚀形成了包括氮化硅、 氧化硅、 氮氧化硅、 类金刚石 无定形碳（DLC )及其组合的材质的栅极侧墙 4。
[0028] 可选地，执行第二次源漏注入，在栅极侧墙 4两侧的村底 1 (源区 3LS、 漏区 3LD )中对称地以较高能量和剂量注入相同导电类型的杂质以形成重掺 杂源区 3HS以及重掺杂漏区 3HD。 可以再次采用退火以激活注入的杂质。 [0029] 参照图 1以及图 3至图 6 , 在漏区上选择性形成阻挡层， 覆盖了漏区一 侧并且暴露了源区一侧。
[0030] 参照图 3 , 在整个器件上沉积阻挡材料层 5。 例如通过 LPCVD PECVD HDPCVD, MBE ALD等常规方法， 在 STI 1A、 源区 3HS、 栅极侧墙 4、 栅极盖 层 2C、 漏区 3HD上沉积阻挡材料层 5。 阻挡材料层 5的材质包括氧化硅、 氮化 硅、 氮氧化硅及其组合， 可以是单层也可以是这些材料的复合层叠结构。 原则上， 阻挡层材料可以是一切与源区、 漏区不同的材料。 为了保证栅极 源端侧墙以及栅极盖层（刻蚀停止层） 2C不被刻蚀， 应保证阻挡材料 5与侧 墙 4以及刻蚀停止层 2C的材料均不同。 例如， 村底 1、 源区、 漏区为 S i , 侧 墙 4、 盖层 2C为 S iN时， 阻挡材料层 5可以是氧化硅或氮氧化硅。 阻挡材料层 5用作后续外延形成提升源区的阻挡材料，被该阻挡层覆盖的区域上将无法 外延生长村底 /源漏区材料。 阻挡材料层 5的厚度依照外延工艺需要而设定， 例如是 5 ~ 30
[0031] 参照图 4 , 在阻挡材料层 5上形成暴露了源区一侧的掩模图形 6。 在阻 挡材料层 5上旋涂、 喷涂、 丝网印刷例如是光刻胶的软掩模图形， 曝光、 显 影之后， 去除了源区一侧的光刻胶， 而仅在漏区一侧保留下光刻胶图形 6 其中 （光刻胶）掩模图形 6可以如图 4所示严格以器件中轴线为界而占据了 漏区的全部和栅极堆叠结构的一半， 但是也可以采取其他形式， 只要暴露 出源区一侧并且覆盖漏区一侧， 例如光刻胶图形 6的左边界位于左侧栅极侧 墙 4左侧面的右方并且位于右侧栅极侧墙 4右侧面的左方， 光刻胶图形 6的右 边界位于漏区 3HD右侧面的右方。
[0032] 参照图 5 , 刻蚀暴露的阻挡材料层 5 , 直至露出源区 3HS (以及栅极侧 以是干法刻蚀或湿法刻蚀。 干法刻蚀包括等离子体刻蚀、 反应离子刻蚀等， 刻蚀气体可以采用氟基气体（碳氟基气体， 例如 CF4 CHF3 CH3F CH2F2； NF3; SF6 )、 C12/HC K Br2/HBr、 氧气、 稀有气体（Ar He )及其组合。 湿法刻蚀 的刻蚀液可以包括 HF HF:丽 4F H202 H2S04 HN03及其组合。 刻蚀也可是是 干法刻蚀和湿法刻蚀的组合， 例如先干法后湿法， 或者对于层叠的阻挡材 料层 5采用不同的干法刻蚀组合、 湿法刻蚀组合、 或者干法与湿法刻蚀的组 合。 如前所述， 阻挡材料 5与侧墙 4、 刻蚀停止层 2C的材料不同， 因此在刻 蚀过程中侧墙 4、 刻蚀停止层 2C不会被刻蚀。
[0033] 参照图 6 , 去除掩模图形 6 , 在漏区 3HD—侧留下了阻挡层 5D。 去除光 刻胶的方法可以是有机溶剂溶解、 无机溶剂氧化、 或者氧气等离子灰化等。
[0034] 参照图 1以及图 7 ,在源区上外延生长提升源区。采用 MBE、 ALD、 MOCVD 等方法， 在暴露的源区 3HS上外延生长提升源区 3RS。 由于 STI 1A、 栅极侧 此外延仅发生在源区 3HS上， 因此也称为选择性外延。 提升源区 3RS的材质 包括 S i、 S iGe、 S i: C及其组合。 优选地， 采用 S iGe、 S i: C以向沟道区施加 应力、 提高沟道区载流子迁移率。 优选地， 在外延生长的同时， 原位掺杂 使得提升源区 3RS具有与源区 3HS相同的导电类型。 可选地， 在外延提升源 区 3RS之后， 再次执行掺杂离子注入并随后退火以激活杂质， 使得提升源区 3RS具有与源区 3HS相同的导电类型。 此时， 由于阻挡层 5D的限制， 漏区 3HD 上没有形成提升漏区， 因此栅极 2B的电力线不会额外穿入到提升漏区中而 引起寄生电容增大， 也即不形成提升漏区降低了漏区一侧的寄生电容。 此 外， 源区一侧的提升源区 3RS使得源区面积增大、 掺杂浓度增大， 寄生电阻 减小， 因此进一步提高了器件性能。
[0035] 参照图 1以及图 8 , 去除阻挡层 5D。 依照阻挡层 5D的材质， 采用与图 5 所示步骤相同的工艺， 去除剩余的阻挡层 5D。 随后， 可以完成后续 MOSFET 制造工艺（未示出）， 例如包括在提升源区 3RS与漏区 3HD上形成金属硅化物 以进一步降氏接触电阻， 在整个器件上形成层间介质层（ILD ), 刻蚀 ILD直 至暴露金属硅化物而形成源漏接触孔，在源漏接触孔中沉积金属 /金属氮化 物形成源漏接触塞等。 当堆栈结构采用后栅工艺时， 在形成层间介质之后， 刻蚀层间介质之前还可包括： 平坦化层间介质层以及假栅极堆叠结构直至 暴露栅极填充层； 去除栅极填充层， 形成栅极沟槽； 栅极沟槽中形成功函 数调节层和电阻调节层。 其中， 功函数调节层与电阻调节层金属如前所述。
[0036] 依照本发明的半导体器件制造方法， 选择性地仅在源区一侧形成提 升源区从而构成非对称器件结构， 针对性减小源区一侧寄生电阻以及漏极 一侧寄生电容， 有效提高了器件性能。 [0037] 尽管已参照一个或多个示例性实施例说明本发明， 本领域技术人员 可以知晓无需脱离本发明范围而对形成器件结构的方法做出各种合适的改 变和等价方式。 此外， 由所公开的教导可做出许多可能适于特定情形或材 料的修改而不脱离本发明范围。 因此， 本发明的目的不在于限定在作为用 于实现本发明的最佳实施方式而公开的特定实施例， 而所公开的器件结构 及其制造方法将包括落入本发明范围内的所有实施例。

Claims

权 利 要 求
1. 一种半导体器件制造方法， 包括：
在村底上形成栅极堆叠结构以及栅极侧墙， 在栅极堆叠结构以及栅极侧墙两侧 村底中分别形成源区和漏区；
在漏区上选择性形成阻挡层， 其中阻挡层覆盖漏区并且暴露源区；
在暴露的源区上外延形成提升源区；
去除阻挡层。
2. 如权利要求 1的半导体器件制造方法， 其中， 阻挡层材料与村底材料不同。
3. 如权利要求 1的半导体器件制造方法， 其中， 在漏区上选择性形成阻挡层 的步骤进一步包括：
在整个器件上形成阻挡材料层；
在阻挡材料层上形成光刻胶图形， 覆盖漏区上的阻挡材料层并且暴露源区上的 阻挡材料层；
刻蚀暴露的源区上的阻挡材料层， 仅留下漏区上的部分阻挡材料层而构成阻挡 层；
去除光刻胶图形。
4. 如权利要求 1的半导体器件制造方法， 其中， 提升源区包括 S i、 S iGe、 S i: C 及其组合。
5. 如权利要求 1的半导体器件制造方法， 其中， 在形成提升源区的同时原位 掺杂， 或者在形成提升源区之后注入掺杂， 使得提升源区与源区导电类型相同。
6. 如权利要求 1的半导体器件制造方法， 其中， 去除阻挡层之后还包括： 在漏区和提升源区上形成金属硅化物； 刻蚀层间介质层直至暴露金属硅化物， 形成源漏接触孔；
在源漏接触孔中沉积形成源漏接触塞。
7. 如权利要求 6的半导体器件制造方法， 其中， 栅极堆叠结构为假栅极堆叠 结构， 包括氧化硅的垫氧化层以及多晶硅、 非晶硅、 氧化硅的假栅极填充层。
8. 如权利要求 7所述的半导体器件制造方法， 其中， 在形成层间介质层之后， 刻蚀层间介质层之前还包括：
平坦化层间介质层以及假栅极堆叠结构直至暴露假栅极填充层；
去除假栅极填充层， 形成栅极沟槽；
栅极沟槽中形成功函数调节层和电阻调节层。
9. 如权利要求 1的半导体器件制造方法， 其中， 源区和 /或漏区包括轻掺杂的 延伸区以及重掺杂区。
10. 如权利要求 1的半导体器件制造方法， 其中， 源区与漏区对称。
PCT/CN2012/079454 2012-07-11 2012-07-31 半导体器件制造方法 WO2014008691A1 (zh)

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