TW201532129A - 半導體裝置結構及其形成方法 - Google Patents

半導體裝置結構及其形成方法 Download PDF

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TW201532129A
TW201532129A TW103115769A TW103115769A TW201532129A TW 201532129 A TW201532129 A TW 201532129A TW 103115769 A TW103115769 A TW 103115769A TW 103115769 A TW103115769 A TW 103115769A TW 201532129 A TW201532129 A TW 201532129A
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gate structure
metal gate
semiconductor device
contact plug
width
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TW103115769A
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English (en)
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TWI574309B (zh
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Wei-Shuo Ho
Tsung-Yu Chiang
Chia-Ming Chang
Jyun-Ming Lin
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Taiwan Semiconductor Mfg Co Ltd
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本發明的實施例提供一種半導體裝置結構，包括：基板；第一金屬閘極結構，形成在基板上，其中第一金屬閘極結構具有第一寬度。半導體裝置結構還包括第一接觸插塞，形成於鄰近第一金屬閘極結構；第二金屬閘極結構，形成在基板上，其中第二金屬閘極結構具有第二寬度小於第一寬度。半導體裝置結構還包括絕緣層，形成在第二金屬閘極結構上，以及第二接觸插塞，自對準(self-algned)於第二金屬閘極結構。

Description

半導體裝置結構及其形成方法
本發明係有關於一種半導體結構及其形成方法，且特別是有關於一種具複數個金屬閘極結構的半導體結構及其形成方法。
半導體裝置應用於各種電子裝置，例如個人電腦、手機、數位相機等各式電子儀器。半導體裝置的形成通常包括在半導體基板上依序沉積絕緣層或介電層、導電層及半導體層材料，並利用微影圖案化各種材料層，以在基板上形成電路元件。
提升裝置表現的方法之一為藉由縮小在給定晶片上的裝置尺寸，以提高電路的積體程度。在進行晶片尺寸的縮小上，容忍度扮演了重要的角色。
隨著積體電路設計中技術節點(nodes)的縮小，可利用金屬閘極取代典型的多晶矽閘極，以在縮小的元件尺寸中提升裝置的效能。「後閘極(gate last)」製程為形成金屬閘極的製程之一。在後閘極製程中，金屬閘極在最後形成，使得其後續製程數目得以減少。
然而，雖然現有的後閘極製程已可達到部分應用上的需求，但隨著元件尺寸的縮小，其表現仍未在所有層面上 令人滿意。
在一些實施例中，提供一種半導體裝置結構，包括：一基板；一第一金屬閘極結構，形成在該基板上，其中該第一金屬閘極結構具有一第一寬度；一第一接觸插塞，形成於鄰近該第一金屬閘極結構；一第二金屬閘極結構，形成在該基板上，其中該第二金屬閘極結構具有一第二寬度小於該第一寬度；一絕緣層，形成在該第二金屬閘極結構上；以及一第二接觸插塞，自對準(self-algned)於該第二金屬閘極結構。
在一些實施例中，提供一種半導體裝置結構，包括：一基板；一第一金屬閘極結構，形成在該基板上；一第一接觸插塞，形成於鄰近該第一金屬閘極結構；一第二金屬閘極結構，形成在該基板上；一絕緣層，形成在該第二金屬閘極結構上；以及一第二接觸插塞，自對準(self-algned)於該第二金屬閘極結構，其中該第一金屬閘極結構具有一第一寬度及一第一高度，該第二金屬閘極結構具有一第二寬度及一第二高度，該第二高度小於該第一高度，且該第一寬度對該第二寬度的比介於約2至15。
在一些實施例中，提供一種半導體裝置結構的形成方法，包括：在一基板上的一層間介電層中形成一第一金屬閘極結構及一第二金屬閘極結構；在該第一金屬閘極結構上形成一罩幕結構而暴露出該第二金屬閘極結構的一頂表面；蝕刻該第二金屬閘極結構的一頂部分，以矮化該第二金屬閘極結構；在該第二金屬閘極結構上形成一絕緣層；以及形成鄰近於 該第一金屬閘極結構的一第一接觸插塞以及自對準於該第二金屬閘極結構的一第二接觸插塞，其中該第一金屬閘極結構具有一第一寬度且該第二金屬閘極結構具有一第二寬度小於該第一寬度。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
102‧‧‧基板
305‧‧‧淺摻雜源極汲極區
307‧‧‧源極汲極區
112‧‧‧層間介電層
100、400‧‧‧半導體裝置結構
134‧‧‧第二接觸插塞
120’‧‧‧矮化之窄的金屬閘極結構
128‧‧‧絕緣層
118‧‧‧寬的金屬閘極結構
132‧‧‧第一接觸插塞
130‧‧‧介電層
L1‧‧‧第一長度
L2‧‧‧第二長度
W1‧‧‧第一寬度
W2‧‧‧第二寬度
H1‧‧‧第一高度
H2‧‧‧第二高度
H3‧‧‧第三高度
313‧‧‧光阻層
315‧‧‧第一開口
317‧‧‧第二開口
204‧‧‧淺溝槽隔離區
104‧‧‧寬的虛設閘極結構
106‧‧‧窄的虛設閘極結構
108‧‧‧閘極介電層
110‧‧‧閘極電極層
319‧‧‧第一接觸插塞溝槽
321‧‧‧第二接觸插塞溝槽
518‧‧‧第四閘極結構
520’‧‧‧第五閘極結構
520”‧‧‧第六閘極結構
301‧‧‧密封層
303‧‧‧間隙物
309‧‧‧接觸蝕刻停止層
122‧‧‧閘極介電層
124‧‧‧功函數金屬層
126‧‧‧金屬閘極電極層
311‧‧‧罩幕結構
127‧‧‧回蝕製程
第1圖顯示在一些實施例中的半導體裝置結構的上視圖。
第2A至2K圖顯示在一些實施例中之半導體裝置結構沿著第1圖的線A-A’在形成的各階段的剖面圖。
第3圖顯示在一些實施例中的半導體裝置結構沿著第1圖所示線B-B’的剖面圖。
第4A圖顯示在一些實施例中之半導體裝置結構的上視圖。
第4B圖顯示在一些實施例中之半導體裝置結構沿著第4A圖所示線C-C’的剖面圖。
第4C圖顯示在一些實施例中之半導體裝置結構沿著第4A圖所示線D-D’的剖面圖。
因本發明之不同特徵而提供數個不同的實施例。本發明中特定的元件及安排係為了簡化，但本發明並不以這些實施例為限。舉例而言，於第二元件上形成第一元件的描述可包括第一元件與第二元件直接接觸的實施例，亦包括具有額外 的元件形成在第一元件與第二元件之間、使得第一元件與第二元件並未直接接觸的實施例。此外，為簡明起見，本發明在不同例子中以重複的元件符號及/或字母表示，但不代表所述各實施例及/或結構間具有特定的關係。
在本發明一些實施例中提供一種半導體裝置結構及其形成方法。半導體裝置結構可包括具有不同通道長度(例如，不同閘極寬度)的複數個閘極結構。一般而言，具有較小的通道寬度的閘極結構具有較小的節距(pitch)。然而，當節距較小時，閘極結構及鄰近於閘極結構的接觸插塞之間短路的風險也會增加。因此，可矮化閘極結構並將絕緣層形成在矮化的閘極結構上，以避免閘極結構及接觸插塞之間的短路。此外，接觸插塞可自對準(seld-aligned)於閘極結構。
第1圖顯示在一些實施例中的半導體裝置結構100的上視圖。半導體裝置100包括形成於基板102上的寬的金屬閘極結構118及矮化之窄的金屬閘極結構120’。寬的金屬閘極結構118的寬度大於矮化之窄的金屬閘極結構120’的寬度。此外，寬的金屬閘極結構118的高度大於矮化之窄的金屬閘極結構120’的高度。
此外，形成第一接觸插塞132鄰近寬的金屬閘極結構118處，並形成第二接觸插塞134鄰近矮化之窄的金屬閘極結構120’。在一些實施例中，寬的金屬閘極結構118、矮化之窄的金屬閘極結構120’、第一接觸插塞132、及第二接觸插塞134形成在基板102上，而淺溝槽隔離(STI)區204形成在基板102中。
第2A至2K圖顯示在一些實施例中之半導體裝置結 構100沿著第1圖的線A-A’在形成的各階段的剖面圖。
如第2A圖所示，在一些實施例中，提供基板102。基板102可為半導體晶圓，例如為矽晶圓。基板102或者或額外可包括元素半導體材料(elementary semiconductor materials)、化合物半導體材料(compound semiconductor materials)、及/或合金半導體材料(alloy semiconductor materials)。元素半導體材料例如為結晶矽(crystal silicon)、多晶矽(polycrystalline silicon)、非晶矽(amorphous silicon)、鍺、及/或鑽石，但並非以此為限。化合物半導體材料例如為碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)、及/或銻化銦(indium arnimonide)，但並非以此為限。合金半導體材料例如為矽鍺(SiGe)、鎵砷磷(GaAsP)、鋁銦砷(AlInAs)、鋁鎵砷(AlGaAs)、鎵銦砷(GaInAs)、鎵銦磷(GaInP)、及/或鎵銦砷磷(GaInAsP)，但並非以此為限。
在一些實施例中，基板102例如包括摻雜區、隔離元件、層間介電層、及/或導電元件等結構。此外，基板102可更包括圖案化的單一或多材料層。上述材料層例如為矽層、介電層、及/或摻雜多晶矽層。
在一些實施例中，在基板102上形成寬的虛設閘極結構104及窄的虛設閘極結構106，如第2A圖所示。在一些實施例中，寬的虛設閘極結構104具有第一寬度W1，且窄的虛設閘極結構106具有第二寬度W2小於第一寬度W1。在一些實施例中，寬的虛設閘極結構104的第一寬度W1介於約10nm至約 500nm。在一些實施例中，窄的虛設閘極結構106的第二寬度W2介於約5nm至約250nm。在一些實施例中，第一寬度W1對第二寬度W2的比約介於2至15。
在一些實施例中，寬的虛設閘極結構104及窄的虛設閘極結構106分別包括虛設閘極介電層108及虛設閘極電極層110。在一些實施例中，形成虛設閘極介電層108的材料為高介電常數(high-k)材料，例如金屬氧化物、金屬氮化物、金屬矽酸鹽、過渡金屬氮化物、過渡金屬矽酸鹽、或金屬的氮氧化物。高介電常數的材料例如包括氧化鉿(hafnium oxide；HfO2)、氧化矽鉿(hafnium silicon oxide；HfSiO)、氮氧化矽鉿(hafnium silicon oxynitride；HfSiON)、氧化鉭鉿(hafnium tantalum oxide；HfTaO)、氧化鈦鉿(hafnium titanium oxide；HfTiO)、氧化鋯鉿(hafnium zirconium oxide；HfZrO)、氮化矽(silicon nitride)、氮氧化矽(silicon oxynitride)、氧化鋯(zirconium oxide)、氧化鈦(titanium oxide)、氧化鋁(aluminum oxide)、二氧化鉿-氧化鋁(hafnium dioxide-alumina；HfO2-Al2O3)合金、或其他適合的介電材料，但並非以此為限。在一些實施例中，形成虛設閘極電極層110的材料為多晶矽。
形成寬的虛設閘極結構104及窄的虛設閘極結構106的步驟可包括沉積、光微影圖案化、及蝕刻製程。沉積製程科包括化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、高密度電漿化學氣相沉積(high density plasma CVD；HDPCVD)、金屬有機化學氣相沉積(metal organic CVD；MOCVD)、或電漿強化化學氣相沉積(plasma enhanced CVD； PECVD)。光微影圖案化製程可包括光阻塗佈(例如：旋轉塗佈)、軟烤、罩幕對準、曝光、曝光後烤(post-exposure baking)、光阻顯影、清洗、乾燥(例如：硬烤)、及/或其他適合的製程。蝕刻製程可包括乾蝕刻、濕蝕刻、及/或其他蝕刻方法(例如：反應性離子蝕刻(reactive ion etching))。
應注意的是，寬的虛設閘極結構104及窄的虛設閘極結構106可為彼此相鄰的結構，或者可在寬的虛設閘極結構104及窄的虛設閘極結構106之間形成其他結構，本發明之範疇並非以此為限。
在一些實施例中，在寬的虛設閘極結構104及窄的虛設閘極結構106的側壁上形成密封層(sealing layer)301。密封層301可保護寬的虛設閘極結構104及窄的虛設閘極結構106不受後續製程的損害或氧化。在一些實施例中，形成密封層301的材料包括氮化矽、氧化矽、氮氧化矽、碳化矽、或其他適合的介電材料。密封層301可包括單一層或多層。
在一些實施例中，在密封層301上形成間隙物303。在一些實施例中，形成間隙物303的材料包括氮化矽、氧化矽、氮氧化矽、碳化矽、或其他適合的介電材料。可利用沉積及蝕刻製程形成間隙物303。
此外，可在基板102中形成各種摻雜區。在一些實施例中，在基板102中形成淺摻雜源極/汲極(LDD)區305及源極/汲極(S/D)區307，如第2A圖所示。淺摻雜源極/汲極區305及源極/汲極區307的形成可利用離子植入製程、光微影、擴散、及/或其他適合的製程。在一些實施例中，淺摻雜源極/汲極區305 及源極/汲極區307的摻雜可利用p型摻質，例如利用硼或氟化硼(BF2)，或者可用n型摻質，例如磷或砷。
在形成寬的虛設閘極結構104及窄的虛設閘極結構106之後，在基板102上形成接觸蝕刻停止層(contact etch stop layer；CESL)309，以覆蓋寬的虛設閘極結構104及窄的虛設閘極結構106，如第2B圖所示。在一些實施例中，形成接觸蝕刻停止層309的材料為氮化矽、氮氧化矽、及/或其他適合的材料。接觸蝕刻停止層309的形成可利用電漿強化化學氣相沉積、低壓化學氣相沉積、或其他適合的製程。
在一些實施例中，在形成接觸蝕刻停止層309之後，在基板102上的接觸蝕刻停止層309上形成層間介電層112。層間介電層112可包括多種介電材料形成的多層結構，例如氧化矽、氮化矽、氮氧化矽、四乙基矽氧烷(tetraethoxysilane；TEOS)、磷矽酸鹽玻璃(phosphosilicate glass；PSG)、硼磷矽玻璃(borophosphosilicate glass；BPSG)、低介電材料、或其他適用的介電材料。低介電材料例如包括氟矽玻璃(Fluorinated Silicate Glass；FSG)、碳摻雜氧化矽(carbon doped silicon oxide)、非晶氟化碳(amorphous fluorinated carbon)、聚對二甲苯(parylene)、苯環丁烯(bis-benzocyclobutenes；BCB)、或聚乙醯胺(polyimide)。層間介電層112的形成可利用化學氣相沉積、物理氣象沉積、原子層沉積、旋轉塗佈、或其他適合的製程。
之後，在一些實施例中，對層間介電層112進行研磨製程，如第2C圖所示。在一些實施例中，利用化學機械研磨 製程平坦化層間介電層112，直到暴露出寬的虛設閘極結構104及窄的虛設閘極結構106的頂表面為止。
在研磨製程之後，以寬的金屬閘極結構118取代寬的虛設閘極結構104，並以窄的金屬閘極結構120取代窄的虛設閘極結構106。更詳細而言，在一些實施例中，移除寬的虛設閘極結構104及窄的虛設閘極結構106以形成寬溝槽114及窄溝槽116，如第2D圖所示。在一些實施例中，利用第一蝕刻製程移除虛設閘極電極層110，並在第一蝕刻製程之後，利用第二蝕刻製程移除虛設閘極介電層108。之後，如第2E圖所示，在一些實施例中，在寬溝槽118及窄溝槽120中分別形成寬的金屬閘極結構118及窄的金屬閘極結構120。
在一些實施例中，寬的金屬閘極結構118及窄的金屬閘極結構120分別包括閘極介電層122、功函數金屬層124、及金屬閘極電極層126。
在一些實施例中，利用高介電常數介電材料形成閘極介電層122。高介電常數介電材料例如包括氧化鉿(hafnium oxide；HfO2)、氧化矽鉿(hafnium silicon oxide；HfSiO)、氮氧化矽鉿(hafnium silicon oxynitride；HfSiON)、氧化鉭鉿(hafnium tantalum oxide；HfTaO)、氧化鈦鉿(hafnium titanium oxide；HfTiO)、氧化鋯鉿(hafnium zirconium oxide；HfZrO)、金屬氧化物(metal oxides)、金屬氮化物(metal nitrides)、金屬矽酸鹽(metal silicates)、過渡金屬氧化物(transition metal oxides)、過渡金屬氮化物(transition metal nitrides)、過渡金屬矽酸鹽(transition metal silicates)、金屬的氮氧化物(oxynitrides of metals)、金屬鋁酸鹽(metal aluminates)、鋯矽酸鹽(zirconium silicate)、鋯鋁酸鹽(zirconium aluminate)、氧化矽(silicon oxide)、氮化矽(silicon nitride)、氮氧化矽(silicon oxynitride)、氧化鋯(zirconium oxide)、氧化鈦(titanium oxide)、氧化鋁(aluminum oxide)、或二氧化鉿-氧化鋁(hafnium dioxide-alumina；HfO2-Al2O3)合金，但並非以此為限。
在閘極介電層122上形成功函數金屬層(Work function metal layer)124。調整功函數金屬層124以達到適當的功函數。例如，如欲得到P型金氧半(PMOS)裝置的P型功函數金屬(P-metal)，可利用氮化鈦(TiN)、氮化鎢(WN)、或鎢。相對的，如欲得到N型金氧半(NMOS)裝置的N型功函數金屬(P-metal)，可利用鈦鋁(TiAl)、氮化鈦鋁(TiAlN)、或氮碳化鉭(TaCN)。
在功函數金屬層124上形成金屬閘極電極層126。在一些實施例中，利用導電材料形成金屬閘極電極層126，例如鋁、銅、鎢、鈦、鉭、氮化鈦(titanium nitride)、氮化鉭(tantalum nitride)、矽化鎳(nickel silicide)、矽化鈷(cobalt silicide)、碳化鉭(TaC)、氮矽化鉭(TaSiN)、氮碳化鉭(TaCN)、鈦鋁(TiAl)、氮化鈦鋁(TiAlN)、或其他適合的材料。可利用任何適合的製程形成具有適當的厚度的閘極介電層122、功函數金屬層124、及金屬閘極電極層126。
應注意的是，在閘極介電層122、功函數金屬層124、及金屬閘極電極層126之上及/或之下，也可形成額外的層狀物，例如襯層(liner layers)、介面層(interface layers)、種 子層(seed layers)、黏著層(adhesion layers)、阻障層(barrier layers)等。此外，閘極介電層122、功函數金屬層124、及金屬閘極電極層126可包括一或多種材料及/或一或多層。
如第2E圖所示，在寬溝槽114中形成寬的金屬閘極結構118，其具有第一寬度W1。在窄溝槽116中形成窄的金屬閘極結構120，其具有第二寬度W2，第二寬度W2小於第一寬度W1。然而，當窄的金屬閘極結構120的第二寬度W2太小時，形成第二接觸插塞134時，很難避免第二接觸插塞134及窄的金屬閘極結構120之間的短路。因此，必須利用回蝕製程(etching back process)形成矮化之窄的金屬閘極結構120’，使得絕緣層128可形成於矮化之窄的金屬閘極結構120’上，以避免第二接觸插塞134及窄的金屬閘極結構120之間的短路。
然而，在回蝕製程中，若一併蝕刻寬的金屬閘極結構118，由於負載效應(loading effect)的影響，在寬的金屬閘極結構118的頂部分所被移除的量會大於在窄的金屬閘極結構120的頂部分被移除的量。亦即，在回蝕製程中，可能會移除掉過多的寬的金屬閘極結構118，例如移除掉過多的頂部的功函數金屬層124及金屬閘極電極層126。因此，矮化之寬的金屬閘極結構的效能可能會被損害，且結構的起始電壓可能會改變。因此，在一些實施例中，利用罩幕結構311以避免寬的金屬閘極結構118在回蝕製程中被損害，如第2F圖所示。
如第2F圖所示，在一些實施例中，在寬的金屬閘極結構118上形成罩幕結構311，以在後續蝕刻製程中保護寬的金屬閘極結構118。如第2F圖所示，罩幕結構311覆蓋寬的金屬 閘極結構118，但並未覆蓋窄的金屬閘極結構120。因此，在後續蝕刻製程中，以罩幕結構311保護寬的金屬閘極結構118，而暴露出窄的金屬閘極結構120的頂表面。在一些實施例中，罩幕結構311包括光阻層及底部抗反射塗佈層(bottom anti-reflective coating layer；BARC layer)。
在一些實施例中，在形成罩幕結構311之後，進行回蝕製程127以矮化窄的金屬閘極結構120，如第2G圖所示。既然寬的金屬閘極結構118被罩幕結構311所保護，寬的金屬閘極結構118的高度在回蝕製程127之後仍維持不變。然而，在回蝕製程127時，暴露出窄的金屬閘極結構120的頂表面，故窄的金屬閘極結構120被矮化而形成矮化之窄的金屬閘極結構120’。
在一些實施例中，寬的金屬閘極結構118具有第一高度H1，矮化之窄的金屬閘極結構120’具有第二高度H2，第二高度H2小於第一高度H1。在一些實施例中，第一高度H1介於約400A至約1000A。在一些實施例中，第二高度H2介於約100A至約990A。在一些實施例中，第一高度H1對第二高度H2的比介於約4至10。
此外，既然以寬的金屬閘極結構118取代虛設寬的閘極結構104，並以矮化之窄的金屬閘極結構120’取代虛設窄的閘極結構106，故寬的金屬閘極結構118也具有第一寬度W1，矮化之窄的金屬閘極結構120’具有第二寬度W2，第二寬度W2小於第一寬度W1。在一些實施例中，第一高度H1對第一寬度W1的比介於約1至25。在一些實施例中，第二高度H2對第二寬度W2的比介於約1至30。
在一些實施例中，在進行回蝕製程127之後，移除罩幕結構311，並在矮化之窄的金屬閘極結構120’上形成絕緣層128。如第2H圖所示，絕緣層128形成在矮化之窄的金屬閘極結構120’上，但並未形成在寬的金屬閘極結構118上。在一些實施例中，絕緣層128的形成包括在基板102上沉積絕緣材料，並移除絕緣材料的頂部分以暴露出寬的金屬閘極結構118的頂表面。
在一些實施例中，絕緣層128具有第三高度H3。在一些實施例中，第三高度H3介於約1A至約300A。在一些實施例中，寬的金屬閘極結構118的第一高度H1大體等於矮化之窄的金屬閘極結構120’的第二高度H2與絕緣層128的第三高度H3的和。
在一些實施例中，形成絕緣層128的材料包括但化材料、碳化材料、或氧化材料，例如氮化矽、碳化矽、氮氧化矽、或氧化鋁。此外，也可利用其他低介電常數介電材料形成絕緣層128。絕緣層128的形成可包括在基板102上沉積絕緣材料，之後進行化學機械研磨製程。可利用化學氣相沉積製程沉積絕緣材料。
接著，在一些實施例中，在層間介電層112、絕緣層128及寬的金屬閘極結構118上形成介電層130，如第2I圖所示。在一些實施例中，形成介電層130的材料例如為氧化矽、氮化矽、氮氧化矽、或其他適合的介電材料，其可與形成層間介電層112的材料相同或相似。可利用化學氣相沉積形成介電層130。
之後，在一些實施例中，在介電層130上形成光阻層313，如第2I圖所示。光阻層313具有第一開口315及第二開口317。進行蝕刻製程以移除層間介電層112及介電層130位於光阻層313之第一開口315及第二開口317下的部分，如第2J圖所示，而形成第一接觸插塞溝槽319及第二接觸插塞溝槽321。在一些實施例中，蝕刻製程為濕蝕刻製程。可依照需要調整第一接觸插塞溝槽319及第二接觸插塞溝槽321的寬度。
接著，在一些實施例中，分別在第一接觸插塞溝槽319及第二接觸插塞溝槽321中分別形成第一接觸插塞132及第二接觸插塞134，如第2K圖所示。在一些實施例中，利用導電材料形成第一接觸插塞132及第二接觸插塞134，例如鋁、銅、鎢、鈦、鉭、氮化鈦(titanium nitride)、氮化鉭(tantalum nitride)、矽化鎳(nickel silicide)、矽化鈷(cobalt silicide)、碳化鉭(TaC)、氮矽化鉭(TaSiN)、氮碳化鉭(TaCN)、鈦鋁(TiAl)、氮化鈦鋁(TiAlN)、其他適合的材料、或前述之組合。
如第2K圖所示，第一接觸插塞132形成於鄰近寬的金屬閘極結構118的源極/汲極區307上，第二接觸插塞134形成於鄰近矮化之窄的金屬閘極結構120’的源極/汲極區307上。此外，既然絕緣層128形成在矮化之窄的金屬閘極結構120’上，且絕緣層128係用以避免第二接觸插塞134及金屬閘極結構之間的短路，故第二接觸插塞134可自對準(self-aligned)於矮化之窄的金屬閘極結構120’。亦即，在利用蝕刻製程形成第二接觸插塞溝槽321時，可利用絕緣層128作為罩幕，如第2J圖所示。因此，形成在第二接觸插塞溝槽321中的第二接觸插塞134可與 矮化之窄的金屬閘極結構120’相對，但第二接觸插塞134不會與矮化之窄的金屬閘極結構120’直接接觸。
如前述，在矮化之窄的金屬閘極結構120’上形成絕緣層128以避免第二接觸插塞134及矮化之窄的金屬閘極結構120’之間的短路。因此，第二接觸插塞134可自對準於矮化之窄的金屬閘極結構120’。此外，既然在回蝕製程127中利用罩幕結構311保護寬的金屬閘極結構118，可避免寬的金屬閘極結構118中的導電結構的損害，且其起始電壓可維持如原本所需。
參照第1圖，在一些實施例中，半導體裝置結構100更包括第三矮化金屬閘極結構120”及第三接觸插塞134’。第3圖顯示在一些實施例中的半導體裝置結構100沿著第1圖所示線B-B’的剖面圖。形成第三矮化金屬閘極結構120”的製程及材料可類似於矮化之窄的金屬閘極結構120’。更詳細而言，第三矮化金屬閘極結構120”也包括閘極介電層122、功函數金屬層124、及金屬閘極電極層126。此外，絕緣層128形成於第三矮化金屬閘極結構120”上。
如第1圖所示，寬的金屬閘極結構118具有第一長度L1，而第三矮化金屬閘極結構120”具有第二長度L2，第二長度L2小於第一長度L1。既然第三矮化金屬閘極結構120”具有相對較小的長度，在一些實施例中，在第三矮化金屬閘極結構120”上形成絕緣層128，以避免第三矮化金屬閘極結構120”及第三接觸插塞134’之間短路的風險，如第3圖所示。在一些實施例中，形成第三接觸插塞134’的材料及製程可類似於形成第二接觸插塞134的材料及製程。在一些實施例中，第三接觸插 塞134’為自對準接觸插塞(self-aligned contact)。
應注意的是，第1圖所示的寬的金屬閘極結構118、矮化之窄的金屬閘極結構120’、第三矮化之金屬閘極結構120”僅為舉例說明之用，本發明之範疇並非以此為限。在一些實施例中，半導體裝置結構僅包括兩個金屬閘極結構，例如僅包括寬的金屬閘極結構118及矮化之窄的金屬閘極結構120’。在一些實施例中，半導體裝置結構包括多於三個金屬閘極結構。
此外，可利用上述使用罩幕結構311之半導體裝置結構的形成方法來形成具有鰭式場效電晶體(fin field-effect transistor；FinFET)結構的半導體裝置。第4A圖顯示在一些實施例中之半導體裝置結構400的上視圖。第4B圖顯示在一些實施例中之半導體裝置結構400沿著第4A圖所示線C-C’的剖面圖。第4C圖顯示在一些實施例中之半導體裝置結構400沿著第4A圖所示線D-D’的剖面圖。
如第4A圖所示，半導體裝置結構400包括形成在基板102上的第四閘極結構518、第五閘極結構520’、及第六閘極結構520”。此外，第四閘極結構518、第五閘極結構520’、及第六閘極結構520”分別橫跨鰭狀結構502而形成。在鄰近於第四閘極結構518處形成第一接觸插塞132。在鄰近於第五閘極結構520’處形成第二接觸插塞134。在鄰近於第六閘極結構520”處形成第三接觸插塞134’。
如第4B圖所示，在一些實施例中，第四閘極結構518可相似於寬的金屬閘極結構118，且第五閘極結構520’可相 似於矮化之窄的金屬閘極結構120’。在一些實施例中，第四閘極結構518及第五閘極結構520’分別包括閘極介電層122、功函數金屬層124及金屬閘極電極層126。此外，由於第五閘極結構520’的寬度相對的小，絕緣層128形成於第五閘極結構520’上，但未形成於第四閘極結構518。因此，第二接觸插塞134可自對準於第五閘極結構520’。
如第4C圖所示，在一些實施例中，第六閘極結構520”可類似於第三金屬閘極結構120”。在一些實施例中，第六閘極結構520”包括閘極介電層122、功函數金屬層124及金屬閘極電極層126。此外，由於第六閘極結構520”具有相對較小的寬度，絕緣層128形成於第六閘極結構520”上，而未形成於第四閘極結構518上。因此，第三接觸插塞134’可自對準於第六閘極結構520”。
如第4B及4C圖所示，在一些實施例中，半導體裝置結構400還包括密封層301、間隙物303、淺摻雜源極/汲極(LDD)區305、源極/汲極區307、接觸蝕刻停止層309、層間介電層112、及介電層130。上述元件可類似於或相同於前述實施例中之元件，故在此不重複敘述。
如前述，在一些實施例中，半導體裝置結構，例如半導體裝置結構100，包括具有各種通道長度的閘極結構。例如，半導體裝置結構100包括寬的金屬閘極結構118及矮化之窄的金屬閘極結構120’，且寬的金屬閘極結構118的第一寬度W1大於矮化之窄的金屬閘極結構120’的第二寬度W2。然而，由於負載效應的影響，第一寬度W1及第二寬度W2之差異會導 致蝕刻速率的不同。因此，在進行回蝕製程127時，需利用罩幕結構311保護寬的金屬閘極結構118。因此，在回蝕製程127中，寬的金屬閘極結構118的頂部分不會被移除，而窄的金屬閘極結構120的頂部會被移除而形成矮化之窄的金屬閘極結構120’。
上述方法可避免寬的金屬閘極結構118在回蝕製程127中受到損害，故寬的金屬閘極結構118可維持其起始電壓。
此外，在矮化之窄的金屬閘極結構120’上形成絕緣層128，以避免矮化之窄的金屬閘極結構120’及第二接觸插塞134之間的短路。因此，在一些實施例中，第二接觸插塞134可自對準。此外，第二接觸插塞134的一部分可形成在絕緣層128上，且利用絕緣層128分隔第二接觸插塞134及矮化之窄的金屬閘極結構120’。
在本發明一些實施例中提供一種半導體裝置結構。半導體裝置結構包括第一金屬閘極結構及第二金屬閘極結構。第一金屬閘極結構具有第一寬度，且第二金屬閘極結構具有第二寬度小於第一寬度。絕緣層形成在第二金屬閘極結構上。利用回蝕製程矮化第二金屬閘極結構。此外，在回蝕製程中，在第一金屬閘極結構上形成罩幕結構，使得第一金屬閘極結構被罩幕結構所保護。因此，在回蝕製程中，第一金屬閘極結構不會受到損害，故第一金屬閘極結構可維持其起始電壓。
在一些實施例中，提供一種半導體裝置結構。半導體裝置結構包括基板及第一金屬閘極結構形成在基板上。第 一金屬閘極結構具有第一寬度。半導體裝置結構還包括第一接觸插塞，形成於鄰近第一金屬閘極結構。半導體裝置結構還包括第二金屬閘極結構，形成在基板上。此外，第二金屬閘極結構具有第二寬度小於該第一寬度。半導體裝置結構更包括絕緣層，形成在第二金屬閘極結構上。半導體裝置結構更包括第二接觸插塞，自對準(self-aligned)於第二金屬閘極結構。
在一些實施例中，提供一種半導體裝置結構。半導體裝置結構包括基板及第一金屬閘極結構形成在基板上。半導體裝置結構還包括第一接觸插塞形成於鄰近第一金屬閘極結構。半導體裝置結構還包括第二金屬閘極結構形成在基板上。半導體裝置結構還包括絕緣層形成在第二金屬閘極結構上以及第二接觸插塞自對準(self-aligned)於第二金屬閘極結構。此外，第一金屬閘極結構具有第一寬度及第一高度，第二金屬閘極結構具有第二寬度及第二高度，第二高度小於第一高度，且第一寬度對第二寬度的比介於約2至15。
在一些實施例中，提供一種半導體裝置結構的形成方法。半導體裝置結構的形成方法包括在基板上的層間介電層中形成第一金屬閘極結構及第二金屬閘極結構，並在第一金屬閘極結構上形成罩幕結構而暴露出第二金屬閘極結構的頂表面。半導體裝置結構的形成方法還包括蝕刻第二金屬閘極結構的頂部分，以矮化第二金屬閘極結構，並在第二金屬閘極結構上形成絕緣層。半導體裝置結構的形成方法更包括形成鄰近於第一金屬閘極結構的第一接觸插塞以及自對準於第二金屬閘極結構的第二接觸插塞。此外，第一金屬閘極結構具有第一 寬度且第二金屬閘極結構具有第二寬度小於第一寬度。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
102‧‧‧基板
305‧‧‧淺摻雜源極汲極區
307‧‧‧源極汲極區
112‧‧‧層間介電層
100‧‧‧半導體裝置結構
134‧‧‧第二接觸插塞
120’‧‧‧矮化之窄的金屬閘極結構
128‧‧‧絕緣層
118‧‧‧寬的金屬閘極結構
132‧‧‧第一接觸插塞
130‧‧‧介電層

Claims (10)

  1. 一種半導體裝置結構，包括：一基板；一第一金屬閘極結構，形成在該基板上，其中該第一金屬閘極結構具有一第一寬度；一第一接觸插塞，形成於鄰近該第一金屬閘極結構；一第二金屬閘極結構，形成在該基板上，其中該第二金屬閘極結構具有一第二寬度小於該第一寬度；一絕緣層，形成在該第二金屬閘極結構上；以及一第二接觸插塞，自對準(self-aligned)於該第二金屬閘極結構。
  2. 如申請專利範圍第1項所述之半導體裝置結構，其中該第一寬度對該第二寬度的比例約介於2至15。
  3. 如申請專利範圍第1項所述之半導體裝置結構，其中該第一金屬閘極結構具有一第一高度，且該第二金屬閘極結構具有一第二高度小於該第一高度。
  4. 如申請專利範圍第3項所述之半導體裝置結構，其中該第一高度對該第二高度的比約介於4至10。
  5. 如申請專利範圍第3項所述之半導體裝置結構，其中形成在該第二金屬閘極結構上的該絕緣層具有一第三高度，且該第二高度及該第三高度相加的和大體等於該第一高度。
  6. 如申請專利範圍第1項所述之半導體裝置結構，其中該絕緣層形成在該第二金屬閘極結構上，但未形成在第一金屬閘極結構上。
  7. 如申請專利範圍第1項所述之半導體裝置結構，其中該第二金屬插塞的一部分形成在該絕緣層上。
  8. 一種半導體裝置結構的形成方法，包括：在一基板上的一層間介電層中形成一第一金屬閘極結構及一第二金屬閘極結構；在該第一金屬閘極結構上形成一罩幕結構而暴露出該第二金屬閘極結構的一頂表面；蝕刻該第二金屬閘極結構的一頂部分，以矮化該第二金屬閘極結構；在該第二金屬閘極結構上形成一絕緣層；以及形成鄰近於該第一金屬閘極結構的一第一接觸插塞以及自對準於該第二金屬閘極結構的一第二接觸插塞；其中該第一金屬閘極結構具有一第一寬度且該第二金屬閘極結構具有一第二寬度小於該第一寬度。
  9. 如申請專利範圍第8項所述之半導體裝置結構的形成方法，其中形成該第一金屬插塞及該第二金屬插塞的步驟更包括：在該基板上形成一介電層以覆蓋該層間介電層、該第一金屬閘極結構及該第二金屬閘極結構；在該介電層上形成一光阻層，其中該光阻層具有一第一開口及一第二開口；通過該第一開口及該第二開口進行一蝕刻製程，以形成一第一接觸插塞溝槽及一第二接觸插塞溝槽；以及以一導電材料填入該第一接觸插塞溝槽及該第二接觸插塞 溝槽以形成該第一接觸插塞及該第二接觸插塞。
  10. 如申請專利範圍第8項所述之半導體裝置結構的形成方法，其中該第一金屬閘極結構具有一高度大體相等於該第二金屬閘極結構及該絕緣層的高度和。
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