TW201526204A - 積體電路及其製造方法 - Google Patents
積體電路及其製造方法 Download PDFInfo
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- TW201526204A TW201526204A TW103143785A TW103143785A TW201526204A TW 201526204 A TW201526204 A TW 201526204A TW 103143785 A TW103143785 A TW 103143785A TW 103143785 A TW103143785 A TW 103143785A TW 201526204 A TW201526204 A TW 201526204A
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- Prior art keywords
- polysilicon
- region
- integrated circuit
- dopant
- grain size
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- 238000000034 method Methods 0.000 title claims abstract description 87
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 258
- 229920005591 polysilicon Polymers 0.000 claims abstract description 258
- 239000002019 doping agent Substances 0.000 claims abstract description 89
- 230000008569 process Effects 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000004151 rapid thermal annealing Methods 0.000 claims abstract description 32
- 238000002513 implantation Methods 0.000 claims abstract description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 21
- 239000007943 implant Substances 0.000 claims description 20
- 229910052732 germanium Inorganic materials 0.000 claims description 18
- 238000002955 isolation Methods 0.000 claims description 15
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052733 gallium Inorganic materials 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- TVFDJXOCXUVLDH-UHFFFAOYSA-N caesium atom Chemical group [Cs] TVFDJXOCXUVLDH-UHFFFAOYSA-N 0.000 claims 1
- 238000001727 in vivo Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 23
- 238000000137 annealing Methods 0.000 description 13
- 125000006850 spacer group Chemical group 0.000 description 10
- 238000001459 lithography Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical group [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
本揭示提供的積體電路包含具有第一晶粒尺寸的第一多晶矽區,以及具有第二晶粒尺寸的第二多晶矽區形成在基底上。此外,本揭示還提供積體電路的製造方法,此方法包含形成具有初始晶粒尺寸的第一多晶矽區在基底上,對第一多晶矽區植入具有第一導電型的第一摻雜物以及第二摻雜物,在植入製程之後,第一多晶矽區會具有大於初始晶粒尺寸的第一晶粒尺寸,然後對第一多晶矽區進行雷射快速熱退火製程。
Description
本發明係有關於積體電路技術,特別有關於多晶矽電阻器的製造方法,以及經由此方法所製造出的積體電路,其可改善積體電路中的多晶矽電阻器之間電阻值不匹配的問題。
目前已經可以經由各種已知的技術製造出積體電路,在積體電路的製造中,形成主動元件和被動元件在半導體基底例如矽晶圓上,然後依據需要的方式讓這些元件互相連接。
電阻器可經由一些熟知的技術形成在半導體基底中,在一種技術中,於半導體基底的一些區域中摻雜以n型或p型摻雜物,經由此方式可以在半導體基底中提供具有所需電阻率的導電區域,在導電區域內的一對互相分開的位置上形成歐姆接點,並藉此提供了擴散區,以這種技術形成的電阻器稱為擴散電阻器(diffused resistor)。
在另一種技術中,於半導體基底的表面上形成絕緣層例如介電層,接著在絕緣層上形成一層多晶矽層,在多晶矽層內摻雜以n型或p型摻雜物,這些摻雜物使得多晶矽層形成具有所需電阻率的導電區,然後在多晶矽層上的一對互相分開
的區域上形成歐姆連接,以完成電阻器,以這種技術形成的電阻器稱為多晶矽電阻器(polysilicon resistor)。
積體電路的製造過程包含退火步驟,退火步驟具有各種作用,包含活化摻雜物,以及降低離子植入對於晶格所造成的損傷。雷射掃描退火(laser scan annealing)是一種已知的退火技術,其相較於其他的退火技術具有許多優點,例如相較於傳統的快速熱退火(rapid thermal annealing)、閃光燈退火(flash annealing)或爐內退火(furnace annealing)等技術,雷射掃描退火具有更多的優勢,這些傳統的退火技術主要是用於舊的製程節點(node)例如100nm的節點中,而雷射掃瞄退火技術則開始頻繁地用於先進的製程節點,例如65nm以及其以下的節點中,然而,雷射掃瞄退火還是有其特有的缺陷機制存在。
本揭示提供積體電路的製造方法,此方法可以克服在積體電路的不同位置上所製作的多晶矽電阻器之間的電阻值不匹配的問題,這些不同位置上的多晶矽電阻器之間的電阻值不匹配是因為雷射快速熱退火製程所引起,而雷射快速熱退火製程是用於活化在多晶矽電阻器內的摻質。在習知的製造方法中,雷射快速熱退火製程所採用的雷射掃瞄退火方式會引起多晶矽電阻器之間的電阻值不匹配的問題,而藉由本揭示的製造方法可以克服此問題。此外,本揭示還提供積體電路,其包含由此方法所製作的多晶矽電阻器。
在本揭示的實施例中,提供積體電路。此積體電路包含:第一多晶矽區形成在一基底上,其具有第一晶粒尺
寸,以及第二多晶矽區形成在此基底上,其具有與第一晶粒尺寸不同的第二晶粒尺寸。
在一些實施例中,第一多晶矽區是被動元件的一部分,第二多晶矽區是主動元件的一部分,第一晶粒尺寸大於第二晶粒尺寸,第一多晶矽區具有p型的第一摻雜物以及第二摻雜物植入於其中,第二摻雜物係選自於第IIIA族元素和第IVA族元素中原子量大於矽原子量的元素。在一些實施例中,第一多晶矽區包含多晶矽電阻器,並且第二多晶矽區包含多晶矽閘極。
在本揭示的實施例中,提供積體電路。此積體電路包含:第一多晶矽區形成在基底上且位於被動元件區內,其包含複數個多晶矽電阻器,並且具有第一晶粒尺寸,以及第二多晶矽區形成在基底上且位於主動元件區內,其包含複數個多晶矽閘極,並且具有與第一晶粒尺寸不同的第二晶粒尺寸。
在一些實施例中,第一晶粒尺寸大於第二晶粒尺寸,多晶矽電阻器圍繞主動元件區,並且設置在主動元件區不同側邊的這些多晶矽電阻器具有一致的電阻值。
在本揭示的實施例中,提供積體電路的製造方法。此方法包含:形成第一多晶矽區在基底上,其具有初始晶粒尺寸;植入第一導電型的第一摻雜物以及第二摻雜物至第一多晶矽區內,在植入製程之後,第一多晶矽區具有的第一晶粒尺寸大於初始晶粒尺寸;以及對第一多晶矽區進行雷射快速熱退火製程。
在本揭示的實施例中,提供積體電路的製造方
法。此方法包含:形成第一多晶矽區在基底上,其包含複數個多晶矽電阻器主體,這些多晶矽電阻器主體具有初始晶粒尺寸,並且這些多晶矽電阻器主體圍繞主動元件區;植入第一導電型的第一摻雜物以及第二摻雜物至這些多晶矽電阻器主體內,在植入製程之後,這些多晶矽電阻器主體具有的第一晶粒尺寸大於初始晶粒尺寸;以及以雷射掃瞄方向移動雷射光束,對這些多晶矽電阻器主體進行雷射快速熱退火製程,此雷射掃瞄方向係垂直於主動元件區的第一側邊和第二側邊。
100‧‧‧積體電路
101‧‧‧半導體基底
102‧‧‧被動元件區
103‧‧‧主動元件區
103R‧‧‧主動元件區的右側邊
103L‧‧‧主動元件區的左側邊
104‧‧‧PMOS區
105‧‧‧多晶矽電阻器主體
105R、105L、105U、105D‧‧‧多晶矽電阻器
106‧‧‧NMOS區
107‧‧‧淺溝槽隔絕結構
108‧‧‧側壁間隙物
109‧‧‧接點
110‧‧‧雷射光束
111‧‧‧介電層
120‧‧‧雷射掃描方向
130‧‧‧第一遮罩
140、150‧‧‧閘極介電層
141、151‧‧‧多晶矽閘極
143、153‧‧‧閘極側壁間隙物
145‧‧‧P通道輕摻雜區
147‧‧‧P通道重摻雜區
155‧‧‧n通道輕摻雜區
157‧‧‧n通道重摻雜區
160、180‧‧‧植入製程
162‧‧‧第一摻雜物
170‧‧‧第二遮罩
182‧‧‧第二摻雜物
190‧‧‧雷射快速熱退火製程
d‧‧‧距離
θ‧‧‧角度
GS1‧‧‧第二晶粒尺寸
GS2‧‧‧第一晶粒尺寸
為了讓本揭示之目的、特徵、及優點能更明顯易懂,以下配合所附圖式作詳細說明如下:第1圖顯示依據一些實施例,在雷射快速熱退火製程期間,積體電路的局部平面示意圖;第2圖顯示依據一些實施例,積體電路的局部剖面示意圖,在雷射快速熱退火製程期間雷射光束照射多晶矽區域;以及第3A至3D圖顯示依據一些實施例,製造積體電路的中間階段之局部剖面示意圖。
以下揭示內容提供一些實施例或例子來實現本揭示之標的,下述元件與其排列方式的特定例子係用於簡化本揭示的說明,這些例子僅作為示範用,並非用於限定本揭示。
參閱第1圖,其為依據一些實施例,在雷射快速
熱退火製程期間,積體電路100的局部平面示意圖。積體電路100包含主動元件和被動元件形成在半導體基底101例如矽晶圓上,主動元件例如電晶體的多晶矽閘極141和151形成在主動元件區103內,被動元件例如多晶矽電阻器105R、105L、105U和105D則圍繞主動元件區103設置,例如多晶矽電阻器105R、105L、105U和105D分別設置在主動元件區103的右側、左側、上側和下側。
經由在半導體基底101上方沈積多晶矽層,然後使用微影與蝕刻製程將多晶矽層圖案化,以形成多晶矽電阻器主體,對多晶矽電阻器主體摻雜以第一導電型的摻雜物,例如n型或p型的摻雜物,以形成多晶矽電阻器105R、105L、105U和105D。在一些實施例中,對多晶矽電阻器主體進行p型摻雜物的重摻雜,以形成p+型多晶矽電阻器,例如使用劑量為1E15/cm2的硼(boron)對多晶矽電阻器主體進行摻雜。
使用雷射快速熱退火製程,亦即採用雷射掃瞄退火方式可將多晶矽電阻器主體內的摻雜物活化,藉此形成p+型的多晶矽電阻器105R、105L、105U和105D,雷射掃瞄退火步驟的進行是使用雷測光束110照射積體電路表面的一小區域,並以雷射掃瞄方向120連續在半導體基底101的全部表面上掃瞄照射區域。在一些實施例中,雷射掃瞄方向120係垂直於主動元件區103的右側邊103R和左側邊103L。
參閱第2圖,其為依據一些實施例,積體電路100的局部剖面示意圖,其中的多晶矽區域105在雷射快速熱退火製程期間被雷射光束110照射。多晶矽區域105例如多晶矽電
阻器係形成在半導體基底101內的介電層107上,在一些實施例中,介電層107為經由淺溝槽隔絕(shallow trench isolation;STI)製程形成的場氧化層(field oxide layer),因此介電層107也可稱為淺溝槽隔絕(STI)結構。如第2圖所示,使用雷射光束110以雷射掃瞄方向120照射多晶矽區域105,藉此活化在多晶矽區域105內的摻雜物。雷射光束110是以大於0度並且小於90度的角度θ設置,此角度θ是從垂直於半導體基底101表面的方向開始計算,而多晶矽區域105的頂部表面則被視為水平方向,角度θ的範圍通常是從約70度至約75度,在70度至75度範圍內的角度θ可以提高從雷射光束110至多晶矽區域105的功率轉移效率。
雷射光束110係以雷射掃瞄方向120橫越半導體基底101的整個頂部表面照射多晶矽區域105,參閱第1圖,在雷射快速熱退火製程期間,雷射光束110以相同的雷射掃瞄方向120掃瞄照射全部的多晶矽電阻器105R、105L、105U和105D的多晶矽主體,當雷射光束110以雷射掃瞄方向120掃瞄照射多晶矽電阻器105R、105U和105D的多晶矽主體時,主動元件區103不會影響雷射光束110的加熱。然而,當雷射光束110以相同的雷射掃瞄方向120掃瞄照射在主動元件區103左側的多晶矽電阻器105L的多晶矽主體時,主動元件區103將會影響雷射光束110的加熱,並使得額外的熱能累積在多晶矽電阻器105L上,而額外的加熱將會導致多晶矽電阻器105L的電阻值降低。因此,在習知的製造方法中,雷射快速熱退火製程會引起在積體電路100的不同位置上的多晶矽電阻
器105R、105L、105U和105D之間的電阻值不匹配的問題,在一些實施例中,左側的多晶矽電阻器105L的電阻值會比其他位置的多晶矽電阻器105R、105U和105D的電阻值低了約10%。
多晶矽電阻器之間的電阻值不匹配會降低積體電路的效能,特別是發生在射頻收發器(radio frequency(RF)transceivers)中的I-Q不匹配,以及在大多數的類比電路中,偏壓點的準確度(biasing point accuracy)也會受到不良影響。當左側的多晶矽電阻器105L與主動元件區103之間的距離d增加時,主動元件區103對於雷射快速熱退火製程的加熱影響程度會降低,因此,距離d的增加可以改善左側的多晶矽電阻器105L的電阻值。另外,降低主動元件區103在晶圓上的密度也可以改善左側的多晶矽電阻器105L的電阻值。換言之,增加左側的多晶矽電阻器105L與主動元件區103之間的距離d,以及降低主動元件區103在晶圓上的密度,可以改善多晶矽電阻器105R、105L、105U和105D之間的電阻值不匹配問題。然而,上述方法將會導致積體電路佈局的面積增加了約5%至10%。
另一種改善多晶矽電阻器105R、105L、105U和105D之間的電阻值不匹配的方法為微調雷射快速熱退火製程的操作方向,亦即微調雷射光束在晶圓上的雷射掃瞄方向。然而,在晶圓上很難找到一個適用於全部積體電路的雷射掃瞄方向的單一方向,來改善多晶矽電阻器之間的電阻值不匹配。
因此,本揭示提供在積體電路中製作多晶矽電阻
器的方法,其可以改善不同位置上的多晶矽電阻器之間的電阻值不匹配問題,而且不需要增加左側的多晶矽電阻器105L與主動元件區103之間的距離d,也不需要降低主動元件區103在晶圓上的密度,同時也不需要改變雷射快速熱退火製程的操作方向,亦即不需要改變在晶圓上的雷射掃瞄方向120。依據本揭示的一些實施例,對多晶矽電阻器的多晶矽主體摻雜以第一導電型的第一摻雜物,例如n型或p型的摻雜物,此外,更對多晶矽電阻器的多晶矽主體摻雜以第二摻雜物,第二摻雜物係選自於第IIIA族元素和第IVA族元素中原子量大於矽原子量的元素。摻雜以第一摻雜物和第二摻雜物的多晶矽電阻器主體具有第一晶粒尺寸(grain size),第一晶粒尺寸大於僅摻雜以第一摻雜物的多晶矽電阻器主體的初始晶粒尺寸。接著,在多晶矽電阻器主體上進行雷射快速熱退火製程,以活化在多晶矽電阻器主體內的第一摻雜物和第二摻雜物,然後形成多晶矽電阻器。
具有較大晶粒尺寸的多晶矽電阻器主體可以有效地降低活化摻雜物所需的能量,藉此可以降低多晶矽電阻器需要的熱預算(thermal budget),特別是對於先進的製程節點,例如65nm的節點以及其以下的製程節點,使用雷射快速熱退火製程的實施例而言,低的熱預算可以降低多晶矽電阻器對於熱的敏感度,因此,當進行雷射快速熱退火製程時,在積體電路的不同位置處的多晶矽電阻器的電阻值將會一致。換言之,植入第二摻雜物至多晶矽電阻器主體內可以有效地改善由雷射快速熱退火製程所引發的多晶矽電阻器之間的電阻值不匹配
問題。
第3A至3D圖顯示依據一些實施例,製造積體電路100的中間階段之局部剖面示意圖。參閱第3A圖,積體電路100形成在半導體基底101之上和其中,半導體基底101可以是矽晶圓、絕緣體上的矽(silicon-on-insulator;SOI)基底,或其他合適的半導體基底。在一些實施例中,積體電路100包含n通道金屬氧化物半導體(n-channel metal oxide semiconductor;NMOS)區106,其係用於製作N型金屬氧化物半導體電晶體(NMOS transistor),以及p通道金屬氧化物半導體(PMOS)區104,其係用於製作P型金屬氧化物半導體電晶體(PMOS transistor),NMOS區106和PMOS區104設置在如第1圖所示之主動元件區103內。此外,積體電路100還包含被動元件區102,其係用於製作多晶矽電阻器,例如第1圖所示之多晶矽電阻器105R、105L、105U和105D。
介電層107可以是經由淺溝槽隔絕(STI)製程形成的場氧化層,其係形成在半導體基底101內,以隔絕NMOS區106和PMOS區104,因此介電層107也可稱為淺溝槽隔絕(STI)結構。此外,淺溝槽隔絕(STI)結構107也形成在被動元件區102內,並且位於如第1圖所示之多晶矽電阻器105R、105L、105U和105D底下。
NMOS區106包含閘極介電層150、多晶矽閘極151、閘極側壁間隙物(sidewall spacer)153、n通道輕摻雜區155以及n通道重摻雜區157。PMOS區104包含閘極介電層140、多晶矽閘極141、閘極側壁間隙物143、p通道輕摻雜區145
以及p通道重摻雜區147。被動元件區102包含多晶矽電阻器主體105,以及側壁間隙物108形成在多晶矽電阻器主體105的側壁上。為了簡化圖式,第3A圖僅在被動元件區102繪出一個多晶矽電阻器主體105做為代表,實際上在被動元件區102內形成有複數個多晶矽電阻器主體,例如第1圖所示之多晶矽電阻器105R、105L、105U和105D的多晶矽電阻器主體。
在一些實施例中,經由在半導體基底101上沈積多晶矽膜,然後使用微影與蝕刻製程將多晶矽膜圖案化,以同時形成多晶矽閘極151、多晶矽閘極141和多晶矽電阻器主體105,因此多晶矽閘極151、多晶矽閘極141和此時的多晶矽電阻器主體105具有相同的晶粒尺寸GS1。在一些實施例中,晶粒尺寸GS1的範圍為60Å至70Å。另外,也可以經由沈積介電材料層,例如氧化矽、氮化矽或前述之組合,然後使用微影與蝕刻製程將介電材料層圖案化,以同時形成閘極側壁間隙物153、閘極側壁間隙物143和側壁間隙物108。
在一些實施例中,對多晶矽電阻器主體105進行第一導電型的摻雜物的重摻雜,例如p型摻雜物的重摻雜,以形成p+型多晶矽電阻器。首先,在積體電路100的頂部表面上方形成植入p型摻雜物時使用的第一遮罩130,第一遮罩130暴露出PMOS區104和被動元件區102,並且覆蓋NMOS區106,第一遮罩130可以是經由微影製程形成的光阻圖案。接著,進行植入製程160,將p型的第一摻雜物162例如硼植入位於PMOS區104的多晶矽閘極141內,以及位於被動元件區102的多晶矽電阻器主體105內,在一些實施例中,植入製程
160所使用的p型的第一摻雜物162的劑量約為1E15/cm2。
參閱第3B圖,在植入製程160之後,將第一遮罩130移除。然後,在積體電路100的頂部表面上方形成植入第二摻雜物時使用的第二遮罩170,第二遮罩170暴露出被動元件區102,並且覆蓋NMOS區106和PMOS區104,第二遮罩170可以是經由微影製程形成的光阻圖案。接著,進行植入製程180,將第二摻雜物182植入位於被動元件區102的多晶矽電阻器主體105內。
依據本揭示的實施例,第二摻雜物182係選自於第IIIA族元素和第IVA族元素中原子量大於矽原子量的元素,例如鍺(Ge)、錫(Sn)、鉛(Pb)、鎵(Ga)、銦(In)或鈦(Ti)。在一些實施例中,第二摻雜物182係選自於鍺(Ge)、鎵(Ga)和銦(In)。在一些實施例中,植入製程180在大於30KeV的能量下進行,將劑量為2E14/cm2至1E15/cm2的第二摻雜物182鍺(Ge)植入多晶矽電阻器主體105內。例如,在一實施例中,植入製程180在等於或大於50KeV的能量進行,將劑量為5E14/cm2的鍺(Ge)植入至多晶矽電阻器主體105內。
當植入製程180採用高能量例如50KeV,將第二摻雜物182植入多晶矽電阻器主體105時,可以得到晶粒尺寸變大的多晶矽電阻器主體105,增加1keV的能量可以使得多晶矽電阻器主體的晶粒尺寸增加了約1.1Å。具有較大晶粒尺寸的多晶矽電阻器主體可以更有效地降低活化摻雜物所需的能量,藉此可降低多晶矽電阻器在後續的雷射快速熱退火製程中的熱預算,低的熱預算使得多晶矽電阻器主體對於熱的敏感度
下降,因此,相較於在30KeV的能量下進行的植入製程180,在等於或或大於50KeV的能量下進行的植入製程180可以更有效地改善多晶矽電阻器之間的電阻值不匹配。
在一些實施例中,當植入製程180在30KeV的能量下進行時,如第1圖所示之右側與左側的多晶矽電阻器105R和105L之間電阻值的差異為小於4%。在一些其他實施例中,當植入製程180在50KeV的能量下進行時,如第1圖所示之右側與左側的多晶矽電阻器105R和105L之間電阻值的差異為小於2%。
參閱第3C圖,在植入製程180之後,將第二遮罩170移除。依據本揭示的實施例,具有第一摻雜物162和第二摻雜物182摻雜在其中的多晶矽電阻器主體105的晶粒尺寸GS2會大於前述的晶粒尺寸GS1,在一些實施例中,晶粒尺寸GS2的範圍在約110Å至約120Å。接著,在積體電路100上進行雷射快速熱退火製程190,於雷射快速熱退火製程190期間,雷射光束以雷射掃瞄方向120掃瞄照射積體電路100的頂部表面,藉此活化在多晶矽閘極141和多晶矽電阻器主體105內的摻雜物。
參閱第3D圖,在雷射快速熱退火製程190之後,多晶矽閘極141內的第一導電型的摻雜物162被活化,此外,在多晶矽電阻器主體105內的第一導電型的摻雜物162和第二摻雜物182也被活化。同時,在其他多晶矽電阻器主體,例如積體電路100中的多晶矽電阻器105L、150U和105D的多晶矽電阻器主體內的摻雜物也被活化。然後,在積體電路100的
頂部表面上方形成介電層111,覆蓋NMOS電晶體和PMOS電晶體以及多晶矽電阻器主體105。接著,在多晶矽電阻器主體105上的一對分開的區域中,形成接點109於介電層111中,以完成多晶矽電阻器。
在一些實施例中,於第3A至3D圖所示之製造積體電路100的數個中間階段中,NMOS電晶體的多晶矽閘極151所具有的晶粒尺寸SG1不會改變,並且PMOS電晶體的多晶矽閘極141所具有的晶粒尺寸SG1也不會改變。此外,在第3A和3B圖所示之製造積體電路100的階段中,最初的多晶矽電阻器主體105以及摻雜以第一摻雜物162的多晶矽電阻器主體105也具有晶粒尺寸SG1,多晶矽電阻器主體105的此晶粒尺寸SG1與PMOS電晶體的多晶矽閘極141和NMOS電晶體的多晶矽閘極151的晶粒尺寸SG1相同,在一些實施例中,此多晶矽的晶粒尺寸SG1的範圍在約60Å至約70Å。然而,在第3C和3D圖所示之製造積體電路100的階段中,摻雜以第一摻雜物162和第二摻雜物182的多晶矽電阻器主體105則具有晶粒尺寸SG2,在一些實施例中,此晶粒尺寸SG2的範圍在約110Å至約120Å。
依據本揭示的實施例,積體電路100包含第一多晶矽區,在第一多晶矽區內含有多晶矽電阻器105,多晶矽電阻器105具有晶粒尺寸SG2,也可稱為第一晶粒尺寸SG2。此外,積體電路100還包含第二多晶矽區,在第二多晶矽區內的PMOS電晶體的多晶矽閘極141和NMOS電晶體的多晶矽閘極151具有晶粒尺寸SG1,也可稱為第二晶粒尺寸SG1。在本揭
示的實施例中,第一晶粒尺寸SG2與第二晶粒尺寸SG1不同,而且第一晶粒尺寸SG2大於第二晶粒尺寸SG1,第一多晶矽區為被動元件的一部分,而第二多晶矽區為主動元件的一部分。
另外,第一多晶矽區包含複數個多晶矽電阻器形成在半導體基底上且位於被動元件區內,這些多晶矽電阻器具有第一晶粒尺寸SG2,第二多晶矽區包含複數個多晶矽閘極形成在半導體基底上且位於主動元件區內,這些多晶矽閘極具有與第一晶粒尺寸SG2不同的第二晶粒尺寸SG1,第一晶粒尺寸SG2大於第二晶粒尺寸SG1。此外,多晶矽電阻器圍繞主動元件區設置,並且設置在主動元件區不同側的多晶矽電阻器具有一致的電阻值。
依據本揭示的實施例,多晶矽電阻器具有p型的第一摻雜物以及第二摻雜物在其中,第二摻雜物係選自於第IIIA族元素和第IVA族元素中原子量大於矽原子量的元素,具有第二摻雜物植入在其中的多晶矽電阻器具有較大的第一晶粒尺寸SG2,可以有效地降低其中摻雜物的活化能量,藉此降低了多晶矽電阻器的熱預算,特別是對於先進的製程節點,例如在65nm以及其以下的製程節點中使用雷射快速熱退火製程的實施例,低的熱預算可以使得全部的多晶矽電阻器主體對於熱的敏感度降低,因此,在多晶矽電阻器主體上進行雷射快速熱退火製程時,位於積體電路的不同位置處的這些多晶矽電阻器的電阻值會一致。因此,植入第二摻雜物至多晶矽電阻器主體內,可以有效地改善由雷射快速熱退火製程所引發的多晶矽電阻器之間的電阻值不匹配的問題。
在具有相同的主動元件區密度,以及從多晶矽電阻器至主動元件區的距離相同的條件下,相較於沒有植入第二摻雜物至多晶矽電阻器主體的積體電路,本揭示之實施例的積體電路在50KeV或大於50KeV的能量下,植入第二摻雜物至多晶矽電阻器主體內,其可以改善多晶矽電阻器之間的電阻值不匹配程度約4至6倍。因此,依據本揭示的實施例可以放寬主動元件區的密度要求,以及從多晶矽電阻器至主動元件區的距離要求,其有助於讓類比電路的積體電路佈局面積達到較小化。
雖然本發明已揭露較佳實施例如上,然其並非用以限定本發明,在此技術領域中具有通常知識者當可瞭解,在不脫離本發明之精神和範圍內,當可做些許更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定為準。
100‧‧‧積體電路
101‧‧‧半導體基底
102‧‧‧被動元件區
103‧‧‧主動元件區
104‧‧‧PMOS區
105‧‧‧多晶矽電阻器主體
106‧‧‧NMOS區
107‧‧‧淺溝槽隔絕結構
108‧‧‧側壁間隙物
120‧‧‧雷射掃描方向
140、150‧‧‧閘極介電層
141、151‧‧‧多晶矽閘極
143、153‧‧‧閘極側壁間隙物
145‧‧‧P通道輕摻雜區
147‧‧‧P通道重摻雜區
155‧‧‧n通道輕摻雜區
157‧‧‧n通道重摻雜區
190‧‧‧雷射快速熱退火製程
GS1‧‧‧第二晶粒尺寸
GS2‧‧‧第一晶粒尺寸
Claims (30)
- 一種積體電路,包括:一第一多晶矽區形成在一基底上,具有一第一晶粒尺寸,;以及一第二多晶矽區形成在該基底上,具有與該第一晶粒尺寸不同的一第二晶粒尺寸。
- 如申請專利範圍第1項所述之積體電路,其中該第一多晶矽區為一被動元件的一部分,該第二多晶矽區為一主動元件的一部分,並且該第一晶粒尺寸大於該第二晶粒尺寸。
- 如申請專利範圍第2項所述之積體電路,其中該第一多晶矽區具有一p型的第一摻雜物以及一第二摻雜物植入於其中,並且該第二摻雜物係選自於第IIIA族元素和第IVA族元素中原子量大於矽原子量的元素。
- 如申請專利範圍第3項所述之積體電路,其中該第二摻雜物包含鍺、鎵或銦。
- 如申請專利範圍第1項所述之積體電路,其中該第一多晶矽區包含一多晶矽電阻器,該第二多晶矽區包含一多晶矽閘極。
- 如申請專利範圍第5項所述之積體電路,其中該多晶矽電阻器和該多晶矽閘極具有相同的一第一導電型的第一摻雜物植入於其中,並且該多晶矽電阻器更包括一第二摻雜物植入於其中。
- 如申請專利範圍第6項所述之積體電路,更包括一淺溝槽隔絕結構形成在該基底內且圍繞一主動元件,其中該多晶矽 電阻器形成在該淺溝槽隔絕結構上。
- 一種積體電路,包括:一第一多晶矽區,包含複數個多晶矽電阻器,具有一第一晶粒尺寸,該第一多晶矽區形成在一基底上,且位於一被動元件區內;以及一第二多晶矽區,包含複數個多晶矽閘極,具有與該第一晶粒尺寸不同的一第二晶粒尺寸,該第二多晶矽區形成在該基底上,且位於一主動元件區內。
- 如申請專利範圍第8項所述之積體電路,其中該些多晶矽電阻器圍繞該主動元件區設置,並且位於該主動元件區的不同側邊的全部該些多晶矽電阻器具有一致的電阻值。
- 如申請專利範圍第8項所述之積體電路,其中該第一晶粒尺寸大於該第二晶粒尺寸。
- 如申請專利範圍第8項所述之積體電路,其中該第一多晶矽區具有一p型的第一摻雜物以及一第二摻雜物植入於其中,並且該第二摻雜物係選自於第IIIA族元素和第IVA族元素中原子量大於矽原子量的元素。
- 如申請專利範圍第11項所述之積體電路,其中該第二摻雜物包含鍺、鎵或銦。
- 如申請專利範圍第8項所述之積體電路,其中該多晶矽電阻器和該多晶矽閘極具有相同的一第一導電型的第一摻雜物植入於其中,並且該多晶矽電阻器更包括一第二摻雜物植入於其中。
- 如申請專利範圍第13項所述之積體電路,更包括一淺溝槽 隔絕結構形成在該基底內且圍繞該主動元件區,其中該些多晶矽電阻器形成在該淺溝槽隔絕結構上。
- 一種積體電路的製造方法,包括:形成一第一多晶矽區在一基底上,該第一多晶矽區具有一初始晶粒尺寸;植入一第一導電型的一第一摻雜物以及一第二摻雜物至該第一多晶矽區內,在該植入製程之後,該第一多晶矽區具有一第一晶粒尺寸大於該初始晶粒尺寸;以及對該第一多晶矽區進行一雷射快速熱退火製程。
- 如申請專利範圍第15項所述之積體電路的製造方法,其中該第一摻雜物包含一p型摻雜物,並且該第二摻雜物係選自於第IIIA族元素和第IVA族元素中原子量大於矽原子量的元素。
- 如申請專利範圍第16項所述之積體電路的製造方法,其中該第二摻雜物包含鍺、鎵或銦。
- 如申請專利範圍第16項所述之積體電路的製造方法,其中該第二摻雜物以大於30KeV的能量和2E14/cm2至1E15/cm2的劑量植入至該第一多晶矽區內。
- 如申請專利範圍第16項所述之積體電路的製造方法,其中該第二摻雜物以等於50KeV或大於50KeV的能量和5E14/cm2的劑量植入至該第一多晶矽區內。
- 如申請專利範圍第15項所述之積體電路的製造方法,更包括:形成一第二多晶矽區在該基底上,該第二多晶矽區具有該 初始晶粒尺寸;植入該第一導電型的第一摻雜物至該第二多晶矽區內,在該植入製程之後,該第二多晶矽區具有一第二晶粒尺寸等於該初始晶粒尺寸;以及對該第二多晶矽區進行該雷射快速熱退火製程。
- 如申請專利範圍第20項所述之積體電路的製造方法,其中該第一多晶矽區包含一多晶矽電阻器形成在一被動元件區內,並且該第二多晶矽區包含一多晶矽閘極形成在一主動元件區內。
- 如申請專利範圍第20項所述之積體電路的製造方法,更包括:形成一第一遮罩,暴露出該第一多晶矽區和該第二多晶矽區,以植入該第一摻雜物至該第一多晶矽區和該第二多晶矽區內;以及形成一第二遮罩,暴露出該第一多晶矽區且覆蓋該第二多晶矽區,以植入該第二摻雜物至該第一多晶矽區內。
- 如申請專利範圍第22項所述之積體電路的製造方法,更包括形成一淺溝槽隔絕結構在該基底內,其中該第一多晶矽區形成在該淺溝槽隔絕結構上。
- 一種積體電路的製造方法,包括:形成一第一多晶矽區在一基底上,包含複數個多晶矽電阻器主體,其中該些多晶矽電阻器主體具有一初始晶粒尺寸,並且該些多晶矽電阻器主體圍繞一主動元件區;植入一第一導電型的第一摻雜物以及一第二摻雜物至該些 多晶矽電阻器主體內,在該植入製程之後,該些多晶矽電阻器主體具有一第一晶粒尺寸大於該初始晶粒尺寸;以及以一雷射掃瞄方向移動一雷射光束,對該些多晶矽電阻器主體進行一雷射快速熱退火製程,其中該雷射掃描方向垂直於該主動元件區的一第一側邊和一第二側邊。
- 如申請專利範圍第24項所述之積體電路的製造方法,其中該雷射光束以該雷射掃描方向照射鄰接於該主動元件區的該第一側邊的一第一多晶矽電阻器主體之後,沿著該雷射掃描方向照射鄰接於該主動元件區的該第二側邊的一第二多晶矽電阻器主體。
- 如申請專利範圍第25項所述之積體電路的製造方法,其中該第二摻雜物以大於30KeV的能量和2E14/cm2至1E15/cm2的劑量植入至該些多晶矽電阻器主體內。
- 如申請專利範圍第25項所述之積體電路的製造方法,其中該第二摻雜物以等於50KeV或大於50KeV的能量和5E14/cm2的劑量植入至該些多晶矽電阻器主體內。
- 如申請專利範圍第24項所述之積體電路的製造方法,更包括:形成一第二多晶矽區在該基底上且位於該主動元件區內,該第二多晶矽區包含複數個多晶矽閘極,且該些多晶矽閘極具有該初始晶粒尺寸;植入該第一導電型的第一摻雜物至該些多晶矽閘極內,在該植入製程之後,該些多晶矽閘極具有一第二晶粒尺寸等於該初始晶粒尺寸;以及 對該些多晶矽閘極進行該雷射快速熱退火製程。
- 如申請專利範圍第28項所述之積體電路的製造方法,更包括:形成一第一遮罩,暴露出該第一多晶矽區和該第二多晶矽區,以植入該第一摻雜物至該些多晶矽電阻器主體和該些多晶矽閘極內;以及形成一第二遮罩,暴露出該第一多晶矽區且覆蓋該第二多晶矽區,以植入該第二摻雜物至該些多晶矽電阻器主體內。
- 如申請專利範圍第24項所述之積體電路的製造方法,更包括形成一淺溝槽隔絕結構在該基底內,其中該些多晶矽電阻器主體形成在該淺溝槽隔絕結構上。
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DE102017205448A1 (de) * | 2017-03-30 | 2018-10-04 | Infineon Technologies Ag | Ein Hochfrequenz-Widerstandselement |
US10868108B2 (en) * | 2018-06-27 | 2020-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having high voltage lateral capacitor and manufacturing method thereof |
US20220238516A1 (en) * | 2021-01-25 | 2022-07-28 | Yanbiao Pan | Polysilicon resistor using reduced grain size polysilicon |
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US9508786B2 (en) | 2016-11-29 |
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US20160043162A1 (en) | 2016-02-11 |
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