TW201501242A - 用於堆疊式矽晶互連技術產物之無基板插入物技術 - Google Patents

用於堆疊式矽晶互連技術產物之無基板插入物技術 Download PDF

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TW201501242A
TW201501242A TW103107854A TW103107854A TW201501242A TW 201501242 A TW201501242 A TW 201501242A TW 103107854 A TW103107854 A TW 103107854A TW 103107854 A TW103107854 A TW 103107854A TW 201501242 A TW201501242 A TW 201501242A
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layer
metal segments
insert
substrateless
metallization
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TWI598995B (zh
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Woon-Seong Kwon
Suresh Ramalingam
Namhoon Kim
Joong-Ho Kim
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Xilinx Inc
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Abstract

一種用於堆疊式矽晶互連技術(SSIT)產物的無基板插入物，其包含：複數個金屬化層，該金屬化層的至少一最底層含有複數個金屬節段，其中每一個該複數個金屬節段是構成於該金屬化層之最底層的頂部表面與底部表面之間，並且該金屬節段是由該最底層中的介電材料所分隔；以及一介電層，其係經構成於該最底層的底部表面上，其中該介電層含有一或更多開口以供接觸於該最底層的複數個金屬節段。

Description

用於堆疊式矽晶互連技術產物之無基板插入物技術
本案所說明的具體實施例為概略關於堆疊式矽晶互連技術(SSIT)產物，並且尤其是關於一種用於SSIT產物的無基板插入物技術。
矽晶堆疊式互連技術(SSIT)牽涉到將多個積體電路(IC)晶粒封裝於一單一封裝中，而此封裝含有一插入物和一封裝基板。運用SSIT可令像是FPGA的IC產物延展至更高的密度、更低的功率、更強的功能性以及應用特定平台解決方案而擁有低成本與快速上市時間的優點。
傳統上，SSIT產物是利用插入物所實作，其包含一插入物基板層，而在該插入物基板層的頂部上建構有多個穿透矽質通道(TSV)和額外的金屬化層。該插入物可提供IC晶粒與該封裝基板之間的連接。然而，製造用於SSIT產物而具有TSV的插入物基板層會是一項複雜的製程。其原因在於需進行多項製造步驟方可構成具有TSV的插入物基板層，這些步驟包含：在該插入物基板層中構成TSV，執行背側薄化處理以及化學汽相沉積(CVD)或化學機械平面化(CMP)，並且提供薄化晶圓處置。因此，對於某些應用項目來說，可能並不希望構成包含一擁有具穿透矽質通道(TSV)的插入物基板層之插入物的SSIT產物。
一種用於堆疊式矽晶互連技術(SSIT)產物的無基板插入物，其包含：複數個金屬化層，該金屬化層的至少一最底層含有複數個金屬節段，其中每一個該複數個金屬節段是構成於該金屬化層之最底層的頂部表面與底部表面之間，並且該金屬節段是由該最底層中的介電材料所分隔；以及一介電層，其係經構成於該最底層的底部表面上，其中該介電層含有一或更多開口以供接觸於該最底層中的複數個金屬節段之至少一部份。
選擇性地，該複數個金屬節段可含有銅。
選擇性地，該無基板插入物亦可包含一具有一或更多開口的鈍化層，該開口在空間上是對應於該介電層處的該一或更多開口，其中該鈍化層是構成於該介電層上。
選擇性地，該無基板插入物亦可包含一凸塊下金屬(UBM)層，其接觸於該最底層中之複數個金屬節段的至少一部份，該UBM層是構成於該最底層上。
選擇性地，該無基板插入物可為組態設定以支撐該金屬化層的最頂層之頂部表面上的複數個IC晶粒。
選擇性地，該複數個IC晶粒可包含異質性IC晶粒。
選擇性地，該複數個IC晶粒可包含同質性IC晶粒。
選擇性地，在該金屬化層之最底層裡不同的複數個金屬節段之群組可分別地對應於複數個IC晶粒。
選擇性地，該複數個金屬節段的不同群組可具有不同的個別 節段密度。
選擇性地，每一個該複數個金屬化層可含有複數個金屬節段，並且在該金屬化層之其一者中的多個金屬節段可為不同於在該金屬化層之另一者中的多個金屬節段。
一種用以構成具有無基板插入物之堆疊式矽晶互連技術(SSIT)產物的方法，其包含：在一基板上構成一介電層；在該介電層上構成複數個金屬化層，該金屬化層的至少一最底層含有複數個金屬節段，其中每一個該金屬節段是構成於該金屬化層之最底層的頂部表面與底部表面之間，並且該金屬節段是由該最底層中的介電材料所分隔；將複數個IC晶粒設置在該複數個金屬化層之最頂金屬化層的頂部表面上；在該介電層處構成一或更多開口以供接觸於該複數個金屬化層之最底層中的複數個金屬節段之至少一部份，其中具有該一或更多開口的介電層和該複數個金屬化層構成該無基板插入物；以及將該無基板插入物設置在一封裝基板上以構成該SSIT產物。
選擇性地，移除該基板的動作可包含利用機械研磨製程以薄化該基板，以及利用蝕刻製程以移除薄化後的該基板。
選擇性地，該複數個IC晶粒可包含異質性IC晶粒。
選擇性地，該複數個IC晶粒可包含同質性IC晶粒。
選擇性地，該方法可進一步包含利用C4凸塊以將該無基板插入物固定於該封裝基板上俾構成該SSIT產物。
選擇性地，該方法可進一步包含在於該介電層處構成該一或更多開口之後在該介電層上構成一鈍化層，其中該鈍化層含有一或更多開 口，此等在空間上是對應於該介電層處的一或更多開口，並且其中該無基板插入物進一步含有該鈍化層。
選擇性地，該方法可進一步包含在該一或更多金屬化層的最底層上構成一凸塊下金屬(UBM)層，其中該凸塊下金屬層為接觸於該一或更多金屬化層的最底層中之該複數個金屬節段的至少一部份，並且其中該無基板插入物進一步含有該UBM層。
選擇性地，在該一或更多金屬化層之最底層裡不同的複數個金屬節段之群組可對應於該複數個IC晶粒的個別者。
選擇性地，該複數個金屬節段的不同群組可具有不同的個別節段密度。
選擇性地，每一個該複數個金屬化層可含有複數個金屬節段，並且在該金屬化層之其一者中的多個金屬節段可為不同於在該金屬化層之另一者中的多個金屬節段。
自閱讀後載詳細說明將能顯知其他與進一步的特點和特性。
100‧‧‧堆疊式矽晶互連技術(SSIT)產物
101、101’‧‧‧積體電路(IC)晶粒
103‧‧‧插入物
105‧‧‧插入物基板層
107‧‧‧穿透矽質通道(TSV)
109‧‧‧金屬化層
111‧‧‧金屬節段
113‧‧‧介電材料
115‧‧‧群組
116‧‧‧插入物基板
117‧‧‧微凸塊
119‧‧‧C4凸塊
121‧‧‧封裝基板
123‧‧‧模鑄裹封
200‧‧‧SSIT產物
201‧‧‧無基板插入物
203‧‧‧介電層
205‧‧‧鈍化層
207‧‧‧凸塊下金屬層
301-317‧‧‧項目
401‧‧‧基板
所附圖式說明本揭所述之各式特性的設計與運用方式，其中類似構件是按共同的參考編號所參照。然該繪圖並不必然地依循比例所繪。為更佳地瞭解如何達成前述與其他優點和目的，本文中將依隨附圖式所示以呈現更為特定的說明。該圖式僅描繪出多項示範性特性，且因而不應將此視為限制本案的申請專利範圍。
圖1為說明一運用一插入物之堆疊式矽晶互連技術(SSIT)產物的截面略圖，而該插入物包含一具有多個穿透矽質通道的插入物基板層。
圖2為一說明一運用無基板插入物技術之SSIT產物的截面略圖。
圖3為一說明一種用以製造運用無基板插入物技術的SSIT產物之方法的流程圖。
圖4-1至4-9為說明一種用以製造運用無基板插入物技術的SSIT產物之方法的截面略圖。
後文中將參照圖式以說明各式特性。應注意到該圖式並非依比例所繪製，並且具有類似結構或功能的構件在全部圖式裡是以相仿參考編號所表示。應注意到該圖式僅欲有助於說明該特性。該並非欲以作為本發明的窮舉性說明或為以限制本發明的範疇。此外，示範性具體實施例無須具備全部的所示特性或優點。併同於一特定具體實施例所描述的特性或優點並不必然地受限於該具體實施例，而是能夠在任何其他具體實施例中加以實作，即使未經如此說明亦然。
矽晶堆疊式互連技術(SSIT)牽涉到將多個積體電路(IC)晶粒封裝於一單一封裝中，而此封裝含有一插入物和一封裝基板。運用SSIT可令IC產物，像是且包含FPGA和其他類型的產物，延展至更高的密度、更低的功率、更強的功能性以及應用特定平台解決方案而擁有低成本與快速上市時間的優點。
圖1為一說明一堆疊式矽晶互連技術(SSIT)產物100的截面略圖。該SSIT產物100含有一封裝基板121、一插入物103以及一或更多IC晶粒101、101’。
該積體電路晶粒101、101’可經由一或更多微凸塊117而功 能性地連接至該插入物103。該積體電路晶粒101、101’可為利用一模鑄裹封123所裹封。該模鑄裹封123可提供抗防於可能對該積體電路晶粒101、101’效能造成影響之環境因素(即如溫度、外部污染等等)的保護。此外，該模鑄裹封123可對該積體電路晶粒101、101’提供機械穩定性。
而該插入物103則含有複數個金屬化層109以及一具有多個穿透矽質通道(TSV)107的插入物基板層105。
各個金屬化層109可含有複數個金屬節段111，而這些節段是由介電材料113所分隔。該金屬節段可為由銅或任意數量的其他種類金屬所組成。該介電材料113可含有二氧化矽及任何其他的介電材料。各個金屬化層109中該金屬節段111可含有對應於不同IC晶粒101、101’的不同群組115。例如，一金屬化層109可含有該金屬節段的第一群組，此群組是對應於一第一IC晶粒101，以及該金屬節段的第二群組，此群組則是對應於一第二IC晶粒101’。此外，該金屬節段111的各個不同群組115可具有不同的節段密度。例如，一金屬化層109可含有該金屬節段111的一第一群組115，此群組具有特定數量的金屬節段111(亦即節段密度)，以及該金屬節段111的一第二群組115，此群組具有不同數量的金屬節段111(亦即節段密度)。一群組115可僅含單一個金屬節段111或是複數個金屬節段111。
該插入物基板層105含有多個TSV 107。該插入物103可經由一或更多C4凸塊119提供該IC晶粒101、101’與該封裝基板121之間的連接。
該插入物103含有複數個金屬化層109和具有多個TSV 107的插入物基板層105，可提供該IC晶粒101、101’與該封裝基板121之間 的連接，以及對於該SSIT產物100的機械穩定性。不過，牽涉到製造出用於該SSIT產物100且具有多個TSV 107之插入物基板層105的複雜度可能會非常高。其原因在於需進行多項製造步驟方可構成具有TSV 107的插入物基板層105，這些步驟包含：在該插入物基板116中構成TSV 107，執行背側薄化處理以及化學汽相沉積(CVD)或化學機械平面化(CMP)，並且提供薄化晶圓處置。因此，對於某些應用項目來說，可能並不希望構成包含一擁有具穿透矽質通道(TSV)107的插入物基板層105之插入物103的SSIT產物100。藉由運用一並未實作具有穿透矽質通道之插入物基板層的插入物，可供實現一種較為簡易的製造程序，並同時仍能針對於一些包含具有成本敏感性之微小形式因數裝置的應用項目保持高密度互連。
圖2為一說明一運用無基板插入物技術之SSIT產物的截面略圖。圖2中的SSIT產物200含有一封裝基板121、一無基板插入物103以及一或更多IC晶粒101、101’。
該積體電路晶粒101、101’可經由一或更多微凸塊117而功能性地連接至該無基板插入物201。該積體電路晶粒101、101’可為利用一模鑄裹封123所裹封。該模鑄裹封123係提供可能對該積體電路晶粒101、101’效能造成影響之環境因素(即如溫度、外部污染等等)的保護。此外，該模鑄裹封123可對該積體電路晶粒101、101’提供機械穩定性。
在一些情況下，該積體電路晶粒101、101’可為異質性IC晶粒。例如，一第一IC晶粒101相較於一第二IC晶粒101’可執行不同的功能性並且具有不同的規格。在其他情況下，該積體電路晶粒101、101’則可為同質性IC晶粒。例如，一第一IC晶粒101相較於一第二IC晶粒101’ 可執行相同的功能性並且具有相同的規格。
該無基板插入物201亦含有複數個金屬化層109。各個金屬化層109可含有複數個金屬節段111，而這些節段是由介電材料113所分隔。該金屬節段可為由銅或任意數量的其他種類金屬所組成。該介電材料113可含有二氧化矽及任何其他的介電材料。
各個金屬化層109中該金屬節段111可含有對應於不同IC晶粒101、101’的不同群組115。例如，一金屬化層109可含有該金屬節段的第一群組，此群組是對應於一第一IC晶粒101，以及該金屬節段的第二群組，此群組則是對應於一第二IC晶粒101’。一群組115可僅含單一個金屬節段111或是複數個金屬節段111。圖2中雖僅說明該金屬節段111為兩個不同群組115，然熟諳本項技藝之人士將能知曉確可依照該SSIT產物200的特定應用項目在該金屬節段111設有任意數量的不同群組115。
此外，該金屬節段111的各個不同群組115可具有不同的節段密度。例如，一金屬化層109可含有該金屬節段111的一第一群組115，此群組具有特定數量的金屬節段111(亦即節段密度)，以及該金屬節段111的一第二群組115，此群組具有不同數量的金屬節段111(亦即節段密度)。在各個金屬化層109中該金屬節段111之各個不同群組115的節段密度可為依照對於該SSIT產物200之IC晶粒101、101’的組態而定。例如，一金屬化層之金屬節段111中對應於具有低連接數量之第一IC晶粒的第一群組115相較於該金屬化層之金屬節段111中對應於具有高連接數量之第二IC晶粒的第二群組115可擁有較低的節段密度。在不同金屬化層109中之金屬節段111裡對應到相同IC晶粒之多個群組的節段密度則無須為相同。
在所示圖式中，該金屬化層109其一者中(即如中央者)之金屬節段的數量是不同於該金屬化層109另一者中(即如最底層109)之金屬節段111的數量。或另者，該金屬化層109之中的兩個或更多者可具有相同數量的金屬節段。
該無基板插入物201亦含有一介電層203。該介電層203是構成於該金屬化層109之最底層中的底部表面上，並且含有一或更多開口以供接觸於該金屬化層109之最底層中的複數個金屬節段111。該介電層203可含有二氧化矽及任何其他的適當介電材料。
在一些情況下，可於該介電層203上構成一鈍化層205。該鈍化層205亦可含有一或更多開口以供接觸於該金屬化層109之最底層中的複數個金屬節段111。該鈍化層205的目的是在該SSIT產物200的處置過程中提供應力緩衝。該鈍化層205可為由有機聚醯亞胺或是任何其他的適當材料所組成。
在一些情況下，一凸塊下金屬層207可為構成於該金屬化層109之最底層的一底部表面上，而該介電層203和該鈍化層205在此具有開口。該凸塊下金屬層207是與該金屬化層109之最底層中的金屬節段111相接觸，並可提供為以稍後將該插入物201連接至該封裝基板121的點處/範圍。
一或更多的C4凸塊119可提供該封裝基板121與該無基板插入物201之間的連接。該C4凸塊119可為構成於該凸塊下金屬層207與該封裝基板121的一接片(未予圖示)之間。
藉由運用一並未實作具有穿透矽質通道之插入物基板層的 無基板插入物，可供實現一種較為簡易的製造程序，並同時仍能針對於一些包含具有成本敏感性之微小形式因數裝置的應用項目保持高密度互連。
圖3為一說明一種用以製造運用無基板插入物技術的SSIT產物之方法的流程圖。圖3應併同於圖4-1至4-9而參照，該圖式說明一種用以製造運用無基板插入物技術的SSIT產物之方法的截面略圖。
首先，在一基板上構成一介電層，即如項目301所示者。該介電層可含有二氧化矽及任何其他的適當介電材料。該介電層可為利用任意數量的不同沉積技術所構成。
一旦構成該介電層後，即可在該介電層上構成含有多個由介電材料所分隔之金屬節段的複數個金屬化層，即如項目303所示者。圖4-1顯示一截面視圖，此圖描繪項目301和303的最終結果。尤其，圖4-1說明一經構成於基板401上的介電層203(這是獲自於項目301)。同時也包含經構成於該介電層203上的複數個金屬化層109(這是獲自於項目303)。該金屬化層109含有多個金屬節段111，這些節段可為由銅或者任意數量的其他種類金屬所組成。該介電材料203可含有二氧化矽及任何其他的介電材料。
各個金屬化層109中該金屬節段111可含有對應於不同IC晶粒的不同群組115。例如，一金屬化層109可含有該金屬節段111的第一群組115，此群組是對應於一第一IC晶粒，以及該金屬節段111的第二群組115，此群組則是對應於一第二IC晶粒。重點是應注意到可根據所予構成之SSIT產物的特定應用項目來運用該金屬節段111之任何數量的不同群組115。
此外，該金屬節段111的各個不同群組115可具有不同的節 段密度。例如，一金屬化層109可含有該金屬節段111的一第一群組，此群組具有特定數量的金屬節段111(亦即節段密度)，以及該金屬節段111的一第二群組115，此群組具有不同數量的金屬節段111(亦即節段密度)。在各個金屬化層109中該金屬節段111之各個不同群組115的節段密度可為依照所予構成的SSIT產物之IC晶粒的組態而定。例如，一金屬化層109之金屬節段111中對應於具有低連接數量之第一IC晶粒的第一群組115相較於該金屬化層109之金屬節段111中對應於具有高連接數量之第二IC晶粒的第二群組115可擁有較低的節段密度。然在不同金屬化層109中之金屬節段111裡對應到相同IC晶粒之多個群組115的節段密度則無須為相同(亦即該可為相同或相異)。
現返回圖3，其次，可將複數個IC晶粒設置在一最頂金屬化層的頂部表面上，即如項目305所示。圖4-2顯示一截面視圖，此圖描繪此項製造處理的最終結果。在所示圖式中，可設置該複數個IC晶粒101、101’以使得該能夠經由微凸塊117連接至該最頂金屬化層109的金屬節段111。
在一些情況下，該積體電路晶粒101、101’可為異質性IC晶粒。例如，一第一IC晶粒101相較於一第二IC晶粒101’可執行不同的功能性並且具有不同的規格。在其他情況下，該積體電路晶粒101、101’則可為同質性IC晶粒。例如，一第一IC晶粒101相較於一第二IC晶粒101’可執行相同的功能性並且具有相同的規格。
現返回圖3，然後可利用晶圓模鑄處理以裹封該IC晶粒，即如項目307所示。圖4-3顯示一截面視圖，此圖描繪此項製造步驟的最終 結果。在所示圖式中，該模鑄裹封123裹封該IC晶粒101、101’。該模鑄裹封123可提供抗防於可能對該IC晶粒101、101’效能造成影響之環境因素(即如溫度、外部污染等等)的保護。此外，該模鑄裹封123可對該IC晶粒101、101’提供機械穩定性。
現返回圖3，接著可移除該基板，即如項目309處所示。移除該基板的程序可分為兩個部份。首先可利用機械研磨/拋光程序以薄化該基板，在一些具體實施例裡可將該基板薄化自20下至50μm的任處。圖4-4顯示一截面視圖，此圖描繪薄化該基板401的最終結果。在向下薄化該基板401之後，接下來可利用高選擇性矽晶蝕刻製程以移除薄化後的該基板401。圖4-5顯示一截面視圖，此圖描繪移除該基板401的最終結果。
接著返回圖3，在移除該基板401之後，可在該介電層處構成一或更多開口，即如項目311處所示者。圖4-6顯示一截面視圖，此圖描繪構成該一或更多開口的最終結果。在該介電層203處所構成的一或更多開口會延伸穿過該介電層203，並且可供接觸於該複數個金屬化層109之最底層109中的複數個金屬節段111。該一或更多開口可為利用高選擇性的矽晶蝕刻製程所構成。
現返回圖3，當既已於該介電層203中構成該一或更多開口之後，可在該介電層203上選擇性地構成一鈍化層，即如項目313處所示者。圖4-7顯示一截面視圖，此圖描繪構成該鈍化層205的最終結果。該鈍化層205亦可含有一或更多開口，其開口在空間上是對應於位在該介電層203處的一或更多開口以供接觸於該金屬化層109之最底層109中的複數個金屬節段111。該鈍化層205的目的是在構成該SSIT產物的處置過程中提供應力 緩衝。該鈍化層205可為由有機聚醯亞胺或是任何其他的適當材料所組成。
現返回圖3，當既已於該介電層203上構成該鈍化層205後，可在該金屬化層109的最底層109上選擇性地在構成一凸塊下金屬層，即如項目315處所示者。圖4-8顯示一截面視圖，此圖描繪構成該凸塊下金屬層207的最終結果。該凸塊下金屬層207可為構成於該金屬化層109之最底層109的一底部表面上，而該介電層203和該鈍化層205在此具有開口。該凸塊下金屬層207是與該金屬化層109之最底層109的金屬節段111相接觸，並可提供為以稍後將該插入物連接至該封裝基板的點處/範圍。
在所示圖式裡，該複數個金屬化層109、該介電層203、該鈍化層205及該凸塊下金屬層207併同地構成該無基板插入物201。在一些其中並未構成該鈍化層205及/或該凸塊下金屬層207的情況下，該無基板插入物201可為由該複數個金屬化層109與該介電層203所構成。
現返回圖3，一旦既已構成該凸塊下金屬層207之後，即可將該無基板插入物201和該IC晶粒101、101’設置在該封裝基板上以構成如項目317所示的SSIT產物。圖4-9中顯示一截面視圖，此圖描繪將該無基板插入物201和該IC晶粒101、101’設置在該封裝基板121上的最終結果。可利用一或更多的C4凸塊119以設置該無基板插入物201和該IC晶粒101、101’而接觸於該封裝基板121。該C4凸塊119可提供該封裝基板121與該無基板插入物201之間的連接。該C4凸塊119可為構成於該凸塊下金屬層207與該封裝基板121的一接片(未予圖示)之間。
即如前文所述，藉由運用一並未實作具有穿透矽質通道之插入物基板層的無基板插入物，可供實現一種較為簡易的製造程序，並同時 仍能針對於一些包含例如具有成本敏感性之微小形式因數裝置的應用項目保持高密度互連。
應注意到，即如在本案文中所使用者，該詞彙「之上」可指直接地或間接地位於其上。例如，當該介電層係經描述為構成於該最底金屬化層的底部表面「之上」時，該介電層可為直接地位於(即如鄰接於)該最底金屬化層的底部表面之上，或者是間接地位於該底部表面之上(即如該介電層可位於該介電層與該最底金屬化層間的另一覆層之上)。而如另一範例，當該IC晶粒係經描述為位於該最頂金屬化層的頂部表面「之上」時，該IC晶粒可為直接地位於(即如鄰接於)該最頂金屬化層的頂部表面之上，或者是間接地位於該頂部表面之上(即如該IC晶粒可位於該IC晶粒與該最頂金屬化層間的另一覆層之上)。
同時，即如在本案文中所使用者，該詞彙「複數個」可指兩個或更多個物項。例如，「複數個」金屬化層可指兩個或更多個金屬化層，這可為或無需所有的可獲用金屬化層。據此，該詞彙「每一個該複數個金屬化層」可指兩個或更多個金屬化層的每一者，其可指所有的可獲用金屬化層，或非所有的可獲用金屬化層。
前文中雖顯示並描述諸多特性，然將能瞭解該並非欲以限制本發明，同時熟諳本項技藝之人士應能知曉確可進行各式變化及修改而不致悖離本發明的範疇。據此，應將本說明書及圖式視為示範性質但不具限制意義。本發明應涵蓋所有各種替代、修改和等同項目。
101、101’‧‧‧積體電路(IC)晶粒
109‧‧‧金屬化層
111‧‧‧金屬節段
113‧‧‧介電材料
115‧‧‧群組
117‧‧‧微凸塊
121‧‧‧封裝基板
123‧‧‧模鑄裹封
200‧‧‧SSIT產物
201‧‧‧無基板插入物
203‧‧‧介電層
205‧‧‧鈍化層
207‧‧‧凸塊下金屬層

Claims (20)

  1. 一種用於堆疊式矽晶互連技術(SSIT)產物的無基板插入物，其包括：複數個金屬化層，該金屬化層的至少一最底層包括複數個金屬節段，其中每一個該複數個金屬節段係構成於該金屬化層之最底層的頂部表面與底部表面之間，並且該金屬節段係由該最底層中的介電材料所分隔；以及一介電層，其係經構成於該最底層的底部表面上，其中該介電層包括一或更多開口以供接觸於該最底層的複數個金屬節段。
  2. 如申請專利範圍第1項所述之無基板插入物，其中該複數個金屬節段包括銅。
  3. 如申請專利範圍第1項所述之無基板插入物，進一步包含一具有一或更多開口的鈍化層，該開口在空間上係對應於該介電層處的該一或更多開口，其中該鈍化層係構成於該介電層上。
  4. 如申請專利範圍第1項所述之無基板插入物，進一步包含一凸塊下金屬(UBM)層，其接觸於該最底層中之複數個金屬節段的至少一些金屬節段，該UBM層係構成於該最底層上。
  5. 如申請專利範圍第1項所述之無基板插入物，其中該無基板插入物係經組態設定以支撐該金屬化層的最頂層之頂部表面上的複數個IC晶粒。
  6. 如申請專利範圍第5項所述之無基板插入物，其中該複數個IC晶粒包括異質性IC晶粒。
  7. 如申請專利範圍第5項所述之無基板插入物，其中該複數個IC晶粒包括同質性IC晶粒。
  8. 如申請專利範圍第5項所述之無基板插入物，其中在該金屬化層之最底層中的複數個金屬節段之不同群組係分別地對應於複數個IC晶粒。
  9. 如申請專利範圍第8項所述之無基板插入物，其中該複數個金屬節段的不同群組具有不同的個別節段密度。
  10. 如申請專利範圍第1項所述之無基板插入物，其中每一個該複數個金屬化層包括複數個金屬節段，並且在該金屬化層之其中一者的多個金屬節段不同於在該金屬化層之另一者的多個金屬節段。
  11. 一種用以構成具有無基板插入物之堆疊式矽晶互連技術(SSIT)產物的方法，其包含：在一基板上構成一介電層；在該介電層上構成複數個金屬化層，該金屬化層的至少一最底層包括複數個金屬節段，其中每一個該金屬節段係構成於該金屬化層之最底層的頂部表面與底部表面之間，並且該金屬節段係由該最底層中的介電材料所分隔；將複數個IC晶粒設置在該複數個金屬化層之最頂金屬化層的頂部表面上；移除該基板；在該介電層處構成一或更多開口以供接觸於該複數個金屬化層之最底層中的複數個金屬節段之至少一些金屬節段，其中具有該一或更多開口的介電層和該複數個金屬化層構成該無基板插入物；以及將該無基板插入物設置在一封裝基板上以構成該SSIT產物。
  12. 如申請專利範圍第11項所述之方法，其中移除該基板的動作包含： 利用機械研磨製程以薄化該基板；以及利用蝕刻製程以移除薄化後的該基板。
  13. 如申請專利範圍第11項所述之方法，其中該複數個IC晶粒包括異質性IC晶粒。
  14. 如申請專利範圍第11項所述之方法，其中該複數個IC晶粒包括同質性IC晶粒。
  15. 如申請專利範圍第11項所述之方法，進一步包含利用C4凸塊將該無基板插入物固定於該封裝基板上以構成該SSIT產物。
  16. 如申請專利範圍第11項所述之方法，進一步包含在該介電層處構成該一或更多開口之後，在該介電層上構成一鈍化層，其中該鈍化層包括一或更多開口，其在空間上係對應於該介電層處的一或更多開口，並且其中該無基板插入物進一步包括該鈍化層。
  17. 如申請專利範圍第16項所述之方法，進一步包含在該一或更多金屬化層的最底層上構成一凸塊下金屬(UBM)層，其中該凸塊下金屬層接觸於該最底層中之該複數個金屬節段的至少一些金屬節段，並且其中該無基板插入物進一步包括該UBM層。
  18. 如申請專利範圍第11項所述之方法，其中在該一或更多金屬化層之最底層裡複數個金屬節段之不同群組係對應於複數個IC晶粒的個別者。
  19. 如申請專利範圍第18項所述之方法，其中該複數個金屬節段的不同群組具有不同的個別節段密度。
  20. 如申請專利範圍第11項所述之方法，其中每一個該複數個金屬化層包括複數個金屬節段，並且在該金屬化層之其中一者的多個金屬節段為不 同於在該金屬化層之另一者中的多個金屬節段。
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