TW201436216A - 在鰭式場效電晶體(FinFET)製程中之多閘極變容器及互補變容器 - Google Patents

在鰭式場效電晶體(FinFET)製程中之多閘極變容器及互補變容器 Download PDF

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TW201436216A
TW201436216A TW102134318A TW102134318A TW201436216A TW 201436216 A TW201436216 A TW 201436216A TW 102134318 A TW102134318 A TW 102134318A TW 102134318 A TW102134318 A TW 102134318A TW 201436216 A TW201436216 A TW 201436216A
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varactor
finfet
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semiconductor fin
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Chi-Hsien Lin
Ying-Ta Lu
Hsien-Yuan Liao
Hoh-Siang Chen
Chewn-Pu Jou
Fu-Lung Hsueh
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Taiwan Semiconductor Mfg
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract

本發明提供一種變容器,該變容器包括至少一個半導體鰭部、第一閘極,及第二閘極,該第二閘極與第一閘極實體地斷開。第一閘極及第二閘極分別與至少一個半導體鰭部形成第一鰭式場效電晶體(Fin Field-Effect Transistor;FinFET)及第二FinFET。第一FinFET及第二FinFET之源極區域及汲極區域經互連以形成變容器。

Description

在鰭式場效電晶體(FinFET)製程中之多閘極變容器及互補變 容器
本發明係有關於一種變容器,其基於鰭式場效電晶體(Fin Field-Effect Transistor;FinFET)結構形成
變容器通常係用於要求電容器具有可變電容值的各種應用中。變容器為全體電容值隨施加於電容器上之電壓而變的電容器。例如,在壓控振盪器(Voltage Controlled Oscillators;VCO)中,廣泛地使用變容器。
變容器通常係使用金屬氧化物半導體(Metal-Oxide-Semiconductor;MOS)裝置形成。在一般變容器中,將MOS裝置之閘極用作變容器之一電容器極板,且將MOS裝置之源極與汲極互連以形成變容器之另一電容器極板。閘極介電質充當電容器絕緣體。在VCO中,通常需要低靈敏度及低KVCO(VCO之增益),其中靈敏度為電容變化與施加於閘極上之偏壓變化的比率。
在一實施方式中,揭露一種變容器,其包含:至少一個半導體鰭部;一第一閘極;以及一第二閘極,該第二閘極與該第一閘極實體地斷開,其中該第一閘極及該第二閘極分別與該至少一個半導體鰭部形成一第一FinFET及一第二FinFET,且其中該第一FinFET及該第二FinFET之源極及汲極區域經互連以形成該變容器。
在一實施方式中,揭露另一種變容器,包含一第一半導體鰭部、一第一閘極介電質、一第一閘極、一第二閘極以及一源極區域及一汲極區域。其中,該一第一閘極介電質包含:一第一側壁部分,該第一側壁部分在該第一半導體鰭部之一第一側壁上;以及一第二側壁部分,該第二側壁部分在該第一半導體鰭部之一第二側壁上。該第一閘極與該第一閘極介電質之該第一側壁部分接觸,其中該第一閘極、該第一閘極介電質之該第一側壁部分,及該第一半導體鰭部之該第一側壁形成一第一變容器部分。該第二閘極與該第一閘極介電質之該第二側壁部分接觸,其中該第二閘極與該第一閘極實體地斷開,且其中該第二閘極、該第一閘極介電質之該第二側壁部分,及該第一半導體鰭部之該第二側壁形成一第二變容器部分。以及,該源極區域及該汲極區域位於該第一閘極介電質之相對端上,其中該源極區域及該汲極區域經互連以形成該第一變容器及該第二變容器。
在一實施方式中,揭露另一種變容器,包含:一第 一FinFET以及一第二FinFET,該第二FinFET連接至該第一FinFET以形成該變容器。其中,該第一FinFET包含:複數個半導體鰭部;一第一閘極,該第一閘極在該複數個半導體鰭部之上方;以及一第一源極及一第一汲極,該第一源極及該第一汲極包含該複數個半導體鰭部之端部,其中該第一源極經電氣連接至該第一汲極。該第二FinFET包含:至少一個半導體鰭部;一第二閘極,該第二閘極在該至少一個半導體鰭部之上方;以及一第二源極及一第二汲極,該第二源極及該第二汲極包含該至少一個半導體鰭部之端部,其中該第二源極經電氣連接至該第二汲極,且其中在該第一FinFET中之鰭部的一第一總數目係大於在該第二FinFET中之鰭部的一第二總數目。
20‧‧‧變容器
20A‧‧‧第一FinFET
20B‧‧‧第二FinFET
22‧‧‧鰭部
22A‧‧‧鰭部
22B‧‧‧鰭部
22C‧‧‧鰭部
23‧‧‧長條形半導體
24‧‧‧閘極介電質
24A‧‧‧部分
24B‧‧‧部分
24C‧‧‧部分
25‧‧‧淺溝槽絕緣區域
26‧‧‧源極及汲極區域
30‧‧‧電容器
600‧‧‧變容器
600A‧‧‧變容器
600B‧‧‧變容器
700‧‧‧變容器
700A‧‧‧變容器
700B‧‧‧變容器
800‧‧‧變容器
800A‧‧‧變容器
800B‧‧‧變容器
800C‧‧‧變容器
900‧‧‧變容器
900A‧‧‧變容器
900B‧‧‧變容器
900C‧‧‧變容器
900D‧‧‧變容器
32‧‧‧電容電壓(C-V)曲線
34‧‧‧線條
36A‧‧‧線條
36B‧‧‧線條
36C‧‧‧線條
36D‧‧‧線條
100‧‧‧變容器
100A‧‧‧變容器
100B‧‧‧變容器
200‧‧‧變容器
200A‧‧‧變容器
200B‧‧‧變容器
300‧‧‧變容器
300A‧‧‧變容器
300B‧‧‧變容器
400‧‧‧變容器
400A‧‧‧變容器
400B‧‧‧變容器
500‧‧‧變容器
500A‧‧‧變容器
500B‧‧‧變容器
1000‧‧‧變容器
1000A‧‧‧變容器
1000B‧‧‧變容器
1000C‧‧‧變容器
1100‧‧‧變容器
1100A‧‧‧變容器
1100B‧‧‧變容器
1100C‧‧‧變容器
1200‧‧‧變容器
1200A‧‧‧變容器
1200B‧‧‧變容器
1200C‧‧‧變容器
1200D‧‧‧變容器
1300‧‧‧變容器
1300A‧‧‧變容器
1300B‧‧‧變容器
1300C‧‧‧變容器
G1‧‧‧閘極
G2‧‧‧閘極
G2A‧‧‧閘極
G2B‧‧‧閘極
為了更加完全地理解此些實施例,及此些實施例之優點,現結合附圖對以下描述進行參考,在此些附圖中:第1A圖、第1B圖、第1C圖及第1D圖圖示根據一些實施例之變容器之透視圖及符號;第1E圖圖示根據例示性實施例之變容器之C-V曲線,在該圖中將此C-V曲線與習知變容器之C-V曲線進行比較;第2A圖及第2B圖分別圖示根據一些實施例之變容器之透視圖及俯視圖,其中該變容器包括兩個變容器,並且該兩個變容器之閘極區域及源極/汲極區域為交叉連接; 第3A圖及第3B圖分別圖示根據一些實施例之變容器之透視圖及俯視圖,其中該變容器包括兩個並聯的變容器;第4A圖及第4B圖分別圖示根據一些實施例之變容器之透視圖及俯視圖,其中該變容器包括兩個並聯的變容器,並且兩個變容器中之每一者之源極區域及汲極區域的導電型彼此相反;第5圖圖示根據一些實施例之複數個變容器之C-V曲線;第6圖圖示作為偏壓之函數的複數個變容器之電容的斜率;及第7圖至第16圖圖示根據一些例示性實施例之變容器的透視圖。
在下文詳細論述本案之實施例之製造及使用。然而,應瞭解,此些實施例提供可體現於各種特定情境中之許多可用之概念。論述之特定實施例為說明性的,且不限制本案之範疇。
根據各種例示性實施例提供變容器及形成此變容器之方法。本文論述了實施例之變化及操作。在各種視圖及說明性實施例中,相同元件符號用於指定相同元件。
第1A圖係圖示例示性的變容器20之透視圖。根據一些實施例,變容器20係基於鰭式場效電晶體(Fin Field-Effect Transistor;FinFET)結構形成,此結構包括半導體鰭部22。鰭部22可為長條形半導體23之頂部,該長條形半導體23在相對淺溝槽絕緣(Shallow Trench Isolation;STI)區域 25之間。此外,半導體鰭部22係在STI區域25之頂表面上方。閘極介電質24包括部分24A及部分24B,此部分24A及此部分24B在鰭部22之相對側壁上。閘極介電質24亦可在鰭部22之頂表面上包括部分24C。與閘極介電質24重疊之鰭部22的一部分形成FinFET之通道。源極及汲極區域26係形成於通道之相對側上,其中源極及汲極區域26中之一者為源極區域,且源極及汲極區域26中之另一者為汲極區域。在整個描述中,使用符號「S/D」(如第1A圖中所示)來指示各個連接區域包括源極區域及汲極區域。
變容器20包括閘極G1及閘極G2。閘極G1及閘極G2彼此實體地分離,且閘極G1及閘極G2彼此電氣斷開。因此,可同時將不同電壓施加於閘極G1及閘極G2上。根據一些實施例,閘極G1及閘極G2係藉由形成連續閘極,且直接蝕刻掉在閘極介電質24之上方的連續閘極之一部分來形成。閘極G1及閘極G2之側壁分別接觸閘極介電質部分24A及閘極介電質部分24B。閘極G1與鰭部22一起形成第一FinFET 20A,其中閘極介電質24之側壁部分24A充當第一FinFET 20A之閘極介電質,且源極及汲極區域26充當第一FinFET 20A之源極及汲極區域。閘極G2與鰭部22一起形成第二FinFET 20B,其中閘極介電質24之側壁部分24B充當第二FinFET 20B之閘極介電質,且源極及汲極區域26亦充當第二FinFET 20B之源極及汲極區域。在一些實施例中,閘極G1及閘極G2不包括與閘極介電質部分24C重疊之部分,且因此第一FinFET20A及第二FinFET 20B係由閘極介電質24之側壁部分形成, 而非由頂部24C形成。在替代實施例中,閘極G1及閘極G2中之一者或兩者延伸重疊閘極介電質部分24C,且因此第一FinFET 20A及第二FinFET 20B除由側壁部分形成之外,亦由閘極介電質24之頂部24C一起形成。
源極及汲極區域26係例如經由上覆金屬層中之接觸插塞及金屬線互連。各個節點亦可表示為「S/D」。因此,FinFET 20A形成第一變容器,且FinFET 20B形成第二變容器。第一變容器及第二變容器係並聯地連接以形成變容器20。
第1B圖圖示變容器20之等效電路圖,其中將第一FinFET 20A及第二FinFET 20B圖示為並聯連接。電容器30為在閘極G1與閘極G2之間的寄生電容器。在第1C圖中,FinFET 20A及FinFET 20B係由變容器20A及變容器20B之符號表示。在第1D圖,圖示了變容器20之符號,此變容器20為三端變容器,其中閘極G1及閘極G2及源極S/汲極D充當三端。
第1E圖圖示變容器20(第1A圖)之電容電壓(Capacitor-Voltage;C-V)曲線32,其中變容器20之電容經圖示為閘極電壓Vctrl之函數,該閘極電壓Vctrl為施加於閘極G1上之電壓。圖示了複數個線條32,其中此些線條32中之每一者係藉由施加電壓於閘極G2上獲得。可以看出,當將不同電壓施加於閘極G2上時,所得的C-V曲線32亦彼此不同,且閘極G2上之電壓愈高,變容器20將具有之電容愈大。第1E圖亦圖示線條34,該線條34係自包含單個閘極之習知二端變容器獲得,在該單個閘極上施加電壓Vctrl。藉由比較線條32 與線條34,可以看出線條34更加陡峭,指示線條32之電容靈敏度較低,其中電容靈敏度為電容變化與閘極電壓變化之比率。因此,本案之實施例具有比習知變容器較小之電容靈敏度。
第2A圖及第2B圖分別圖示根據一些實施例之變容器100之透視圖及俯視圖。變容器100亦包括閘極G1及閘極G2。此外,變容器100包括鰭部22(包括鰭部22A、鰭部22B及鰭部22C)。鰭部22A及22B與閘極G1及閘極介電質124A及124B一起形成FinFET 100A,且鰭部22C與閘極G2及閘極介電質124C一起形成FinFET 100B。FinFET 100A之源極S1與汲極D1互連,以便FinFET 100A形成變容器,該變容器亦可表示為100A。FinFET 100B之源極S2與汲極D2互連,以便FinFET 100B形成變容器,該變容器亦可表示為100B。此外,閘極G1連接至源極S2及汲極區域D2以形成變容器100之一電容器極板VAR_G,且閘極G2連接至源極S1及汲極區域D1以形成變容器100之另一電容器極板VAR_S/D。
源極及汲極區域S1、S2、D1,及D2可為諸如p型或n型之相同導電型。變容器100A及變容器100B中之每一者可包括任何整數數目之鰭部。在一些實施例中,變容器100A及變容器100B包括不同數目之鰭部,如第2A圖及第2B圖中所示。在替代實施例中,變容器100A及變容器100B包括相同數目之鰭部,其中鰭部數目可為1個、2個、3個、4個或更多個。
第3A圖及第3B圖分別圖示變容器200之透視圖及 俯視圖。變容器200亦包括閘極G1及閘極G2。此外,變容器200包括鰭部22(包括鰭部22A、鰭部22B及鰭部22C)。鰭部22A及22B與閘極G1及閘極介電質124A及124B一起形成FinFET 200A,且鰭部22C與閘極G2及閘極介電質124C一起形成FinFET 200B。FinFET 200A之源極S1與汲極D1互連,以便FinFET 200A形成變容器,該變容器亦可表示為200A。FinFET 200B之源極S2與汲極D2互連,以便FinFET 200B形成變容器,該變容器亦可表示為200B。此外,閘極G1及閘極G2經互連以形成變容器200之一電容器極板VAR_G,且源極S1及汲極D1經連接至源極S2及汲極D2以形成變容器200之另一電容器極板VAR_S/D。
在一些實施例中,源極及汲極區域S1、S2、D1,及D2具有可為p型或n型之相同導電型。在替代實施例中,源極S1及汲極D1可具有與源極S2及汲極D2之導電型相反的導電型。例如,源極S1及汲極D1可為p型,而源極S2及汲極D2可為n型。或者,源極S1及汲極D1為n型,而源極S2及汲極D2為p型。變容器100A及變容器100B中之每一者可包括任何整數數目之鰭部。在一些實施例中,變容器100A及變容器100B包括不同數目之鰭部,如第3A圖及第3B圖中所示。在替代實施例中,變容器100A及變容器100B包括相同數目之鰭部,其中此數目可為1個、2個、3個、4個或更多個。
第4A圖及第4B圖分別圖示變容器300之透視圖及俯視圖。變容器300包括閘極G1及閘極G2,該閘極G1及閘 極G2經互連以充當電容器極板VAR_G。源極S1及汲極D1經連接至源極S2及汲極D2以形成變容器300之另一電容器極板VAR_S/D。此些實施例類似於第2A圖及第2B圖中之實施例,區別為源極區域S1及S2具有相同導電型,且該相同導電型與汲極區域D1及D2之導電型相反。例如,源極區域S1及S2可為p型,且汲極區域D1及D2可為n型。或者,源極區域S1及S2可為n型,且汲極區域D1及D2可為p型。
根據一些實施例,如例示性第2A圖、第2B圖、第3A圖、第3B圖、第4A圖及第4B圖中所示,第一變容器(100A/200A/300A)之大小不同於第二變容器(100B/200B/300B)之大小。此舉可例如藉由使第一變容器(100A/200A/300A)中之鰭部數目與第二變容器(100B/200B/300B)中之鰭部數目不同來達成。由於兩個變容器中之鰭部數目彼此不同,各個變容器之電容靈敏度可以降低。此外,藉由調整兩個變容器中之鰭部數目的比率,可將各個變容器之電容靈敏度調整至所需值。第5圖圖示一些例示性變容器之C-V曲線,其中變容器20之電容經圖示為偏壓之函數,該偏壓為施加於兩個變容器之兩個互連閘極上之電壓。可自變容器獲得此些結果,此些變容器具有類似於第3A圖及第3B圖中所示之變容器的結構,其中線條36A、線條36B、線條36C及線條36D中之每一者係自變容器產生。用於產生線條36A、線條36B、線條36C及線條36D中之每一者的變容器100B/200B/300B及變容器100A/200A/300A分別包括n型FinFET及p型FinFET。線條36A、線條36B、線條36C及線條36D係自具有不同鰭部數目 比率(Fin Number Ratio;FNR)之變容器獲得。FNR表示各個變容器100B/200B/300B中之鰭部數目與各個變容器100A/200A/300A中之鰭部數目的比率(第3A圖及第3B圖)。在C-V曲線圖示為線條36A、線條36B、線條36C及線條36D之每一變容器中,變容器100B/200B/300B及變容器100A/200A/300A之總鰭部數目等於24。線條36A係當FNR為(1:0)時獲得,且因此變容器100B/200B/300B包括24個鰭部,且變容器100A/200A/300A不包括鰭部,如此意謂無變容器並聯連接至變容器100B/200B/300B。線條36B、線條36C及線條36D係分別當將FNR調整至(2:1)、(1:1)及(1:2)時獲得。可以看出,隨著FNR改變,電容值降低,且電容靈敏度亦降低,如自較小陡峭之線條36B、線條36C及線條36D清楚地觀察到。此外,藉由將線條36B、線條36C及線條36D之電容值與線條36A之電容值比較,可以看出,變容器之實際電容與FNR成比例。
第6圖圖示作為偏壓之函數的電容斜率(由第5圖計算),其中該斜率為電容靈敏度。將該斜率計算為電容變化與偏壓變化之比率。該圖清楚地表明,隨著FNR降低(其中線條36A具有最高FNR,且線條36D具有最低FNR),電容靈敏度亦降低。
在上文論述中,儘管將等於或小於1之FNR作為實例,但是當FNR等於或大於1時,可獲得相同結果,其中藉由擴大兩個互連的變容器中之鰭部數目之間的差異,所得變容器之電容靈敏度可降低,而與互連變容器中之何者具有更 多鰭部無關。
第7圖至第16圖圖示根據本案之實施例之變容器的變化。應注意,在第7圖至第16圖中之每一圖中,複數個FinFET之導電型可彼此相同,或複數個FinFET之導電型可彼此相反。在本文中未詳細論述在第7圖至第15圖中之諸如閘極介電質(在閘極與各個鰭部之間)的各種組件,而將此些組件圖示。
第7圖圖示單指部二鰭部變容器400。變容器400包括對準於直線之閘極G1及閘極G2,因此形成指部。鰭部22A及22B彼此平行,且鰭部22A及22B分別與閘極G1及G2形成變容器400A及400B。變容器400之源極及汲極區域S/D互連,而閘極G1及G2彼此斷開。在此些實施例中,閘極G1不與鰭部22B形成任何FinFET及任何變容器,且閘極G2不與鰭部22A形成任何FinFET及任何變容器。
第8圖圖示圖示單指部二鰭部變容器500,該變容器類似於第7圖中之變容器400。在此些實施例中,鰭部22A及22B彼此平行,且鰭部22A及22B分別與閘極G1及G2形成變容器500A及500B。此外,閘極G1延伸以接觸閘極介電質24之側壁部分,且因此閘極G1亦與鰭部22B一起形成FinFET(此FinFET亦為變容器)。剩餘部分與第7圖實質上相同。
第9圖圖示變容器600,該變容器為單指部三鰭部變容器,該變容器包括對準於直線之閘極G1及G2,因此形成一指部。鰭部22A及22B彼此平行,且鰭部22A及22B與閘 極G1一起形成變容器600A。閘極G2與閘極介電質24之側壁部分一起形成變容器600B。將變容器600之源極及汲極區域互連,而將閘極G1及G2彼此實體斷開,且閘極G1及G2可以彼此電氣斷開,亦可以不彼此電氣斷開。在此些實施例中,閘極G1與鰭部22C一起形成FinFET(此FinFET亦為變容器),且閘極G2不與鰭部22A及22B一起形成任何FinFET及任何變容器。
第10圖圖示單指部三鰭部變容器700,該變容器包括對準於直線之閘極G1及G2,因此形成一指部。鰭部22A及22B彼此平行,且鰭部22A及22B與閘極G1一起形成變容器700A。鰭部22C與閘極G2一起形成變容器700B。變容器700之源極及汲極區域互連,而閘極G1及G2彼此實體地且電氣地斷開。在此些實施例中,閘極G1不與鰭部22C形成任何FinFET及任何變容器,且閘極G2不與鰭部22A及22B形成任何FinFET及任何變容器。
第11圖圖示二指部二鰭部變容器800,該變容器包括互連之變容器800A、800B及800C。變容器800包括對準於直線之閘極G1及閘極G2A,因此形成一指部。閘極G2B形成另一指部,該指部不對準於閘極G1及G2A所對準至之相同直線。閘極G2A及G2B經互連以形成各個變容器800之閘極G2。閘極G1、閘極G2A及閘極G2B可彼此平行。鰭部22A及22B彼此平行,且鰭部22A及22B與閘極G2B一起形成變容器800C。鰭部22A與閘極G1一起進一步形成變容器800A。鰭部22B與閘極G2A一起進一步形成變容器800B。變容器 800A、變容器800B及變容器800C之源極及汲極區域經互連為節點S/D,而閘極G1及G2彼此斷開。
第12圖圖示二指部二鰭部變容器900,該變容器包括互連之變容器900A、900B及900C及900D。第12圖類似於第11圖,區別為閘極G1及G2中之每一者包括兩個實體分離且電氣互連之閘極,此些閘極與鰭部22A及22B一起形成變容器。
第13圖亦圖示二指部二鰭部變容器1000,該變容器包括互連之變容器1000A、1000B及1000C。變容器1000類似於第11圖中之變容器,區別為閘極G1延伸至閘極介電質24之側壁以形成另一變容器。此外,閘極G1亦與側壁及鰭部22A之頂表面形成FinFET(此FinFET亦為變容器)。閘極G2與閘極介電質24之側壁部分形成變容器。
第14圖圖示三閘極變容器1100,該變容器包括互連之變容器1100A、1100B及1100C。變容器1100亦為二指部二鰭部變容器。根據一些實施例,閘極G1及G2形成一指部。閘極G3形成另一指部。閘極G1、閘極G2及閘極G3彼此實體地且電氣地斷開,以便可將不同電壓同時施加於閘極G1、閘極G2及閘極G3上。因此,各個變容器1100為四端變容器。
第15圖圖示四閘極變容器1200,該變容器包括互連之變容器1200A、1200B、1200C及1200D。此些實施例類似於第14圖中之實施例,區別為變容器1200之閘極G1包括在兩個指部中之部分。變容器1200A、1200B、1200C及1200D之 閘極彼此實體地斷開。變容器1200A及1200C之閘極經互連以形成閘極G1。變容器1200B之閘極G2及變容器1200D之閘極G3與閘極G1電氣斷開,且變容器1200B之閘極G2及變容器1200D之閘極G3彼此電氣斷開。
第16圖圖示三閘極變容器1300,該變容器包括互連之變容器1300A、1300B及1300C,該互連之變容器1300A、1300B及1300C分別包括閘極G1、G2及G3。此些實施例類似於第14圖中之實施例,區別為變容器1300之閘極G1延伸至閘極介電質24之側壁以形成另一變容器。
根據本案之實施例,藉由形成包括多個閘極及/或多個鰭部之變容器,變容器之電容靈敏度可降低。此外,可達成較佳品質因數(Q factor)。本案之實施例符合FinFET形成製程,且不需要額外製程步驟。
根據一些實施例,變容器包括至少一個半導體鰭部、第一閘極,及第二閘極,該第二閘極與第一閘極實體地斷開。第一閘極及第二閘極分別與至少一個半導體鰭部形成第一FinFET及第二FinFET。第一FinFET及第二FinFET之源極及汲極區域經互連以形成變容器。
根據其他實施例,變容器包括第一半導體鰭部,及閘極介電質,該閘極介電質包括在第一半導體鰭部之第一側壁上的第一側壁部分,及在第一半導體鰭部之第二側壁上的第二側壁部分。變容器進一步包括第一閘極及第二閘極,該第一閘極與閘極介電質之第一側壁部分接觸,且該第二閘極 與閘極介電質之第二側壁部分接觸。第一閘極、閘極介電質之第一側壁部分,及第一半導體鰭部之第一側壁形成第一變容器部分。第二閘極與第一閘極實體地斷開。第二閘極、閘極介電質之第二側壁部分,及第一半導體鰭部之第二側壁形成第二變容器部分。源極及汲極區域係位於閘極介電質之相對端上,其中源極及汲極區域經互連以形成第一變容器及第二變容器。
根據另外實施例,變容器包括第一FinFET及連接至該第一FinFET之第二FinFET以形成變容器。第一FinFET包括複數個半導體鰭部、在此些半導體鰭部之上方的第一閘極,及包含此些半導體鰭部之端部的第一源極及第一汲極。第一源極經電氣連接至第一汲極。第二FinFET包括至少一個半導體鰭部、在至少一個半導體鰭部之上方的第二閘極,及包含此至少一個半導體鰭部之端部的第二源極及第二汲極。第二源極經電氣連接至第二汲極。第一FinFET中之鰭部的總數目大於第二FinFET中之鰭部的總數目。
儘管已詳細描述了實施例及此些實施例之優點,但是應理解,在不背離由所附申請專利範圍所定義之實施例之精神及範疇的情況下,可在本文中進行各種改變、替換及變更。此外,本案之範疇並不意欲限於本說明書中描述之製程、機器、製造,及物質組成、手段、方法及步驟之特定實施例。如本領域一般技藝者將自本案容易地瞭解,根據本案可利用目前存在或有待以後開發、可執行與本文所述之相應實施例大體上相同的功能或達成與本文所述之相應實施例大體上相 同的結果之製程、機器、製造、物質組成、手段、方法,或步驟。因此,隨附申請專利範圍意欲在此隨附申請專利範圍之範疇內包括此些製程、機器、製造、物質組成、手段、方法,或步驟。此外,每一請求項構成單獨的實施例,且各種請求項及實施例之組合在本案之範疇之內。
20‧‧‧變容器
20A‧‧‧第一FinFET
20B‧‧‧第二FinFET
22‧‧‧鰭部
23‧‧‧長條形半導體
24‧‧‧閘極介電質
24A,24B,24C‧‧‧部分
25‧‧‧淺溝槽絕緣區域
26‧‧‧源極及汲極區域

Claims (10)

  1. 一種變容器,包含:至少一個半導體鰭部;一第一閘極;以及一第二閘極,該第二閘極與該第一閘極實體地斷開,其中該第一閘極及該第二閘極分別與該至少一個半導體鰭部形成一第一FinFET及一第二FinFET,且其中該第一FinFET及該第二FinFET之源極及汲極區域經互連以形成該變容器。
  2. 如請求項1所述之變容器,其中該至少一個半導體鰭部包含一第一半導體鰭部,其中該第一閘極與該第一半導體鰭部之一第一側壁部分形成該第一FinFET,且其中該第二閘極與該第一半導體鰭部之一第二側壁部分形成該第二FinFET。
  3. 如請求項2所述之變容器,其中該第一閘極及該第二閘極彼此電氣去耦。
  4. 如請求項1所述之變容器,其中該第一FinFET包含彼此平行之一第一數目之鰭部,且該第二FinFET包含一第二數目之鰭部,且其中鰭部之該第一數目大於鰭部之該第二數目。
  5. 如請求項1所述之變容器,其中該第一閘極經連接至該第二FinFET之一第二源極及一第二汲極,且其中該第二閘極經 連接至該第一FinFET之一第一源極及一第一汲極。
  6. 一種變容器,包含:一第一半導體鰭部;一第一閘極介電質,包含:一第一側壁部分,該第一側壁部分在該第一半導體鰭部之一第一側壁上;以及一第二側壁部分,該第二側壁部分在該第一半導體鰭部之一第二側壁上;一第一閘極,該第一閘極與該第一閘極介電質之該第一側壁部分接觸,其中該第一閘極、該第一閘極介電質之該第一側壁部分,及該第一半導體鰭部之該第一側壁形成一第一變容器部分;一第二閘極,該第二閘極與該第一閘極介電質之該第二側壁部分接觸,其中該第二閘極與該第一閘極實體地斷開,且其中該第二閘極、該第一閘極介電質之該第二側壁部分,及該第一半導體鰭部之該第二側壁形成一第二變容器部分;以及一源極區域及一汲極區域,該源極區域及該汲極區域位於該第一閘極介電質之相對端上,其中該源極區域及該汲極區域經互連以形成該第一變容器及該第二變容器。
  7. 如請求項6所述之變容器,進一步包含: 一第二半導體鰭部,該第二半導體鰭部平行於該第一半導體鰭部;以及一第二閘極介電質,該第二閘極介電質在該第二半導體鰭部之側壁及一頂表面上,其中該第一閘極進一步延伸於該第二閘極介電質之上方。
  8. 如請求項6所述之變容器,進一步包含:一第二閘極介電質,該第二閘極介電質在該第一半導體鰭部之側壁及一頂表面上,以及一第三閘極,該第三閘極在該第二閘極介電質之上方。
  9. 如請求項8所述之變容器,其中該第一閘極經電氣連接至該第三閘極,且該第一閘極與該第二閘極電氣斷開。
  10. 如請求項8所述之變容器,其中該第一閘極與該第二閘極及該第三閘極電氣斷開。
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