TW201401593A - Hall element - Google Patents

Abstract

Provided is a Hall element having little variation in characteristics of a generated Hall voltage. The Hall element includes an n-type well (6) square in plan and provided on a p-type substrate (7), an insulating film (5) provided on the n-type well (6) except for the four corners of the Hall element (10), an n-type polysilicon film (8) provided on the insulating film (5), and n-type diffusion layers (1 to 4) provided on the n-type well (6) at the four corners of the Hall element (10). Since a depletion layer is produced at an upper part of the n-type well (6) under the insulating layer (5), Hall current flows under the depletion layer. Therefore, the Hall current is neither affected by stains, dust, or scratches that may exist on the surface of the semiconductor substrate, nor affected by the interface between an oxide film and the semiconductor.

Description

Hall element

The present invention is directed to a Hall element.

A conventional Hall element will be described using FIG. 6(A) is a plan view of a conventional Hall element, and FIG. 6(B) is a YY cross-sectional view in a plan view of a conventional Hall element, and FIG. (C) is a ZZ cross-section in a plan view of a conventional Hall element. Figure.

In the Hall element 30, a power supply voltage is applied between the N-type diffusion layer 32 and the N-type diffusion layer 33, so that a current flows from the N-type diffusion layer 32 to the N-type diffusion layer 33. At this time, when a magnetic field in a direction different from the direction of the current flowing through the Hall element 30 is applied, the Hall current flows vertically to generate a Hall voltage for both the current and the magnetic field. In other words, a Hall voltage occurs between the N-type diffusion layer 31 and the N-type diffusion layer 34 (see, for example, Patent Document 1).

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Laid-Open Patent Publication No. 2008-008883 (Fig. 17)

Here, in the prior art, the current path of the Hall element 30 is formed on the surface of the outermost surface of the P-type substrate 37, that is, the N-type well 36. In the manufacturing process of the Hall element 30, dirt, waste, and the like which occur during cleaning adhere to the surface of the N-type well 36. Or there is an interface between damage or ruthenium and ruthenium oxide film. Therefore, the current path of the Hall element 30 is affected by these. In addition, the current path of the Hall element 30 is also affected by the interface level between the N-well 36 and the insulating film thereon. All of these are sources of noise, and the characteristics of the Hall voltage generated by the Hall element 30 are not uniform.

The present invention is directed to providing a Hall element having few variations in characteristics.

In order to solve the above problems, the present invention provides a Hall element including: a first conductivity type substrate; a second conductivity type well provided on the substrate; an insulating film provided on a surface of the well; The well is a first conductivity type polysilicon film provided at a lower potential than the well and disposed above the insulating film; a depletion layer occurring in an upper portion of the well below the insulating film; a surface of the conductive well, a first and a fourth diffusion layer of the second conductivity type that are disposed opposite to each other with the polysilicon film interposed therebetween; and a surface of the second conductivity type well adjacent to the surface of the second conductivity type The second and third diffusion layers of the second conductivity type, the straight lines connecting the first and fourth diffusion layers, and the second and third The lines connecting the diffusion layers intersect.

According to the present invention, the current path in the Hall element is not formed on the outermost surface of the first conductive type substrate, that is, the surface of the second conductive type well, and is formed in the second conductive type well which occurs under the insulating film. Below the upper vacant layer. Therefore, the current path of the Hall element is not affected by the cleaning or waste of the manufacturing process of the Hall element, or the defect or the interface level, thereby suppressing the Hall voltage generated by the Hall element. Uneven characteristics.

1~4‧‧‧N type diffusion layer

5‧‧‧Insulation film

6‧‧‧N type well

7‧‧‧P type substrate

8‧‧‧N type polycrystalline silicon film

10‧‧‧ Hall element

21‧‧‧Power supply

22‧‧‧ voltmeter

30‧‧‧ Hall element

31~34‧‧‧N type diffusion layer

36‧‧‧N type well

37‧‧‧P type substrate

VREF‧‧‧ reference voltage

1 is a view showing a Hall element, (A) is a plan view of a Hall element, (B) is a YY cross-sectional view in a plan view of a Hall element, and (C) is a ZZ cross-sectional view in a plan view of a Hall element.

Fig. 2 is a circuit connection diagram illustrating a Hall element.

Fig. 3 is a circuit connection diagram illustrating a Hall element.

4 is an energy band diagram. (A) When the voltage of the N-type polycrystalline germanium film is a ground voltage, and (B) the voltage of the N-type polysilicon film is lower than a reference voltage of the ground voltage.

5 is an energy band diagram. (A) When the voltage of the P-type polysilicon film is a ground voltage, and (B) the voltage of the P-type polysilicon film is lower than a reference voltage of the ground voltage.

6 is a view showing a conventional Hall element, (A) is a plan view of a conventional Hall element, and (B) is in a plan view of a conventional Hall element. YY cross-sectional view, (C) is a ZZ cross-sectional view in a plan view of a conventional Hall element.

Embodiments of the present invention will be described below with reference to the drawings.

First, the configuration of the Hall element will be described. 1 is a view showing a Hall element, (A) is a plan view of a Hall element, (B) is a sectional view taken along line YY of a Hall element, and (C) is a plan view along a Hall element. Sectional view of ZZ.

The P-type substrate 7 is provided with a square N-shaped well 6 in plan view. An insulating film 5 is provided over the N-type well 6 except for the square corners of the Hall element 10. An N-type polysilicon film 8 is provided over the insulating film 5. At the four corners of the Hall element 10, N-type diffusion layers 1 to 4 are provided on the upper portion of the N-type well 6. Here, the N-type diffusion layers 1 to 4 are respectively provided at the edges (four corners) of the N-type well 6 in plan view, the N-type diffusion layer 1 and the N-type diffusion layer 4 are opposed to each other, and the N-type diffusion layer 2 and the N-type are formed. The diffusion layer 3 is opposed to each other. A straight line connecting the N-type diffusion layer 1 and the N-type diffusion layer 4 intersects with a straight line connecting the N-type diffusion layer 2 and the N-type diffusion layer 3. Among them, the N-type well 6 is thinner than the N-type diffusion layers 1 to 4, and has a deep diffusion layer of impurity distribution.

Next, the operation of the Hall element 10 will be described. Fig. 2 is a view showing a circuit connection of a Hall element. Fig. 3 is a view illustrating a circuit connection of a Hall element. Figure 4 is a band diagram. (A) The voltage of the N-type polysilicon film is the ground voltage, and the voltage of the (B) N-type polysilicon film is lower than the ground voltage. The reference voltage is the time.

As shown in FIG. 3, the positive electrode terminal of the power source 21 is connected to the N-type diffusion layer 2, and the negative electrode terminal of the power source 21 is connected to the N-type diffusion layer 3. A voltage lower than a voltage applied to the N-type diffusion layer 2 can be applied to the N-type polysilicon film 8 system. A voltmeter 22 for metering the Hall voltage is provided between the N-type diffusion layer 1 and the N-type diffusion layer 4.

When there is no voltage difference between the N-type polycrystalline germanium film 8 and the N-type well 6, the energy band acts in a thermal equilibrium state, and the N-type polycrystalline germanium film 8 and the N-type well 6 operate in a manner consistent with the Fermi level. . Therefore, a heat balance state is generated between the N-type polysilicon film 8 and the N-type well 6, and as shown in FIG. 4(A), a majority carrier, that is, an electron accumulation layer, slightly occurs in the upper portion of the N-type well 6 below the insulating film 5. Therefore, the current flowing between the N-type diffusion layers 2 and 3 flows at the surface at this time.

However, with the circuit shown in FIG. 3, when the reference voltage VREF lower than the ground voltage is applied to the N-type polysilicon film 8, the negative under the insulating film 5 can be controlled by the negative reference voltage VREF. Formation of a depleted layer in the upper portion of the well 6. Specifically, when the reference voltage VREF is lowered, the essential Fermi level is close to the Fermi level, and as shown in FIG. 4(B), a depletion layer can be formed on the surface of the N-type well 6. If the voltage is lowered (the absolute value is increased on the negative side), the depletion layer is changed wide. In this state, on the surface of the N-type well 6, the current is strong, that is, the electron system is hardly depleted, so that the current flowing between the N-type diffusion layers 2 and 3 is more than the depletion layer near the surface. For the lower part, the deeper part, that is, the inside of the N-type well 6 flows. Therefore, the Hall current presented in the presence of a magnetic field is also in the N-well 6 Internally, a Hall voltage occurs between the N-type diffusion layer 1 and the N-type diffusion layer 4. The Hall voltage is measured by a voltmeter 22. In the inside of the N-type well 6, there is no contamination, waste, or damage existing on the surface of the semiconductor substrate, and there is no possibility of being affected by the interface. By operating in the state as described above, the noise which affects the Hall current which determines the characteristics of the Hall element is reduced, and the unevenness can be reduced.

In addition, an operational amplifier, a comparator, and a reference voltage generating circuit may be provided instead of the voltmeter 22. At this time, the operational amplifier amplifies the Hall voltage. The reference voltage generating circuit generates a reference voltage. The comparator compares the amplified Hall voltage with the reference voltage. If the amplified Hall voltage is higher than the reference voltage, the output logic of the comparator becomes a high level, and if it is low, it becomes a low level.

Further, a P-type polysilicon film may be used instead of the N-type polysilicon film 8. The energy band diagram when the P-type polycrystalline germanium film is used is shown in Fig. 5. In the P-type polycrystalline germanium film and the N-type polycrystalline germanium film 8, since the Fermi level is different, the energy band diagram is also different, as shown in Fig. 5(A), the Fermi scale of the P-type polycrystalline germanium film and the N-type polycrystalline germanium film 8 In the state of thermal equilibrium in which the phases are consistent, the surface near-lanthanum of the N-type well is formed into a substantially depleted state. Therefore, when operating as a Hall element as it is, the Hall current flows inside the N-type well below the depletion layer. Therefore, there is no possibility of being affected by the contamination, waste, damage, or the interface between the oxide film and the semiconductor which are present on the surface of the semiconductor substrate. In the same manner as in the case of using the N-type polysilicon film, the noise which affects the Hall current which determines the characteristics of the Hall element is also reduced, and the unevenness can be reduced.

When the potential of the P-type polysilicon film is made lower than the potential of the N-type well region, the depletion of the N-type well region progresses, and an inversion layer is formed even on the surface. Fig. 5(B) shows this state. At this time, the depletion layer is formed to enter the inside more slightly than the surface. Therefore, the Hall current flows more internally in the lower N-type well region of the depletion layer. As indicated above, the depth of the Hall current flow can be controlled by controlling the potential difference between the P-type polysilicon film and the N-well region.

1~4‧‧‧N type diffusion layer

5‧‧‧Insulation film

6‧‧‧N type well

7‧‧‧P type substrate

8‧‧‧N type polycrystalline silicon film

10‧‧‧ Hall element

Claims (6)

A Hall element comprising: a first conductivity type substrate; a second conductivity type well provided on the substrate; an insulating film provided on a surface of the well; and being applied to the well or the well a lower conductivity, a first conductivity type polysilicon film disposed over the insulating film; a depletion layer occurring in an upper portion of the well below the insulating film; a surface near the second conductivity type well a first and a fourth diffusion layer of a second conductivity type disposed opposite to each other with the polysilicon film; and a second conductivity type disposed opposite to the surface of the second conductivity type with the polysilicon film interposed therebetween In the second and third diffusion layers, a straight line connecting the first and fourth diffusion layers intersects with a straight line connecting the second and third diffusion layers. The Hall element of claim 1, wherein the second conductivity type well is square in plan view. The Hall element according to claim 2, wherein the first to fourth diffusion layers are respectively provided in a square view of the well in a plan view. A Hall element comprising: a first conductivity type substrate; a second conductivity type well provided on the substrate; an insulating film provided on a surface of the well; a lower potential than the well is applied, and a second conductivity type polycrystalline germanium film disposed on the insulating film; a depletion layer that occurs in an upper portion of the well below the insulating film; a second conductivity type first and fourth diffusion layer that is disposed opposite to the surface of the second conductivity type well and that faces the polycrystalline germanium film; And a second line and a third diffusion layer of the second conductivity type that are disposed opposite to each other across the surface of the second conductivity type well, and the first and fourth diffusion layers are connected to each other The straight lines connecting the second and third diffusion layers are intersected. A Hall element according to claim 4, wherein the second conductivity type well is square in plan view. The Hall element according to claim 5, wherein the first to fourth diffusion layers are respectively provided in a square view of the well in a plan view.