WO2018121673A1

WO2018121673A1 - Semi-conductor device

Info

Publication number: WO2018121673A1
Application number: PCT/CN2017/119395
Authority: WO
Inventors: 孙晓峰; 秦仁刚
Original assignee: 无锡华润上华科技有限公司
Priority date: 2016-12-30
Filing date: 2017-12-28
Publication date: 2018-07-05
Also published as: CN108269788B; CN108269788A

Abstract

A semi-conductor device comprising a substrate (10), a polysilicon layer (30) on the substrate (10), a first metal layer (40) and a second metal layer (50), with a metal shielding layer (42) provided between the second metal layer (50) and the polysilicon layer (30). The first metal layer (40) is connected to the polysilicon layer (30) below through a metal plug (31) in a first contact hole; the height of the second metal layer (50) within the semi-conductor device is greater than the height of the metal shielding layer (42) within the semi-conductor device; the metal shielding layer (42) is connected to the substrate (10) below through the metal plug (31) in a second contact hole; and the metal shielding layer (42) is used for shielding an electric field generated by the second metal layer (50) to reduce the influence of the electric field on the polysilicon layer (30).

Description

Semiconductor device

Technical field

The present invention relates to the field of semiconductor fabrication, and more particularly to a semiconductor device.

Background technique

Typical polysilicon has a resistivity of about 300 ohm/sq, while high-resistance polysilicon (Poly HR, HR, High Resistor) has a resistivity of more than 1000 ohm/sq. In the conventional semiconductor device with high-resistance polysilicon structure, when the test and use, the resistance value of the high-resistance polysilicon deviates greatly from the design value, and the resistance value is unstable.

Summary of the invention

Based on this, it is necessary to provide a semiconductor device having high resistance value stability of high-resistance polysilicon.

A semiconductor device comprising a substrate, a polysilicon layer on a substrate, a first metal layer, and a second metal layer, wherein the first metal layer is connected to the underlying polysilicon layer through a metal plug in the first contact hole, A metal shield layer disposed between the second metal layer and the polysilicon layer, the second metal layer having a height in the semiconductor device greater than a height of the metal shield layer in the semiconductor device, The metal shielding layer is connected to the underlying substrate through a metal plug in the second contact hole, the metal shielding layer is configured to shield an electric field generated by the second metal layer to reduce the electric field to the polysilicon layer influences.

In the above semiconductor device, the metal shield layer is provided to shield the electric field generated by the second metal layer, and the stability of the resistance value of the polysilicon layer can be improved. Moreover, since the electric field generated by the second metal layer is shielded, it is not necessary to avoid the wiring of the second metal layer from the polysilicon layer during wiring of the layout, so that the degree of freedom of wiring can be improved.

DRAWINGS

1 is a schematic view of a front view of a semiconductor device in an embodiment;

Figure 2 is a plan view of the semiconductor device shown in Figure 1;

Figure 3 is a left side view of the semiconductor device of Figure 1.

detailed description

In order to facilitate the understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the invention are given in the drawings. However, the invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and comprehensive.

All technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. The terminology used in the description of the present invention is for the purpose of describing particular embodiments and is not intended to limit the invention. The term "and/or" used herein includes any and all combinations of one or more of the associated listed items.

The vocabulary of the semiconductor field used herein is a technical vocabulary commonly used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish the doping concentration, the simple P+ type represents a heavily doped concentration of the P-type, and the P-type represents P type with doping concentration, P-type represents P type with light doping concentration, N+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents light doping concentration N type.

The inventor believes that the resistance value of high-resistance polysilicon deviates greatly from the design value and the resistance value is unstable. The reason is that high-resistance polysilicon is a semiconductor resistor, and its unit resistance value is relatively large, and it is more susceptible to voltage. The influence of external conditions such as temperature. Specifically, the inventors have found that the resistance value of the high-resistance polysilicon is easily affected by the trace and potential of the external metal layer (mainly the metal wiring layer of the device itself), especially the metal wiring layer which is easily exposed to the high-resistance polysilicon. Impact.

1 is a schematic view (and cross-sectional view) of a front view of a semiconductor device including a substrate 10, a polysilicon layer 30 on a substrate 10, a first metal layer 40, a second metal layer 50, and a metal shield layer 42. It should be noted that the structure in the substrate 10 and the structure of the interlayer dielectric (ILD) are omitted in the figure, and only a structure having a large correlation with the inventive point is drawn. The first metal layer 40 is connected to the underlying polysilicon layer 30 through a metal plug 31 in the first contact hole. The metal shielding layer 42 is disposed between the second metal layer 50 and the polysilicon layer 30. The height of the metal shielding layer 42 in the semiconductor device is smaller than the height of the second metal layer 50 in the semiconductor device (ie, the metal shielding layer 42 is in FIG. 1 The coordinates on the Z axis are smaller than the coordinates of the second metal layer 50 on the Z axis in FIG. The metal shield layer 42 is connected to the underlying substrate 10 through a metal plug (not shown in FIG. 1) in the second contact hole. The metal shield layer 42 is shielded between the second metal layer 50 and the polysilicon layer 30, and can shield the electric field generated by the second metal layer 50 to reduce the influence of the electric field on the polysilicon layer 30.

In the above semiconductor device, the metal shield layer 42 is provided to shield the electric field generated by the second metal layer 50, and the stability of the resistance value of the polysilicon layer 30 can be improved. Further, since the electric field generated by the second metal layer 50 is shielded, it is not necessary to avoid the wiring of the second metal layer 50 from the polysilicon layer 30 during wiring of the layout, so that the degree of freedom of wiring can be improved.

Referring to FIG. 1, a semiconductor device includes an active region 110 and an isolation region, a polysilicon layer 30 is located in the isolation region, and the substrate 10 is a silicon substrate. In the embodiment shown in FIG. 1, the isolation region includes a shallow trench isolation (STI) structure 20, and the polysilicon layer 30 is disposed on the surface of the oxide layer of the shallow trench isolation structure 20.

In one embodiment, the polysilicon layer is a high resistance polysilicon (Poly HR). It can be understood that since the high-resistance polysilicon is a semiconductor resistor, the unit resistance value is relatively large, and is more susceptible to external conditions such as voltage and temperature. Therefore, it is necessary to provide a metal shield layer 42 for shielding. For other processes and structures of the polysilicon layer, the metal shield layer 42 can also be provided for electric field shielding. In the embodiment shown in FIG. 1, the polysilicon layer 30 is a high resistance polysilicon disposed on the surface of the shallow trench isolation structure 20 as a resistor.

In one embodiment, the first metal layer 40 and the second metal layer 50 are metal wiring layers. Referring to FIG. 1, the first metal layer 40 is designed to avoid the polysilicon layer 30. Therefore, the metal shield layer 42 is designed to shield the electric field generated by the second metal layer 50. The second metal layer 50 is a trace designed for high voltage (greater than the voltage applied to the first metal layer 40 when the device is in operation), and when the second metal layer 50 passes over the polysilicon layer 30, if there is no metal shield layer 42 By shielding the electric field generated by it, the charge on the high-resistance polysilicon of the polysilicon layer 30 will accumulate, which will result in a low-resistance layer, which will eventually affect the total resistance of the high-resistance polysilicon.

In one embodiment, the first metal layer 40 and the metal shield layer 42 are formed in the same step, such that the number of fabrication processes and lithographic plates may not be increased relative to conventional structures.

Please refer to FIG. 2 and FIG. 3 together, which are respectively a plan view and a left side view of the device shown in FIG. 1 (the structure omitted in FIG. 1 is also omitted). A metal plug 33 in the second contact hole is shown in Figures 2 and 3. In one embodiment, the metal plug 31 in the first contact hole and the metal plug 33 in the second contact hole are formed in the same step, but the metal plug 31 connects the polysilicon layer 30 to the first metal layer 40, the metal Plug 33 pulls metal shield layer 42 to the substrate potential.

Referring to FIG. 2, the orthographic projection of the second metal layer 50 on the surface of the substrate 10 intersects and partially overlaps the orthographic projection of the metal shield layer 42 on the surface of the substrate 10. That is, the second metal layer 50 directly straddles the metal shield layer 42 and the high-resistance polysilicon head, and does not have an excessive influence on the resistance value of the high-resistance polysilicon, so that the degree of freedom of wiring of the second metal layer 50 can be improved. .

Referring to FIG. 2, the polysilicon layer 30 includes polysilicon strips, and the width of the polysilicon strips (the dimension in the X direction in FIG. 2) is smaller than the width of the metal shield layer 42. The orthographic projection of the metal shield layer 42 on the surface of the substrate 10 can completely cover the polysilicon strips in the width direction, so that a better shielding effect can be obtained. The metal shield layer 42 should also cover the polysilicon strip as much as possible in the length direction (Y direction in FIG. 2), but it is necessary to leave a safe distance from the first metal layer 40 to avoid the metal shield layer 42 and the first metal layer. 40 are connected together at the time of manufacture to cause a short circuit.

In the embodiment shown in FIG. 2, the metal shield layer 42 includes a lateral shield section and a longitudinal contact hole lead-out section, and the second contact hole is connected to the contact hole lead-out section.

The technical features of the above-described embodiments may be arbitrarily combined. For the sake of brevity of description, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction between the combinations of these technical features, All should be considered as the scope of this manual.

The above-described embodiments are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the invention. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be determined by the appended claims.

Claims

A semiconductor device comprising a substrate, a polysilicon layer on a substrate, a first metal layer, and a second metal layer, wherein the first metal layer is connected to the underlying polysilicon layer through a metal plug in the first contact hole, A metal shield layer disposed between the second metal layer and the polysilicon layer, the second metal layer having a height in the semiconductor device greater than a height of the metal shield layer in the semiconductor device, The metal shielding layer is connected to the underlying substrate through a metal plug in the second contact hole, the metal shielding layer is configured to shield an electric field generated by the second metal layer to reduce the electric field to the polysilicon layer influences.
The semiconductor device according to claim 1, wherein said polysilicon layer is high resistance polysilicon.
The semiconductor device according to claim 1, wherein the first metal layer and the second metal layer are metal wiring layers.
The semiconductor device according to claim 3, wherein a design working voltage of said second metal layer is greater than a design operating voltage of said first metal layer.
The semiconductor device according to claim 1, wherein said first metal layer and said metal shield layer are formed in the same step.
The semiconductor device according to claim 5, wherein the metal plug in the first contact hole and the metal plug in the second contact hole are formed in the same step.
The semiconductor device of claim 1 wherein an orthographic projection of said second metal layer at said substrate surface intersects and partially overlaps an orthographic projection of said metal shield layer at said substrate surface.
The semiconductor device according to claim 1, wherein said semiconductor device comprises an active region and an isolation region, and said polysilicon layer is located in said isolation region.
The semiconductor device of claim 8, wherein the isolation region comprises a shallow trench isolation structure, the polysilicon layer being disposed on an oxide layer surface of the shallow trench isolation structure.
The semiconductor device according to claim 1, wherein said polysilicon layer comprises a polysilicon strip, a width of said polysilicon strip is smaller than a width of said metal shield layer, and an orthographic projection of said metal shield layer on said substrate surface can The polysilicon strip is completely covered in the width direction.
The semiconductor device according to claim 2, wherein said polysilicon layer functions as a resistor.
The semiconductor device of claim 1, wherein the metal plug in the second contact hole pulls the metal shield layer to a substrate potential by connecting the metal substrate.
The semiconductor device according to claim 1, wherein a distance between the metal shield layer and the first metal layer is separated by a safe distance.
The semiconductor device according to claim 1, wherein said metal shield layer comprises a shield portion in a first direction and a contact hole lead-out portion in a second direction, and a metal plug in said two contact holes is connected to said contact hole Lead the paragraph.
The semiconductor device of claim 14, wherein the first direction is perpendicular to the second direction.