WO2013129103A1

WO2013129103A1 - Hall element

Info

Publication number: WO2013129103A1
Application number: PCT/JP2013/053354
Authority: WO
Inventors: 美香海老原; 嘉胤廣瀬
Original assignee: セイコーインスツル株式会社
Priority date: 2012-03-02
Filing date: 2013-02-13
Publication date: 2013-09-06
Also published as: TW201401593A; JP2013183097A

Abstract

Provided is a Hall element having little variation in characteristics of a generated Hall voltage. The Hall element includes an n-type well (6) square in plan and provided on a p-type substrate (7), an insulating film (5) provided on the n-type well (6) except for the four corners of the Hall element (10), an n-type polysilicon film (8) provided on the insulating film (5), and n-type diffusion layers (1 to 4) provided on the n-type well (6) at the four corners of the Hall element (10). Since a depletion layer is produced at an upper part of the n-type well (6) under the insulating layer (5), Hall current flows under the depletion layer. Therefore, the Hall current is neither affected by stains, dust, or scratches that may exist on the surface of the semiconductor substrate, nor affected by the interface between an oxide film and the semiconductor.

Description

Hall element

The present invention relates to a Hall element.

A conventional Hall element will be described with reference to FIG. 6A is a plan view of a conventional Hall element, FIG. 6B is a YY sectional view of the conventional Hall element, and FIG. 6C is a ZZ in the plan view of the conventional Hall element. It is sectional drawing.

In the Hall element 30, since a power supply voltage is applied between the N-type diffusion layer 32 and the N-type diffusion layer 33, a current flows from the N-type diffusion layer 32 to the N-type diffusion layer 33. At this time, when a magnetic field having a direction different from the direction of the current flowing through the Hall element 30 is applied, a Hall current flows perpendicularly to both the current and the magnetic field to generate a Hall voltage. That is, a Hall voltage is generated between the N-type diffusion layer 31 and the N-type diffusion layer 34 (see, for example, Patent Document 1).

Japanese Patent Laying-Open No. 2008-008883 (FIG. 17)

Here, in the conventional technique, the current path in the Hall element 30 is formed on the surface of the N-type well 36 which is the outermost surface of the P-type substrate 37. On the surface of the N-type well 36, dirt, dust, etc. generated during cleaning in the manufacturing process of the Hall element 30 adhere. Or there is a flaw or an interface between the silicon and the silicon oxide film. Therefore, the current path of the Hall element 30 is affected by these effects. The current path in the Hall element 30 is also affected by the interface state between the N-type well 36 and the insulating film thereon. All of these become sources of noise, and the characteristics of the Hall voltage generated by the Hall element 30 are varied.

An object of the present invention is to provide a Hall element with little characteristic variation.

In order to solve the above problems, the present invention provides a first conductivity type substrate, a second conductivity type well provided on the substrate, an insulating film provided on the surface of the well, and the same as the well or A potential lower than that of the well is applied, a first conductivity type polysilicon film provided on the insulating film, a depletion layer generated on the well below the insulating film, and the second conductivity A first conductivity type first diffusion layer and a fourth diffusion layer provided opposite to each other in the vicinity of the surface of the mold well, and the polysilicon film in the vicinity of the surface of the second conductivity type well. A second conductive type second and third diffusion layers provided opposite to each other with a straight line connecting the first and fourth diffusion layers and the second and third diffusion layers. Provided is a Hall element in which a connecting straight line intersects.

According to the present invention, the current path in the Hall element is not formed on the surface of the second conductivity type well, which is the outermost surface of the first conductivity type substrate, and is generated on the second conductivity type well below the insulating film. Formed under the depletion layer. Therefore, the current path in the Hall element is not affected by cleaning, dust, etc. in the Hall element manufacturing process, or the influence of defects and interface states, so that variations in Hall voltage characteristics generated by the Hall element are suppressed. The

It is a figure which shows a Hall element, (A) is a top view of a Hall element, (B) is YY sectional drawing in the top view of a Hall element, (C) is ZZ sectional drawing in the top view of a Hall element. is there. It is a figure which illustrates the circuit connection of a Hall element. It is a figure which illustrates the circuit connection of a Hall element. It is an energy band figure, (A) is a thing in case the voltage of an N type polysilicon film is a ground voltage, (B) is a case where the voltage of an N type polysilicon film is a reference voltage lower than a ground voltage belongs to. It is an energy band figure, (A) is a thing in case the voltage of a P-type polysilicon film is a ground voltage, (B) is a case where the voltage of a P-type polysilicon film is a reference voltage lower than a ground voltage belongs to. It is a figure which shows the conventional Hall element, (A) is a top view of the conventional Hall element, (B) is YY sectional drawing in the top view of the conventional Hall element, (C) is the conventional Hall element. It is ZZ sectional drawing in the top view.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First, the structure of the Hall element will be described. FIG. 1 is a view showing a Hall element, (A) is a plan view of the Hall element, (B) is a cross-sectional view along YY in the plan view of the Hall element, and (C) is a plan view of the Hall element. It is sectional drawing along ZZ in a figure.

A P-type substrate 7 is provided with an N-type well 6 that is square in plan view. An insulating film 5 is provided on the N-type well 6 except for the four corners of the Hall element 10. An N-type polysilicon film 8 is provided on the insulating film 5. At the four corners of the Hall element 10, N-type diffusion layers 1 to 4 are provided above the N-type well 6. Here, the N-type diffusion layers 1 to 4 are respectively provided at the edges (four corners) of the N-type well 6 in the plan view. The N-type diffusion layer 1 and the N-type diffusion layer 4 are opposed to each other. And the N-type diffusion layer 3 face each other. The straight line connecting the N-type diffusion layer 1 and the N-type diffusion layer 4 intersects the straight line connecting the N-type diffusion layer 2 and the N-type diffusion layer 3. The N-type well 6 is a diffusion layer having a lower impurity concentration and a deeper impurity distribution than the N-type diffusion layers 1 to 4.

Next, the operation of the Hall element 10 will be described. FIG. 2 is a diagram illustrating the circuit connection of the Hall elements. FIG. 3 is a diagram illustrating circuit connection of the Hall elements. 4A and 4B are energy band diagrams. FIG. 4A shows the case where the voltage of the N-type polysilicon film is the ground voltage, and FIG. 4B shows the reference voltage where the voltage of the N-type polysilicon film is lower than the ground voltage. Is the case.

3, the positive terminal of the power source 21 is connected to the N-type diffusion layer 2 and the negative terminal of the power source 21 is connected to the N-type diffusion layer 3. A voltage lower than the voltage applied to the N-type diffusion layer 2 is applied to the N-type polysilicon film 8. A voltmeter 22 for measuring the Hall voltage is provided between the N-type diffusion layer 1 and the N-type diffusion layer 4.

When there is no voltage difference between the N-type polysilicon film 8 and the N-type well 6, the energy band moves so that the Fermi level matches between the N-type polysilicon film 8 and the N-type well 6 in a thermal equilibrium state. Therefore, a thermal equilibrium state is generated between the N-type polysilicon film 8 and the N-type well 6, and as shown in FIG. 4A, electrons of majority carriers are formed above the N-type well 6 below the insulating film 5. A slight accumulation layer is generated. Therefore, in this case, the current flowing between the N-

type diffusion layers

2 and 3 flows on the surface.

However, when a reference voltage VREF lower than the ground voltage is applied to the N-type polysilicon film 8 by the circuit shown in FIG. 3, the negative reference voltage VREF generates the upper part of the N-type well 6 below the insulating film 5. It is possible to control the formation of a depletion layer. Specifically, when the reference voltage VREF is lowered, the intrinsic Fermi level approaches the Fermi level, and a depletion layer can be formed on the surface of the N-type well 6 as shown in FIG. When the voltage is lowered (the absolute value is increased on the negative side), the depletion layer further expands accordingly. In this state, the surface of the N-type well 6 has almost no electrons as a current carrier due to depletion, so that the current flowing between the N-

type diffusion layers

2 and 3 is lower than the depletion layer near the surface. Then, it flows inside the N-type well 6 which is a deeper portion. Therefore, the hole current that appears when there is a magnetic field also flows inside the N-type well 6, and a Hall voltage is generated between the N-type diffusion layer 1 and the N-type diffusion layer 4. The Hall voltage is measured by a voltmeter 22. The N-type well 6 is free from dirt, dust and scratches present on the surface of the semiconductor substrate and is not affected by the interface. By operating in such a state, noise that affects the Hall current that determines the characteristics of the Hall element is reduced, and variation can be reduced.

Note that an operational amplifier, a comparator, and a reference voltage generation circuit may be provided instead of the voltmeter 22. At this time, the operational amplifier amplifies the Hall voltage. The reference voltage generation circuit generates a reference voltage. The comparator compares the amplified Hall voltage with a reference voltage. When the Hall voltage after amplification is higher than the reference voltage, the output logic of the comparator becomes high level, and when it is low, it becomes low level.

It is also possible to use a P-type polysilicon film instead of the N-type polysilicon film 8. FIG. 5 shows an energy band diagram when a P-type polysilicon film is used. Since the Fermi level is different between the P-type polysilicon film and the N-type polysilicon film 8, the energy band diagrams are also different, and the Fermi level of the P-type polysilicon film and the N-type polysilicon film 8 is shown in FIG. In the thermal equilibrium state where the two coincide with each other, the vicinity of the surface of the N-type well is almost depleted. Therefore, when the device is operated as it is, the hole current flows through the N-type well under the depletion layer. Therefore, it is not affected by dirt, dust, scratches, or the interface between the oxide film and the semiconductor that exists on the surface of the semiconductor substrate. Similar to the case of using the N-type polysilicon film, in this case, noise affecting the Hall current that determines the characteristics of the Hall element is reduced, and variation can be reduced.

When the potential of the P-type polysilicon film is made lower than the potential of the N-type well region, depletion of the N-type well region proceeds, and an inversion layer is formed on the surface. FIG. 5B shows this state. In this case, the depletion layer is formed at a position slightly inside the surface. Therefore, the hole current flows further inside the N-type well region below the depletion layer. In this way, the depth at which the hole current flows can be controlled by controlling the potential difference between the P-type polysilicon film and the N-type well region.

10 Hall element 1-4 N-type diffusion layer 5 Insulating film 6 N-type well 7 P-type substrate 8 N-type polysilicon film

Claims

A first conductivity type substrate;
A second conductivity type well provided on the substrate;
An insulating film provided on the surface of the well;
A first conductive type polysilicon film provided on the insulating film, to which the same potential as the well or lower than the well is applied;
A depletion layer generated above the well under the insulating film;
A first conductivity type first diffusion layer and a fourth diffusion layer provided in the vicinity of the surface of the second conductivity type well opposite to each other with the polysilicon film interposed therebetween;
A second conductivity type second and third diffusion layers provided opposite to each other across the polysilicon film in the vicinity of the surface of the second conductivity type well;
A Hall element in which a straight line connecting the first and fourth diffusion layers intersects with a straight line connecting the second and third diffusion layers.
The Hall element according to claim 1, wherein the second conductivity type well is square in a plan view.
3. The Hall element according to claim 2, wherein the first to fourth diffusion layers are respectively provided at four corners of the well in a plan view.
A first conductivity type substrate;
A second conductivity type well provided on the substrate;
An insulating film provided on the surface of the well;
A potential lower than that of the well, and a second conductive type polysilicon film provided on the insulating film;
A depletion layer generated above the well under the insulating film;
A first conductivity type first diffusion layer and a fourth diffusion layer provided in the vicinity of the surface of the second conductivity type well opposite to each other with the polysilicon film interposed therebetween;
A second conductivity type second and third diffusion layers provided opposite to each other across the polysilicon film in the vicinity of the surface of the second conductivity type well;
A Hall element in which a straight line connecting the first and fourth diffusion layers intersects with a straight line connecting the second and third diffusion layers.
The Hall element according to claim 4, wherein the second conductivity type well is square in a plan view.
6. The Hall element according to claim 5, wherein the first to fourth diffusion layers are respectively provided at four corners of the well in a plan view.