TW201317571A - Wiring defect detecting method, wiring defect detecting apparatus, wiring defect detecting program, and wiring defect detecting program recording medium - Google Patents

Wiring defect detecting method, wiring defect detecting apparatus, wiring defect detecting program, and wiring defect detecting program recording medium Download PDF

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TW201317571A
TW201317571A TW101132399A TW101132399A TW201317571A TW 201317571 A TW201317571 A TW 201317571A TW 101132399 A TW101132399 A TW 101132399A TW 101132399 A TW101132399 A TW 101132399A TW 201317571 A TW201317571 A TW 201317571A
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wiring
short
resistance
resistance value
defect
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TWI518318B (en
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Eiji Yamada
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Sharp Kk
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/52Testing for short-circuits, leakage current or ground faults
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/55Testing for incorrect line connections

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Liquid Crystal (AREA)

Abstract

This wiring defect inspecting method for detecting a wiring short-circuited portion on a semiconductor substrate is characterized in performing: a pre-short-circuiting step of short-circuiting between terminals of wiring to be inspected; and a resistance value measuring step of determining, after the pre-short-circuiting step, whether there is the wiring short-circuited portion or not by measuring a resistance value of the wiring to be inspected.

Description

配線缺陷檢查方法、配線缺陷檢查裝置、配線缺陷檢查程式及配線缺陷檢查程式紀錄媒體 Wiring defect inspection method, wiring defect inspection device, wiring defect inspection program, and wiring defect inspection program recording medium

本發明係關於一種配線缺陷檢查方法、配線缺陷檢查裝置、配線缺陷檢查程式及配線缺陷檢查程式紀錄媒體,其適合於液晶顯示器或有機EL(Electroluminescence,電致發光)顯示器等中所使用之TFT(Thin film transistor,薄膜電晶體)陣列基板、或太陽電池面板等之半導體基板上所形成之配線之缺陷檢測。 The present invention relates to a wiring defect inspection method, a wiring defect inspection device, a wiring defect inspection program, and a wiring defect inspection program recording medium, which are suitable for a TFT used in a liquid crystal display or an organic EL (Electroluminescence) display or the like ( Defect detection of wiring formed on a semiconductor substrate such as a thin film transistor or a solar cell panel.

通常,液晶面板之製造步驟中係經由TFT陣列步驟、單元步驟、及模組步驟等而製造液晶面板。其中,TFT陣列步驟中,於透明基板上平行地配設作為TFT之掃描線而發揮功能之複數根閘極線,並且與閘極線正交地配設有作為信號線而發揮功能之複數根源極線,且以保護膜被覆後,形成透明電極。其後,進行陣列檢查,檢查電極或配線有無短路。 Generally, in the manufacturing process of a liquid crystal panel, a liquid crystal panel is manufactured via a TFT array process, a unit process, a module process, etc. In the TFT array step, a plurality of gate lines functioning as scanning lines of the TFTs are disposed in parallel on the transparent substrate, and a plurality of roots functioning as signal lines are disposed orthogonally to the gate lines. After the electrode is covered with a protective film, a transparent electrode is formed. Thereafter, an array inspection is performed to check whether the electrodes or wiring are short-circuited.

例如,專利文獻1中揭示有一種與利用紅外線放射源檢測基板之短路缺陷之紅外線檢查有關之技術。圖14係該文獻所揭示之薄膜電晶體基板缺陷檢查、修正裝置300之整體構成圖。該薄膜電晶體基板缺陷檢查、修正裝置300係藉由利用施加電壓前後之檢查對象基板301之差異圖像(difference image),檢測因通電而發熱之基板之配線部與短路缺陷部之紅外線圖像,根據線狀或點狀之發熱圖案或缺陷位置、缺陷數量等切換施加電壓、檢測位置、透鏡、 紅外線檢測器303等以檢測發熱之配線,從而可特定缺陷位置。 For example, Patent Document 1 discloses a technique relating to infrared inspection for detecting a short-circuit defect of a substrate by an infrared radiation source. Fig. 14 is a view showing the overall configuration of a thin film transistor substrate defect inspection and correction device 300 disclosed in the document. The thin film transistor substrate defect inspection and correction device 300 detects an infrared image of a wiring portion and a short defect portion of a substrate which generates heat due to energization by using a difference image of the inspection target substrate 301 before and after application of a voltage. Switching the applied voltage, detecting position, lens, etc. according to the linear or dot-like heating pattern or the position of the defect, the number of defects, and the like The infrared ray detector 303 or the like detects the heat generating wiring so that the defect position can be specified.

又,專利文獻2中揭示有如下方法:藉由電性檢查而檢測配置於基板上之複數種配線間之短路,於檢測出短路之情形時,實施紅外線檢查以特定短路位置。電性檢查係對配線間施加電壓而測定電阻值。若電阻值不為無限大,則流通有電流,判斷為存在短路。或,對配線間施加電壓,測定電流值,若電流不為0,則判斷為存在短路。 Further, Patent Document 2 discloses a method of detecting a short circuit between a plurality of types of wirings arranged on a substrate by electrical inspection, and performing an infrared inspection to specify a short-circuit position when a short circuit is detected. The electrical inspection measures the resistance by applying a voltage to the wiring. If the resistance value is not infinite, a current flows and it is determined that there is a short circuit. Alternatively, a voltage is applied to the wiring line, and the current value is measured. If the current is not 0, it is determined that there is a short circuit.

[先前技術文獻] [Previous Technical Literature] [專利文獻] [Patent Literature]

[專利文獻1]日本公開專利公報「日本專利特開平6-207914號公報(1994年7月26日公開)」 [Patent Document 1] Japanese Laid-Open Patent Publication No. Hei 6-207914 (published on July 26, 1994)

[專利文獻2]日本公開專利公報「日本專利特開平2-64594號公報(1990年3月5日公開)」 [Patent Document 2] Japanese Laid-Open Patent Publication No. Hei 2-64594 (published on March 5, 1990)

然而,如上述專利文獻2所揭示之測定配置於基板上之複數種配線間之電阻而檢查配線間之短路之方法中,開始電阻測定後,測定值發生變動,直至其穩定並收斂需要時間。其原因在於,電子零件或電子電路中存在因該等之物理構造而產生之並非設計者意圖之電容成分即雜散電容。 However, in the method of measuring the resistance between the plurality of types of wirings disposed on the substrate and detecting the short circuit between the wirings as disclosed in Patent Document 2, after the resistance measurement is started, the measured value fluctuates until it is stable and converges. This is because the electronic component or the electronic circuit has a stray capacitance which is a capacitance component which is not intended by the designer due to the physical structure.

例如,圖15中表示電阻測定時之一般等效電路。雜散電容係作為相當於電容器312之電荷容量者而予以記載。電阻311之電阻值係與電容器312並聯連接之電阻成分。電阻 315之電阻值係與電容器312串聯連接之電阻成分。此處,測定電阻311與電阻315之電阻之合計值。於是,介隔基板上之近接之配線或配線與配線間之絕緣層出現靜電電容,此將對電阻測定動作造成影響。 For example, a general equivalent circuit at the time of resistance measurement is shown in FIG. The stray capacitance is described as equivalent to the charge capacity of the capacitor 312. The resistance value of the resistor 311 is a resistance component connected in parallel with the capacitor 312. resistance The resistance value of 315 is a resistance component connected in series with the capacitor 312. Here, the total value of the resistances of the resistor 311 and the resistor 315 is measured. As a result, electrostatic capacitance occurs in the insulating layer between the wiring or the wiring on the substrate and the wiring, which affects the resistance measurement operation.

具體而言,圖15中,閉合開關313、由電源314施加電壓而開始電阻測定時,因閉合開關313後立即出現雜散電容,故與電阻311之電阻值狀況無關,形式上以電容器312之兩端之節點316與節點317短路之方式流通電流。最初,電流流向電容器312一方,繼而,電容器312與電阻311中流通電流,若電容器312之充電結束,則僅電阻311中流通電流。該現象被稱作介電吸收,介電吸收收斂後,可正確測定電阻311與電阻315之電阻之合計值。 Specifically, in FIG. 15, when the switch 313 is closed and the voltage is applied by the power source 314 to start the resistance measurement, the stray capacitance occurs immediately after the switch 313 is closed, so that it is in the form of the capacitor 312 regardless of the resistance value of the resistor 311. The current is transmitted in such a manner that the node 316 at both ends is short-circuited with the node 317. First, a current flows to the capacitor 312, and then a current flows through the capacitor 312 and the resistor 311. When the charging of the capacitor 312 is completed, only a current flows through the resistor 311. This phenomenon is called dielectric absorption, and after the dielectric absorption is converged, the total value of the resistances of the resistor 311 and the resistor 315 can be accurately measured.

又,亦有藉由其他配線間之電阻測定或靜電,使電容器312事先少量帶電之情形,因此,亦有根據將要進行電阻測定前之電容器312之充電量,直至介電吸收收斂為止之時間發生變動,電阻測定所需之總測定時間產生偏差之情形。若測定時間存在偏差,則需較長地估計直至介電吸收收斂為止之時間而進行測定,或基於以往之測定資料,配合最長之測定時間進行各測定。因此,有一次所花費之檢查時間變長以致檢查效率下降之問題。 Further, there is a case where the capacitor 312 is charged a small amount in advance by resistance measurement or static electricity in the other wiring compartments. Therefore, depending on the amount of charge of the capacitor 312 before the resistance measurement is performed, the time until the dielectric absorption converges occurs. Variation, the case where the total measurement time required for resistance measurement is deviated. If there is a variation in the measurement time, it is necessary to estimate the time until the dielectric absorption converges for a long period of time, or to perform each measurement based on the measurement data of the past and the longest measurement time. Therefore, there is a problem that the inspection time taken is lengthened so that the inspection efficiency is lowered.

本發明係鑒於上述問題點而完成者,其目的在於提供一種配線缺陷檢查方法、配線缺陷檢查裝置、配線缺陷檢查程式及配線缺陷檢查程式紀錄媒體,其可在檢測TFT陣列基板等半導體基板之缺陷時,抑制測定時間之偏差,從而 以恰當之測定時間正確且效率良好地檢查缺陷。 The present invention has been made in view of the above problems, and an object thereof is to provide a wiring defect inspection method, a wiring defect inspection device, a wiring defect inspection program, and a wiring defect inspection program recording medium which can detect defects of a semiconductor substrate such as a TFT array substrate. Inhibiting the deviation of the measurement time, thereby The defect is checked correctly and efficiently with the appropriate measurement time.

本發明之配線缺陷檢查方法之特徵在於:其係進行半導體基板中之配線短路部之檢測者,且進行如下步驟:預短路步驟,其係使檢查對象之配線之端子間短路;及電阻值測定步驟,其係於上述預短路步驟之後測定上述檢查對象之配線之電阻值,藉此判定有無上述配線短路部。 The wiring defect inspection method according to the present invention is characterized in that it is a method of detecting a short-circuit portion of a wiring in a semiconductor substrate, and performing a pre-shorting step of short-circuiting between terminals of a wiring to be inspected; and measuring a resistance value In the step of measuring the resistance value of the wiring to be inspected after the pre-short circuit step, it is determined whether or not the wiring short-circuit portion is present.

本發明之配線缺陷檢查裝置之特徵在於:其係進行半導體基板中之配線短路部之檢測者,且包含:預短路部,其使檢查對象之配線之端子間短路;電壓施加部,其對上述檢查對象之配線施加電壓;電阻測定部,其測定上述配線之電阻值;及控制部,其控制上述電壓施加部;且基於藉由上述電阻測定部所測定之電阻值,判定有無上述配線短路部。 The wiring defect inspection device according to the present invention is characterized in that it detects a short-circuit portion of a wiring in a semiconductor substrate, and includes a pre-short portion that short-circuits between terminals of a wiring to be inspected, and a voltage applying portion that faces the above a voltage applied to the wiring of the inspection target; a resistance measuring unit that measures a resistance value of the wiring; and a control unit that controls the voltage application unit; and determines whether or not the wiring short-circuit portion is formed based on a resistance value measured by the resistance measuring unit .

本發明之配線缺陷檢查程式之特徵在於:其係使上述配線缺陷檢查裝置進行動作者,且使電腦作為上述各機構發揮功能。 The wiring defect inspection program according to the present invention is characterized in that the wiring defect inspection device is operated by an operator and the computer functions as each of the above-described mechanisms.

本發明之配線缺陷檢查程式紀錄媒體之特徵在於:記錄有上述之配線缺陷檢查程式。 The wiring defect inspection program recording medium of the present invention is characterized in that the wiring defect inspection program described above is recorded.

根據本發明,可於檢測TFT基板等半導體基板之缺陷時,抑制測定時間之偏差,從而以恰當之測定時間正確且效率良好地檢查缺陷。 According to the present invention, when a defect of a semiconductor substrate such as a TFT substrate is detected, variation in measurement time can be suppressed, and defects can be inspected accurately and efficiently with an appropriate measurement time.

以下,一面參照圖一面就本發明之實施形態進行說明。再者,本發明之圖式中,相同之參照符號係表示相同之部分或相當之部分。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same reference numerals are used to refer to the same or equivalent parts.

<實施形態1> <Embodiment 1>

圖1(a)係表示本實施形態之配線缺陷檢查裝置100之構成的方塊圖;圖1(b)係作為使用配線缺陷檢查裝置100進行配線缺陷檢查之對象之母基板1的立體圖。此處,如圖1(b)所示,母基板1上形成有P1~P8之8片液晶面板。 1(a) is a block diagram showing the configuration of the wiring defect inspection device 100 of the present embodiment, and FIG. 1(b) is a perspective view of the mother substrate 1 as a target for performing wiring defect inspection using the wiring defect inspection device 100. Here, as shown in FIG. 1(b), eight liquid crystal panels of P1 to P8 are formed on the mother substrate 1.

配線缺陷檢查裝置100可檢查圖1(b)所示之母基板1上所形成之複數個液晶面板2中之配線等之缺陷。因此,配線缺陷檢查裝置100包含用於與液晶面板2導通之探針3、及將探針3移動至各液晶面板2上之探針移動機構4。又,配線缺陷檢查裝置100包含用於取得紅外線圖像之紅外線相機5、及使紅外線相機5在液晶面板2上移動之相機移動機構6。進而,配線缺陷檢查裝置100包含控制探針移動機構4及相機移動機構6之主控制部7。 The wiring defect inspection apparatus 100 can inspect the defects of the wiring or the like in the plurality of liquid crystal panels 2 formed on the mother substrate 1 shown in FIG. 1(b). Therefore, the wiring defect inspection apparatus 100 includes the probe 3 for conducting the liquid crystal panel 2 and the probe moving mechanism 4 for moving the probe 3 to each of the liquid crystal panels 2. Further, the wiring defect inspection device 100 includes an infrared camera 5 for acquiring an infrared image and a camera moving mechanism 6 for moving the infrared camera 5 on the liquid crystal panel 2. Further, the wiring defect inspection device 100 includes a main control unit 7 that controls the probe moving mechanism 4 and the camera moving mechanism 6.

上述探針3上連接有用於測定液晶面板2之配線間之電阻之電阻測定部8、用於對液晶面板2之配線間施加電壓之電壓施加部9、及作為事先使測定對象之端子間短路之開關之預短路部10。該等電阻測定部8、電壓施加部9及預短路部10由主控制部7予以控制。 The probe 3 is connected to a resistance measuring unit 8 for measuring the electric resistance between the wirings of the liquid crystal panel 2, a voltage applying unit 9 for applying a voltage between the wirings of the liquid crystal panel 2, and a short-circuit between the terminals to be measured in advance. The pre-short circuit portion 10 of the switch. The resistance measuring unit 8, the voltage applying unit 9, and the pre-short circuit unit 10 are controlled by the main control unit 7.

圖2係表示本實施形態之配線缺陷檢查裝置100之構成的立體圖。如圖2所示,配線缺陷檢查裝置100構成為於基台上設置有對準載物台11,且對準載物台11上可載置母基板 1。載置有母基板1之對準載物台11以與探針移動機構4及相機移動機構6之XY座標軸平行地進行位置調整。此時,對準載物台11之位置調整中使用設置於對準載物台11之上方且用於確認母基板1之位置之光學相機12。 Fig. 2 is a perspective view showing the configuration of the wiring defect inspection device 100 of the present embodiment. As shown in FIG. 2, the wiring defect inspection apparatus 100 is configured such that an alignment stage 11 is disposed on the base, and the mother substrate can be placed on the alignment stage 11. 1. The alignment stage 11 on which the mother substrate 1 is placed is positionally adjusted in parallel with the XY coordinate axes of the probe moving mechanism 4 and the camera moving mechanism 6. At this time, the position adjustment of the alignment stage 11 uses an optical camera 12 provided above the alignment stage 11 for confirming the position of the mother substrate 1.

上述探針移動機構4設置成可於配置在對準載物台11之外側之導軌13a上進行滑動。又,於探針移動機構4之本體側亦設置有導軌13b及13c,且以可沿該等導軌13於XYZ之各座標方向上移動之方式設置有安裝部14a。於該安裝部14a搭載有與液晶面板2對應之探針3。 The probe moving mechanism 4 is provided to be slidable on the guide rail 13a disposed on the outer side of the alignment stage 11. Further, guide rails 13b and 13c are provided on the main body side of the probe moving mechanism 4, and mounting portions 14a are provided so as to be movable in the respective coordinate directions of the XYZ along the guide rails 13. The probe 3 corresponding to the liquid crystal panel 2 is mounted on the mounting portion 14a.

上述相機移動機構6設置成可於配置在探針移動機構4之外側之導軌13d上進行滑動。又,於相機移動機構6之本體亦設置有導軌13e及13f,且3處安裝部14b、14c及14d分別可沿該等導軌13於XYZ之各座標方向上移動。 The camera moving mechanism 6 is provided to be slidable on the guide rail 13d disposed on the outer side of the probe moving mechanism 4. Further, the main body of the camera moving mechanism 6 is also provided with guide rails 13e and 13f, and the three mounting portions 14b, 14c and 14d are respectively movable along the guide rails 13 in the respective coordinate directions of XYZ.

於安裝部14c搭載有宏觀計測用之紅外線相機5a,於安裝部14b搭載有微觀計測用之紅外線相機5b,又,於安裝部14d搭載有光學相機16。 The infrared camera 5a for macro measurement is mounted on the mounting portion 14c, the infrared camera 5b for microscopic measurement is mounted on the mounting portion 14b, and the optical camera 16 is mounted on the mounting portion 14d.

宏觀計測用之紅外線相機5a係視野可拓寬至520×405 mm左右之可進行宏觀計測之紅外線相機。為拓寬視野,宏觀計測用之紅外線相機5a例如組合4台紅外線相機而構成。即,每一台宏觀計測用之紅外線相機之視野為一片液晶面板2之大小之大致1/4。又,微觀計測用之紅外線相機5b雖視野較小為32×24 mm左右,但為可進行高解析度之攝影之可微觀計測之紅外線相機。 The infrared camera 5a for macro measurement can be expanded to a depth of 520 × 405 mm for infrared measurement of macroscopic cameras. In order to broaden the field of view, the infrared camera 5a for macro measurement is configured by, for example, combining four infrared cameras. That is, the field of view of the infrared camera for each macro measurement is approximately 1/4 of the size of one liquid crystal panel 2. Further, the infrared camera 5b for microscopic measurement has a small field of view of about 32 × 24 mm, but is an infrared camera capable of microscopic measurement capable of high-resolution photography.

再者,相機移動機構6中亦可追加安裝部,以搭載用於 修正缺陷部位之雷射照射裝置。藉由搭載雷射照射裝置,可於特定缺陷部之位置後,藉由對缺陷部照射雷射而連續地進行缺陷修正。 Further, an attachment portion may be added to the camera moving mechanism 6 for mounting Correct the laser irradiation device of the defective part. By mounting the laser irradiation device, it is possible to continuously perform defect correction by irradiating the defective portion with a laser after the position of the specific defect portion.

探針移動機構4及相機移動機構6分別設置於不同之導軌13a及13d上。因此,可於對準載物台11之上方沿X座標方向互不干涉地移動。藉此,可在使探針3接觸液晶面板2之狀態下使紅外線相機5a、5b及光學相機16移動至液晶面板2上。 The probe moving mechanism 4 and the camera moving mechanism 6 are respectively disposed on different guide rails 13a and 13d. Therefore, it is possible to move without interference in the X coordinate direction above the alignment stage 11. Thereby, the infrared cameras 5a and 5b and the optical camera 16 can be moved to the liquid crystal panel 2 with the probe 3 in contact with the liquid crystal panel 2.

圖3(a)係形成於母基板1上之複數個液晶面板2中之一個液晶面板2的俯視圖。如圖3(a)所示,各液晶面板2上形成有像素部17、周邊配線部18、及端子部19a~19d。像素部17形成有閘極線與源極線,進而於閘極線與源極線交叉之各交點形成有TFT。周邊配線部18形成有將閘極線及源極線與端子部19a~19d連接之配線。 FIG. 3(a) is a plan view of one of the plurality of liquid crystal panels 2 formed on the mother substrate 1. As shown in FIG. 3(a), the liquid crystal panel 2 is formed with a pixel portion 17, a peripheral wiring portion 18, and terminal portions 19a to 19d. The pixel portion 17 is formed with a gate line and a source line, and a TFT is formed at each intersection of the gate line and the source line. Wiring for connecting the gate line and the source line to the terminal portions 19a to 19d is formed in the peripheral wiring portion 18.

圖3(b)係用於與設置於液晶面板2上之端子部19a~19d導通之探針3的俯視圖。探針3形成為大小與圖3(a)所示之液晶面板2之大小大致相同之框狀的形狀,且具備與設置於液晶面板2上之端子部19a~19d對應之複數個探針21a~21d。複數個探針21a~21d可經由繼電器(未圖示)逐個將探針21個別地連接於圖1(a)所示之電阻測定部8及電壓施加部9。因此,探針3可選擇性地連接於與端子部19a~19d相連之複數根配線,或總括地連接複數根配線。又,探針3形成為大小與液晶面板2大致相同之框之形狀。再者,如上所述,藉由使用光學相機12進行母基板1之位置調整, 而使端子部19a~19d及探針21a~21d之位置對準。 FIG. 3(b) is a plan view of the probe 3 for conducting electricity with the terminal portions 19a to 19d provided on the liquid crystal panel 2. The probe 3 is formed in a frame shape having a size substantially equal to that of the liquid crystal panel 2 shown in FIG. 3(a), and includes a plurality of probes 21a corresponding to the terminal portions 19a to 19d provided on the liquid crystal panel 2. ~21d. The plurality of probes 21a to 21d can individually connect the probes 21 to the resistance measuring unit 8 and the voltage applying unit 9 shown in Fig. 1(a) via relays (not shown). Therefore, the probe 3 can be selectively connected to a plurality of wires connected to the terminal portions 19a to 19d, or a plurality of wires can be connected in total. Further, the probe 3 is formed into a shape of a frame having substantially the same size as that of the liquid crystal panel 2. Furthermore, as described above, the position adjustment of the mother substrate 1 is performed by using the optical camera 12, The positions of the terminal portions 19a to 19d and the probes 21a to 21d are aligned.

如上所述,本實施形態之配線缺陷檢查裝置100具備探針3及連接於探針3之電阻測定部8,將探針3與液晶面板2導通,可測定各配線之電阻值及鄰接之配線間之電阻值等。 As described above, the wiring defect inspection apparatus 100 of the present embodiment includes the probe 3 and the resistance measuring unit 8 connected to the probe 3. The probe 3 and the liquid crystal panel 2 are electrically connected to each other, and the resistance value of each wiring and the adjacent wiring can be measured. The resistance value between them.

又,本實施形態之配線缺陷檢查裝置100具備探針3、連接於探針3之電壓施加部9、及紅外線相機5a及5b。並且,經由探針3對液晶面板2之配線或配線間施加電壓,利用紅外線相機5a及5b計測缺陷部中流通電流所引起之發熱,從而可特定缺陷部之位置。因此,根據本實施形態之配線缺陷檢查裝置100,可藉由1台檢查裝置兼用而進行電阻檢查及紅外線檢查。 Further, the wiring defect inspection apparatus 100 of the present embodiment includes a probe 3, a voltage application unit 9 connected to the probe 3, and infrared cameras 5a and 5b. Then, a voltage is applied between the wiring or the wiring of the liquid crystal panel 2 via the probe 3, and the heat generated by the current flowing through the defective portion is measured by the infrared cameras 5a and 5b, whereby the position of the defective portion can be specified. Therefore, according to the wiring defect inspection apparatus 100 of the present embodiment, the resistance inspection and the infrared inspection can be performed by using one inspection apparatus.

圖4係使用本實施形態之配線缺陷檢查裝置100之配線缺陷檢查方法之流程圖。流程圖中之S表示各步驟。如圖4所示,本實施形態之配線缺陷檢查方法係藉由步驟S1~步驟S10之步驟,對形成於母基板1上之複數個液晶面板2依次實施配線缺陷檢查。 Fig. 4 is a flowchart showing a wiring defect inspection method using the wiring defect inspection device 100 of the present embodiment. The S in the flowchart indicates each step. As shown in FIG. 4, in the wiring defect inspection method of the present embodiment, the wiring defect inspection is sequentially performed on the plurality of liquid crystal panels 2 formed on the mother substrate 1 by the steps S1 to S10.

首先,於步驟S1中,將母基板1載置於配線缺陷檢查裝置100之對準載物台11上,以與XY座標軸平行之方式調整基板之位置。繼而,於步驟S2中,利用探針移動機構4使探針3移動至成為檢查對象之液晶面板2之上部,使探針21a~21d與液晶面板2之端子部19a~19d接觸。此處,於步驟S3中,使成為測定對象之配線或配線間之全部端子短路。該短路處理係指藉由閉合分別連接於探針21a~21d之 繼電器(未圖示),使探針之間電性短路。形成於液晶面板2上之閘極線與源極線原本並未電性連接,但該短路動作中,成為測定對象之配線或配線間成為電性連接之狀態。 First, in step S1, the mother substrate 1 is placed on the alignment stage 11 of the wiring defect inspection apparatus 100, and the position of the substrate is adjusted so as to be parallel to the XY coordinate axis. Then, in step S2, the probe moving mechanism 4 moves the probe 3 to the upper portion of the liquid crystal panel 2 to be inspected, and the probes 21a to 21d are brought into contact with the terminal portions 19a to 19d of the liquid crystal panel 2. Here, in step S3, all the terminals of the wiring to be measured or the wiring are short-circuited. The short circuit treatment refers to being connected to the probes 21a 21d by being closed respectively. Relays (not shown) electrically short the probes. The gate line and the source line formed on the liquid crystal panel 2 are not electrically connected to each other. However, in the short-circuit operation, the wiring or the wiring to be measured is electrically connected.

通常,液晶面板上平行地配設有作為掃描線而發揮功能之複數根閘極線,並且與閘極線正交地配設有作為信號線而發揮功能之複數根源極線,進而,為使像素之電壓保持固定,亦配設有蓄積有電荷之輔助電容線(以下,稱作Cs線)。又,除此之外,亦有為修復斷線或短路之配線而配置有預備配線之情形。本發明亦可於測定與該等配線之任一者之電阻時予以應用。本實施形態中,作為一例,測定閘極線、源極線、Cs線之配線或配線間之電阻。步驟S3中,使閘極線、源極線、及Cs線之全部端子短路。 Usually, a plurality of gate lines functioning as scanning lines are disposed in parallel on the liquid crystal panel, and a plurality of source lines functioning as signal lines are disposed orthogonally to the gate lines, and further, The voltage of the pixel is kept constant, and a storage capacitor line (hereinafter referred to as a Cs line) in which electric charge is accumulated is also disposed. Further, in addition to this, there is a case where the backup wiring is arranged to repair the disconnected or short-circuited wiring. The invention can also be applied when measuring the electrical resistance of any of these wirings. In the present embodiment, as an example, the electric resistance between the wiring of the gate line, the source line, the Cs line, or the wiring is measured. In step S3, all the terminals of the gate line, the source line, and the Cs line are short-circuited.

圖5係以等效電路表示本實施形態之電阻測定者。定電壓電源59係內置於作為電阻測定部8之一部分之電阻測定器中之電源。圖5(a)所示之等效電路係測定對象之液晶面板2中有短路缺陷之情形,節點56與節點57之間係經由電阻55、電阻53而導通之狀態。圖5(b)所示之等效電路係無短路缺陷之良品之液晶面板2之等效電路。虛線58所包圍之電路部分表示液晶面板2。又,未被包圍之電路部分即較節點56、57靠紙面左側之部分表示電阻測定部8及預短路部10。電容器54表示雜散電容;電阻53表示並聯連接於電容器54之電阻值;電阻55表示串聯連接於電容器54之電阻值。 Fig. 5 is a diagram showing an electric resistance measurer of the present embodiment in an equivalent circuit. The constant voltage power source 59 is incorporated in a power source that is a part of the resistance measuring unit 8 and is a power source. The equivalent circuit shown in FIG. 5( a ) is a state in which a short-circuit defect is present in the liquid crystal panel 2 to be measured, and the node 56 and the node 57 are electrically connected via the resistor 55 and the resistor 53 . The equivalent circuit shown in FIG. 5(b) is an equivalent circuit of the liquid crystal panel 2 which is free from short-circuit defects. The portion of the circuit surrounded by the broken line 58 represents the liquid crystal panel 2. Further, the circuit portion that is not surrounded, that is, the portion on the left side of the paper surface of the nodes 56 and 57, indicates the resistance measuring unit 8 and the pre-short circuit portion 10. Capacitor 54 represents a stray capacitance; resistor 53 represents a resistance value connected in parallel to capacitor 54; and resistor 55 represents a resistance value connected in series to capacitor 54.

閉合開關52之狀態表示電阻測定中。藉由閉合開關52, 定電壓電源59對連接於2根被測定配線之節點56與節點57之間施加電壓。若2根被測定配線間發生短路時,流通電流。電阻測定部8測定節點56與節點57間之電阻。 The state of the closed switch 52 indicates that the resistance is being measured. By closing the switch 52, The constant voltage source 59 applies a voltage between the node 56 connected to the two wires to be measured and the node 57. When a short circuit occurs between the two wires to be measured, a current flows. The resistance measuring unit 8 measures the electric resistance between the node 56 and the node 57.

又,亦可代替測定電阻而測定電流。該情形時,測定電流,將定電壓電源59之電壓值除以電流值而求取電阻值。若2根被測定配線間未發生短路時,不流通電流,故而電阻值成為無限大。 Further, the current can be measured instead of measuring the resistance. In this case, the current is measured, and the voltage value of the constant voltage source 59 is divided by the current value to obtain a resistance value. When there is no short circuit between the two connected wirings, no current flows, and the resistance value becomes infinite.

步驟S3中,於打開開關52之狀態下,閉合作為預短路部10之開關51,使成為測定對象之配線或配線間之全部端子短路,並放置特定時間以使其自然放電。放電後,打開開關51。將閉合該開關51、經過特定時間後打開開關51之動作稱作預短路處理。繼而,步驟S4中,與各種缺陷模式對應地選擇用於進行電阻檢查之配線或配線間,進行導通之探針21之切換。就缺陷模式於後予以說明。 In the state in which the switch 52 is turned on, the switch 51 as the pre-short circuit portion 10 is closed, and all the terminals of the wiring or the wiring to be measured are short-circuited, and placed for a predetermined period of time to be naturally discharged. After the discharge, the switch 51 is turned on. The operation of closing the switch 51 and opening the switch 51 after a certain period of time is referred to as a pre-short circuit process. Then, in step S4, the wiring or the wiring for performing the resistance inspection is selected in accordance with various defect modes, and the probe 21 that is turned on is switched. The defect mode will be described later.

步驟S5中,閉合圖5之開關52,進行電阻檢查。步驟S5中,測定選出之配線或配線間之電阻值,藉由對該電阻值與無缺陷時之電阻值進行比較而檢查有無缺陷。 In step S5, the switch 52 of Fig. 5 is closed to perform a resistance check. In step S5, the resistance value between the selected wiring or the wiring is measured, and the presence or absence of the defect is checked by comparing the resistance value with the resistance value at the time of no defect.

圖6係閉合開關52後之電流值之變化的一例;圖6(a)表示液晶面板2中有短路缺陷之情形;圖6(b)表示無短路缺陷之情形。又,縱軸為電流值I,橫軸為時間t。閉合開關52後,電流立即流向電容器54與電阻53兩方,開始電容器54之充電。此時,於液晶面板2中有短路缺陷時,如圖6(a)所示,隨著電容器54之充電接近完畢,電容器54中流通之電流逐漸減少,而電阻53即此處稱作短路缺陷部分中流通之 電流逐漸增加。最終,電容器54之充電完畢之時間t0以後,電阻53中繼續流通固定之電流I0Fig. 6 is an example of a change in current value after the switch 52 is closed; Fig. 6(a) shows a case where a short-circuit defect is present in the liquid crystal panel 2, and Fig. 6(b) shows a case where there is no short-circuit defect. Further, the vertical axis represents the current value I and the horizontal axis represents the time t. After the switch 52 is closed, the current immediately flows to both the capacitor 54 and the resistor 53 to start charging of the capacitor 54. At this time, when there is a short defect in the liquid crystal panel 2, as shown in FIG. 6(a), as the charging of the capacitor 54 approaches, the current flowing in the capacitor 54 gradually decreases, and the resistor 53 is referred to herein as a short defect. The current flowing in the part gradually increases. Finally, after the time t 0 after the completion of the charging of the capacitor 54, the fixed current I 0 continues to flow through the resistor 53.

另一方面,於液晶面板2中無短路缺陷而為良品時,如圖6(b)所示,電容器54之充電完畢之時間t0以後不流通電流,測定之電阻值變為無限大。 On the other hand, when there is no short-circuit defect in the liquid crystal panel 2 and it is good, as shown in FIG. 6(b), the current does not flow after the time t 0 of completion of charging of the capacitor 54, and the measured resistance value becomes infinite.

圖6(c)表示未進行步驟S3中所示之於電阻測定前使成為測定對象之配線或配線間之全部端子短路之步驟即預短路處理,而以先前之方法進行若干電阻測定時之經過時間與電流值。電容器54之充電完畢之時間並不固定,有時間較圖6(a)、圖6(b)所示之電容器之充電完畢之時間t0長之情形亦有較其短之情形。即,電阻測定所需之時間產生偏差。 (c) of FIG. 6 shows a pre-short circuit which is a step of short-circuiting all the terminals between the wirings or wirings to be measured before the resistance measurement in step S3, and the resistance measurement is performed by the previous method. Time and current values. The charging time of the capacitor 54 is not fixed, and the time is longer than the time t 0 when the charging of the capacitor shown in Fig. 6 (a) and Fig. 6 (b) is completed. That is, the time required for the resistance measurement varies.

本發明中,步驟S3中,因事先於電阻測定前使成為測定對象之配線或配線間之全部端子短路,並進行電容器54之放電,故電容器54之帶電自0之狀態開始測定。因此,電容器54之充電完畢之時間t0一直為固定,直至判定液晶面板2中是否有短路缺陷為止之時間亦為固定,可抑制測定時間之偏差。又,可除去靜電引起之帶電。 In the present invention, in the step S3, all the terminals of the wiring or the wiring to be measured are short-circuited before the resistance measurement, and the capacitor 54 is discharged. Therefore, the charging of the capacitor 54 is started from the state of 0. Therefore, the time t 0 at which the charging of the capacitor 54 is completed is always fixed until the time for determining whether or not there is a short-circuit defect in the liquid crystal panel 2 is fixed, and the variation in the measurement time can be suppressed. Moreover, charging due to static electricity can be removed.

圖7係詳細說明實施形態1之電阻值測定步驟的圖。圖7係對於短路缺陷部之電阻值不同之R1~R4(電阻值係R4=∞且R3>R2>R1),以時間t之經過表示自測定開始之電阻測定器之指示值R之變化。 Fig. 7 is a view for explaining in detail the step of measuring the resistance value in the first embodiment. Fig. 7 shows changes in the resistance value of the short-circuit defective portion, R1 to R4 (resistance value R4 = ∞ and R3 > R2 > R1), and the change in the indication value R of the resistance measuring device from the start of the measurement is expressed by the elapse of time t.

關於無短路缺陷部之電阻值為無限大之R4,指示值R較配線間之電容器54之充電完畢而可進行電阻測定之時間t0更早地超過測定極限,而成為過載(OL,Over Load),從 而判定為無短路缺陷。此處,所謂過載表示電阻測定部8測定出可測定之最大電阻值之狀態。因該最大電阻值為足夠大之電阻值,故判斷過載狀態為無短路缺陷。另一方面,缺陷短路部之電阻值為有限之R1~R3係於指示值R穩定之後,將時間t0之指示值R作為短路缺陷部之電阻值而與特定閾值TR進行比較,藉此可判定有無短路缺陷。例如,若如R3般電阻值為液晶面板2之顯示上不存在問題之程度之高電阻則判定為良品,於如R1或R2般電阻值為特定閾值TR以下之情形時判定為有短路缺陷。 Regarding the R4 in which the resistance value of the short-circuit-free defect portion is infinite, the indication value R is higher than the measurement limit at the time t 0 at which the resistance of the capacitor 54 between the wirings is completed, and becomes an overload (OL, Over Load) ), thereby determining that there is no short circuit defect. Here, the overload indicates the state in which the resistance measuring unit 8 measures the maximum measurable resistance value. Since the maximum resistance value is a sufficiently large resistance value, it is judged that the overload state is no short-circuit defect. On the other hand, R1 to R3 of the defect short-circuit portion are limited, and after the indication value R is stabilized, the indication value R of the time t 0 is compared with the specific threshold value T R as the resistance value of the short-circuit defect portion. It can be determined whether there is a short circuit defect. For example, if the resistance value such as R3 is high, the resistance is such that there is no problem in the display of the liquid crystal panel 2, and it is judged to be a short defect when the resistance value is equal to or less than a certain threshold value T R such as R1 or R2. .

實施形態1中,藉由進行預短路處理,可抑制直至電阻測定器之指示值R穩定為止之時間t0之偏差,故而藉由選定恰當之測定時間t0進行測定,可根據電阻值正確檢查缺陷。 In the first embodiment, by performing the pre-short circuit processing, it is possible to suppress the deviation from the time t 0 until the indication value R of the resistance measuring device is stabilized. Therefore, by selecting the appropriate measurement time t 0 for measurement, the resistance value can be correctly checked. defect.

然而,直至指示值R穩定為止所需之時間t0通常需要3秒左右。因此,例如於檢查如液晶面板般之多根配線之情形時,因測定次數變多,故電阻值測定步驟之間歇時間變長。 However, the time t 0 required until the indication value R is stabilized usually takes about 3 seconds. Therefore, for example, when a plurality of wirings such as a liquid crystal panel are inspected, since the number of times of measurement increases, the intermittent time of the resistance value measuring step becomes long.

因此,期望無需等至指示值R穩定之時間t0,而可於指示值R穩定前之測定剛開始後之過渡期中判定有無短路缺陷。如圖7所示,測定開始後之過渡期中,若於時間t01與時間t02之間求取指示值R之變化率,則相對於電阻R1~R4而成為如△r1~△r4般。 Therefore, it is desirable to wait for the time t 0 at which the indication value R is stable, and to determine whether or not there is a short-circuit defect in the transition period immediately after the start of the measurement before the indication value R is stabilized. As shown in FIG. 7, in the transition period after the start of the measurement, if the rate of change of the indication value R is obtained between time t 01 and time t 02 , it becomes Δr 1 to Δr 4 with respect to the resistors R1 to R4. Like.

若事先測定該變化率△r與時間t0之指示值R即短路缺陷部之電阻值,收集測定資料而作成表格,則例如圖8所 示,變化率△r與短路缺陷部之電阻值之關係成為比例關係。因此,藉由求得該指示值R之變化率△r,決定時間t0時所預測之電阻值,可判定有無短路缺陷。又,即使根據測定條件等,變化率△r與短路缺陷部之電阻值完全不為比例關係時,對應關係仍可事先自測定資料求得,從而可以相同之方法判定有無短路缺陷。 When the resistance value of the short-circuit defect portion, that is, the indication value R of the change rate Δr and the time t 0 is measured in advance, and the measurement data is collected and formed into a table, for example, as shown in FIG. 8, the change rate Δr and the resistance value of the short-circuit defect portion are Relationships become proportional relationships. Therefore, by determining the rate of change Δr of the indication value R and determining the resistance value predicted at time t 0 , it is possible to determine whether or not there is a short circuit defect. Further, even if the change rate Δr is not proportional to the resistance value of the short-circuit defect portion according to the measurement conditions or the like, the correspondence relationship can be obtained from the measurement data in advance, and the presence or absence of the short-circuit defect can be determined by the same method.

具體而言,如圖8所示,可將指示值R之變化率△r與特定閾值Tr進行比較,將△r1、△r2小於閾值Tr之情形判定為有短路缺陷者。變化率△r可以測定開始後之時間t01與時間t02之至少2次之電阻測定值之差量求得。例如,最初之時間t01係自測定開始後之100 ms後,其次之時間t02係自測定開始後之300 ms後,且均可設為遠早於時間t0之測定時間。又,特定閾值Tr只要自實際測定所收集之變化率△r與電阻值之資料,憑經驗選擇恰當之值即可。如此,藉由於測定剛開始後之過渡期中求得指示值R之變化率△r而決定電阻值,即使如檢查多根配線之情形時,仍可縮短電阻值測定步驟之間歇時間。 Specifically, as shown, may be a value indicating the change of rate R with the particular threshold △ r 8 T r comparing the △ r 1, △ r 2 is smaller than the threshold value T r of the case is determined by short-circuit defect. The rate of change Δr can be determined by measuring the difference between the measured values of the resistance at least two times from the start time t 01 and the time t 02 . For example, the initial time t 01 is 100 ms after the start of the measurement, and the second time t 02 is 300 ms after the start of the measurement, and can be set to a measurement time much earlier than the time t 0 . Further, the specific threshold value T r may be selected from an appropriate value by empirically selecting the data of the rate of change Δr and the resistance value collected from the actual measurement. In this manner, the resistance value is determined by determining the rate of change Δr of the indication value R during the transition period immediately after the start of the measurement, and the intermittent time of the resistance value measurement step can be shortened even when a plurality of wirings are inspected.

再者,實施形態1中係利用測定開始後之時間t01與時間t02之至少2次之電阻測定所得之指示值R之差量求得變化率△r,但當然亦可進行3次以上之電阻測定,藉由線性內插所得之複數個指示值R求得變化率△r,而於電阻值測定步驟中予以使用,且可進一步提高短路缺陷之檢測精度。 In the first embodiment, the rate of change Δr is obtained by using the difference between the indication values R obtained by measuring the resistance at least two times from the time t 01 and the time t 02 after the start of the measurement, but it is of course possible to perform the third time or more. In the resistance measurement, the change rate Δr is obtained by a plurality of indication values R obtained by linear interpolation, and is used in the resistance value measurement step, and the detection accuracy of the short-circuit defect can be further improved.

又,根據短路缺陷部之狀態等,有即使於過渡期之最初期之階段仍可檢測與短路缺陷部之電阻值對應之變化率△r 之情形,從而亦可於電阻值測定步驟中,僅於時間t01測定一次指示值R之變化率△r,而求得自時間0起之變化率△r。該情形時,因僅於過渡期之最初期進行1次電阻測定即可,故可進一步縮短測定時間。 Further, depending on the state of the short-circuit defective portion or the like, the change rate Δr corresponding to the resistance value of the short-circuit defective portion can be detected even at the initial stage of the transition period, and in the resistance value measuring step, only The rate of change Δr of the indication value R is measured once at time t 01 , and the rate of change Δr from time 0 is obtained. In this case, since the resistance measurement is performed only once in the initial period of the transition period, the measurement time can be further shortened.

再者,亦可以定電流電源替換定電壓電源59。藉由閉合開關52,欲使連接於2根被測定配線之節點56與節點57之間流通定電流。若2根被測定配線間發生短路時,流通定電流。電阻測定部8測定節點56與節點57之間之電壓,將測定出之電壓值除以定電流值而求得電阻值。若2根被測定配線間未發生短路時,不流通電流,故而電阻值變為無限大。 Furthermore, the constant current source 59 can also be replaced by a constant current source. By closing the switch 52, a constant current is flowed between the node 56 connected to the two wires to be measured and the node 57. When a short circuit occurs between the two wires to be measured, a constant current flows. The resistance measuring unit 8 measures the voltage between the node 56 and the node 57, and divides the measured voltage value by the constant current value to obtain a resistance value. When there is no short circuit between the two tested wirings, no current flows, and the resistance value becomes infinite.

此處,假設為尚未進行電阻測定之狀態。即,開關52打開。圖5(a)中,電容器54與電阻53成為閉迴路,蓄積於電容器54中之電荷進行自然放電。另一方面,圖5(b)中,成為開迴路,蓄積於電容器54中之電荷並未放電。因此,無短路缺陷之良品之液晶面板並未進行自然放電,其受到其他配線間之電阻測定或靜電之影響較大,直至介電吸收收斂為止之時間較大地變動。 Here, it is assumed that the state of resistance measurement has not been performed. That is, the switch 52 is turned on. In FIG. 5(a), the capacitor 54 and the resistor 53 are closed, and the electric charge stored in the capacitor 54 is naturally discharged. On the other hand, in FIG. 5(b), the circuit is opened, and the electric charge accumulated in the capacitor 54 is not discharged. Therefore, the liquid crystal panel which does not have a short-circuit defect is not subjected to natural discharge, and is affected by resistance measurement or static electricity in other wirings, and the time until the dielectric absorption converges greatly changes.

圖9(a)~(c)中,作為一例,模式性地表示像素部17中所產生之配線之短路部即缺陷部23之位置。圖9(a)表示例如閘極線及源極線般配線X與配線Y交叉之液晶面板中,配線X與配線Y於該交叉部分發生短路之缺陷部23。將導通之探針21切換為圖3所示之21a與21d之組或21b與21c之組,對配線X1~X10及配線Y1~Y10以1對1地測定配線間之 電阻值,藉此可特定缺陷部23之有無與位置。 In (a) to (c) of FIG. 9 , as an example, the position of the defective portion 23 which is a short-circuit portion of the wiring generated in the pixel portion 17 is schematically shown. (a) of FIG. 9 shows a defect portion 23 in which the wiring X and the wiring Y are short-circuited at the intersection portion in the liquid crystal panel in which the gate line and the source line-like wiring X and the wiring Y intersect. Switching the conductive probe 21 to the group of 21a and 21d or the group of 21b and 21c shown in FIG. 3, and measuring the wiring between the wirings X1 to X10 and the wirings Y1 to Y10 in a one-to-one manner. The resistance value, whereby the presence or absence of the defective portion 23 and the position can be specified.

圖9(b)表示例如閘極線及Cs線般鄰接之配線X之配線間發生短路之缺陷部23。如此之短路部23藉由將導通之探針21切換為21b之奇數號與21d之偶數號之組,測定配線X1~X10之相鄰之配線間之電阻值,而可特定有缺陷部23之配線。 Fig. 9(b) shows a defect portion 23 in which a short circuit occurs between wirings of the wiring X adjacent to the gate line and the Cs line, for example. The short-circuit portion 23 is configured by switching the conductive probe 21 to the odd-numbered number of 21b and the even-numbered number of 21d, and measuring the resistance value between the adjacent wirings of the wirings X1 to X10, and the defective portion 23 can be specified. Wiring.

圖9(c)表示例如源極線及Cs線般鄰接之配線Y之配線間發生短路之缺陷部23。如此之缺陷部23藉由將導通之探針21切換為21a之奇數號與21c之偶數號之組,測定配線Y1~Y10之相鄰之配線間之電阻值,而可特定有缺陷部23之配線。 Fig. 9(c) shows a defect portion 23 in which a short circuit occurs between wirings of the wiring Y adjacent to the source line and the Cs line, for example. The defect portion 23 is configured to switch the conductive probe 21 to the group of the odd number of 21a and the even number of 21c, and measure the resistance value between the adjacent wirings of the wirings Y1 to Y10, and the defective portion 23 can be specified. Wiring.

步驟S6中,根據步驟S5中所檢查之缺陷部23之有無,判斷是否進行紅外線檢查。有缺陷部23之情形時,為進行紅外線檢查而移至步驟S7;無缺陷部23之情形時,不進行紅外線檢查而移至步驟S10。該步驟S6可稱作電阻值測定步驟之一部分。 In step S6, it is determined whether or not the infrared inspection is performed based on the presence or absence of the defective portion 23 inspected in step S5. In the case of the defective portion 23, the process proceeds to step S7 for the infrared ray inspection, and the non-defective portion 23 is not performed, and the process proceeds to step S10 without performing the infrared ray inspection. This step S6 can be referred to as part of the resistance value determination step.

例如,如圖9(a)所示,於配線X及配線Y交叉之部位產生缺陷部23時,因藉由配線間之電阻檢查,檢測出配線X4及配線Y4存在異常,故甚至可特定缺陷部23之位置。因此,於圖9(a)所示之缺陷部23之情形時,並不需要於步驟S7中利用紅外線檢查特定其位置。即,若係對配線X與配線Y之全部組合之每一組進行電阻檢查,則亦可特定位置,故而無需進行紅外線檢查。但,因組合數過於龐大故需較長時間。例如,於全高畫質用液晶面板之情形時,因配線X 為1080根,配線Y為1920根,故其全部組合為約207萬。若對如此之組合之每一組進行電阻檢查,則間歇時間變長,導致檢查處理能力大幅下降,而並不現實。因此,藉由將配線X與配線Y之全部組合歸總為若干後進行電阻檢查,可減少電阻檢查次數。例如,若於歸總為1個之配線X與歸總為1個之配線Y之間進行電阻檢查,則該電阻檢查次數僅為1次。然而,雖可利用電阻檢查檢測配線間之短路,但卻無法特定位置。因此,需利用紅外線檢查特定缺陷部23之位置。 For example, as shown in FIG. 9(a), when the defective portion 23 is formed in the portion where the wiring X and the wiring Y intersect, the wiring X4 and the wiring Y4 are detected to have abnormalities due to the resistance check between the wirings, so that a specific defect can be specified. The position of the department 23. Therefore, in the case of the defective portion 23 shown in Fig. 9(a), it is not necessary to use the infrared ray inspection to specify its position in the step S7. In other words, if each group of the combination of the wiring X and the wiring Y is subjected to the resistance inspection, the position can be specified, so that it is not necessary to perform the infrared inspection. However, it takes a long time because the number of combinations is too large. For example, in the case of a full-height LCD panel, due to wiring X For 1080, the wiring Y is 1920, so the total combination is about 2.07 million. If the resistance check is performed for each of such a combination, the intermittent time becomes long, and the inspection processing ability is drastically lowered, which is not realistic. Therefore, the resistance check can be reduced by totaling all the combinations of the wiring X and the wiring Y and performing resistance inspection. For example, if the resistance check is performed between the wiring X having one total and the wiring Y having one total, the number of times of the resistance inspection is only one. However, although a short circuit between wirings can be detected by a resistance check, a specific position cannot be obtained. Therefore, it is necessary to check the position of the specific defect portion 23 by using infrared rays.

另一方面,於如圖9(b)或圖9(c)般,鄰接之配線間產生缺陷部23時,可特定出一對配線例如配線X3與配線X4之間有缺陷部。但,於該配線之長度方向上缺陷部23之位置無法特定,故而需利用紅外線檢查特定缺陷部23之位置。 On the other hand, when the defective portion 23 is formed between the adjacent wiring lines as shown in FIG. 9(b) or FIG. 9(c), a pair of wirings such as a defective portion between the wiring X3 and the wiring X4 can be specified. However, since the position of the defective portion 23 is not specified in the longitudinal direction of the wiring, it is necessary to inspect the position of the specific defective portion 23 by infrared rays.

因相鄰之配線間之電阻檢查為龐大之數故需較長時間。例如,全高畫質用液晶面板之情形時,相鄰之配線X間之電阻檢查次數為1079、相鄰之配線Y間之電阻檢查次數為1919。如圖9(b)之情形般之相鄰之配線X間之電阻檢查之情形時,若於全部X奇數號與全部X偶數號之間進行電阻檢查,則該電阻檢查次數僅為1次。如圖9(c)之情形般之相鄰之配線Y間之電阻檢查之情形時,若於全部Y奇數號與全部Y偶數號之間進行電阻檢查,則該電阻檢查次數僅為1次。然而,雖可利用電阻檢查檢測配線間之短路,但無法特定位置。因此,需利用紅外線檢查特定缺陷部23之位置。因此,步驟S6中,就判斷為需進行紅外線檢查之液晶 面板2進行紅外線檢查。 It takes a long time because the resistance check of the adjacent wiring closets is a large number. For example, in the case of a liquid crystal panel for full-height image quality, the number of resistance inspections between adjacent wirings X is 1079, and the number of resistance inspections between adjacent wirings Y is 1919. In the case of the resistance check between the adjacent wirings X as in the case of Fig. 9(b), if the resistance check is performed between all the X odd numbers and all the X even numbers, the number of times of the resistance check is only one. In the case of the resistance check between the adjacent wires Y as in the case of Fig. 9(c), if the resistance check is performed between all the Y odd numbers and all the Y even numbers, the number of times of the resistance check is only one. However, although the short circuit between the wirings can be detected by the resistance check, the position cannot be specified. Therefore, it is necessary to check the position of the specific defect portion 23 by using infrared rays. Therefore, in step S6, it is determined that the liquid crystal needs to be inspected by infrared rays. Panel 2 performs an infrared inspection.

步驟S8中,為檢測來自藉由施加上述電壓而產生電流並發熱之缺陷部23之紅外光,使用紅外線相機攝影缺陷部23,而特定缺陷部23之位置。本實施形態中包含宏觀計測用之紅外線相機5a與微觀計測用之紅外線相機5b,首先,利用可將液晶面板2之較廣範圍收納於視野內之宏觀計測用之紅外線相機5a,根據需要掃描宏觀計測用之紅外線相機5a,而特定缺陷部23之位置。繼而,亦可根據需要使用微觀計測用之紅外線相機5b計測發熱部之附近。因利用宏觀計測用之紅外線相機5a特定出發熱部之位置,故可以使發熱部位於微觀計測用之紅外線相機5b之視野內之方式移動相機,而高精度地特定缺陷部23之座標位置,或進行關於修正所需之形狀等之資訊之計測。再者,本實施形態中係包含宏觀計測用之紅外線相機5a與微觀計測用之紅外線相機5b以2個階段進行攝影,但本發明並非限定於此,亦可為利用1個紅外線相機以1個階段進行攝影之構成。 In step S8, in order to detect the infrared light from the defective portion 23 which generates a current by the application of the voltage and generates heat, the defect portion 23 is photographed by the infrared camera, and the position of the defective portion 23 is specified. In the present embodiment, the infrared camera 5a for macro measurement and the infrared camera 5b for microscopic measurement are included. First, the infrared camera 5a for macro measurement, which can accommodate a wide range of the liquid crystal panel 2 in the field of view, is scanned as needed. The position of the specific defect portion 23 is measured by the infrared camera 5a. Then, the vicinity of the heat generating portion can be measured using the infrared camera 5b for microscopic measurement as needed. Since the position of the heat generating portion is specified by the infrared camera 5a for macro measurement, the camera can be moved so that the heat generating portion is positioned in the field of view of the infrared camera 5b for microscopic measurement, and the coordinate position of the defective portion 23 can be specified with high precision, or Perform measurement on the information such as the shape required for correction. In the present embodiment, the infrared camera 5a for macro measurement and the infrared camera 5b for microscopic measurement are imaged in two stages. However, the present invention is not limited thereto, and one infrared camera may be used. The stage is the composition of photography.

又,圖2之光學相機16係由圖1之主控制部7控制,用於將微觀計測用之紅外線相機5b所偵測出之短路缺陷作為可視圖像予以攝影。或,亦可設為兼用作光學相機16與上述雷射照射裝置之同軸光學單元。 Further, the optical camera 16 of Fig. 2 is controlled by the main control unit 7 of Fig. 1 for photographing the short-circuit defect detected by the infrared camera 5b for microscopic measurement as a visible image. Alternatively, it may be a coaxial optical unit that also serves as the optical camera 16 and the above-described laser irradiation device.

步驟S9中,就檢查中之液晶面板2,判斷各種缺陷模式之所有檢查是否完畢,於存在未檢查之缺陷模式時,返回步驟S3。並且,使測定對象之全部端子預短路後,重複進行缺陷檢查。此處,所謂缺陷模式係如圖9所示之缺陷部 23之種類。圖9中表示有3種缺陷模式。即,圖9(a)之配線X與配線Y之短路缺陷模式、圖9(b)之配線X間之短路缺陷模式、圖9(c)之配線Y間之短路缺陷模式。 In step S9, it is judged whether or not all the inspections of the various defect modes are completed in the liquid crystal panel 2 under inspection, and when there is an unchecked defect mode, the process returns to step S3. Then, after all the terminals of the measurement target are pre-short-circuited, the defect inspection is repeated. Here, the defect mode is the defect part shown in FIG. 23 types. There are three defect modes shown in FIG. That is, the short-circuit defect mode of the wiring X and the wiring Y of FIG. 9(a), the short-circuit defect mode between the wirings X of FIG. 9(b), and the short-circuit defect mode between the wirings Y of FIG. 9(c).

步驟S10中,針對檢查中之母基板1,判斷所有液晶面板2之缺陷檢查是否完畢,若有剩下未檢查之液晶面板2,返回步驟S2。並且,將探針移動至成為下一檢查對象之液晶面板2,重複進行缺陷檢查。 In step S10, it is judged whether or not the defect inspection of all the liquid crystal panels 2 is completed for the mother substrate 1 under inspection, and if there is any unchecked liquid crystal panel 2, the process returns to step S2. Then, the probe is moved to the liquid crystal panel 2 which is the next inspection target, and the defect inspection is repeated.

圖10係表示與使用圖9所說明之3種缺陷模式對應之繼電器之接線的圖。電阻測定器415為電阻測定部8之一部分,其測定電阻。電源416為電壓施加部9之一部分,其對液晶面板2之配線或配線間施加電壓。圖10之虛線所包圍之虛線區塊401、404、407、410表示探針21a~21d。虛線區塊401表示連接於奇數號配線X之端子部之探針、虛線區塊404表示連接於偶數號配線X之端子部之探針、虛線區塊407表示連接於奇數號配線Y之端子部之探針、虛線區塊410表示連接於偶數號配線Y之端子部之探針。虛線區塊402、403、405、406、408、409、411、412、413、414表示繼電器。虛線區塊402、403係與虛線區塊401對應之繼電器;同樣地,虛線區塊405、406係與虛線區塊404對應之繼電器;虛線區塊408、409係與虛線區塊407對應之繼電器;虛線區塊411、412係與虛線區塊410對應之繼電器。以下,設虛線區塊N內之繼電器為繼電器N。例如,虛線區塊402內之繼電器為繼電器402。 Fig. 10 is a view showing the wiring of the relay corresponding to the three defect modes described using Fig. 9. The resistance measuring device 415 is a part of the resistance measuring unit 8, and measures resistance. The power source 416 is a portion of the voltage applying portion 9 that applies a voltage to the wiring or wiring of the liquid crystal panel 2. The dotted line blocks 401, 404, 407, and 410 surrounded by the broken line of Fig. 10 indicate the probes 21a to 21d. The dotted line block 401 indicates a probe connected to the terminal portion of the odd-numbered wiring X, the broken line block 404 indicates a probe connected to the terminal portion of the even-numbered wiring X, and the broken-line block 407 indicates a terminal portion connected to the odd-numbered wiring Y. The probe and the dotted line block 410 indicate probes connected to the terminal portions of the even-numbered wires Y. The dashed blocks 402, 403, 405, 406, 408, 409, 411, 412, 413, 414 represent relays. The dotted block 402, 403 is a relay corresponding to the dotted block 401; similarly, the dotted block 405, 406 is a relay corresponding to the broken block 404; the dotted block 408, 409 is a relay corresponding to the broken block 407 The dashed blocks 411, 412 are relays corresponding to the dashed block 410. Hereinafter, it is assumed that the relay in the dotted line block N is the relay N. For example, the relay within the dashed block 402 is the relay 402.

繼電器402、405、408、411經由繼電器413而連接於電 阻測定值415及電源416之正極性端子。繼電器403、406、409、412經由繼電器414而連接於電阻測定器415及電源416之負極性端子。繼電器413係連接於電阻測定器之端子之繼電器。繼電器414係連接於電源416之端子之繼電器。藉由切換該等複數個繼電器,可分別實施步驟S3中所示之短路處理、步驟S4中所示之電阻測定、及步驟S7中所示之電壓施加。 Relays 402, 405, 408, 411 are connected to electricity via relay 413 The measured value 415 and the positive terminal of the power source 416 are blocked. The relays 403, 406, 409, and 412 are connected to the negative polarity terminals of the resistance measuring device 415 and the power source 416 via the relay 414. Relay 413 is a relay that is connected to the terminals of the resistance measuring device. Relay 414 is a relay that is connected to the terminals of power source 416. By switching the plurality of relays, the short-circuit processing shown in step S3, the resistance measurement shown in step S4, and the voltage application shown in step S7 can be performed separately.

圖11係表示圖10中所示之各繼電器之開關的表格。在短路處理中,將虛線區塊401、404、407、410之各探針之連接全部閉合,使配線或配線間之全部端子短路。同時,將繼電器413、414全部打開,切離電阻測定器415及電源416。 Figure 11 is a table showing the switches of the relays shown in Figure 10. In the short-circuit processing, all the connections of the probes of the broken line blocks 401, 404, 407, and 410 are closed, and all the terminals of the wiring or wiring are short-circuited. At the same time, the relays 413, 414 are all turned on, and the resistance measuring device 415 and the power source 416 are cut away.

電阻測定及電壓施加中,根據缺陷模式而分別切換虛線區塊401、404、407、410之各探針之連接。例如,在如圖9(a)所示之配線X與配線Y之短路缺陷模式之電阻測定中,閉合繼電器402、405、409、412、413,打開繼電器403、406、408、411、414,將奇數及偶數之配線X連接於電阻測定器415之正極性端子,將奇數及偶數之配線Y連接於電阻測定器415之負極性端子。又,如圖9(a)所示,在配線X與配線Y之短路缺陷模式之電壓施加中,閉合繼電器402、405、409、412、414,打開繼電器403、406、408、411、413,將奇數及偶數之配線X連接於電源416之正極性端子,將奇數及偶數之配線Y連接於電源416之負極性端子。 In the resistance measurement and the voltage application, the connections of the probes of the broken line blocks 401, 404, 407, and 410 are switched in accordance with the defect mode. For example, in the resistance measurement of the short-circuit defect mode of the wiring X and the wiring Y as shown in FIG. 9(a), the relays 402, 405, 409, 412, and 413 are closed, and the relays 403, 406, 408, 411, and 414 are turned on. The odd and even wirings X are connected to the positive terminal of the resistance measuring device 415, and the odd and even wirings Y are connected to the negative terminal of the resistance measuring device 415. Further, as shown in FIG. 9(a), in the voltage application of the short-circuit defect mode of the wiring X and the wiring Y, the relays 402, 405, 409, 412, and 414 are closed, and the relays 403, 406, 408, 411, and 413 are turned on. The odd and even wirings X are connected to the positive terminal of the power supply 416, and the odd and even wirings Y are connected to the negative terminal of the power supply 416.

如此,藉由切換複數個繼電器,可變更液晶面板2之配 線與電阻測定器及電源之間之接線。再者,關於配線X、配線Y、Cs線、及預備配線之缺陷模式(例如Cs線間缺陷模式、配線X與Cs線之缺陷模式、配線Y與Cs線之缺陷模式、配線X與預備配線之缺陷模式、配線Y與預備配線之缺陷模式),亦可藉由適當追加繼電器,而實施短路處理、電阻測定、電壓施加。 Thus, by switching a plurality of relays, the matching of the liquid crystal panel 2 can be changed. Wiring between the wire and the resistance tester and the power supply. In addition, the defect pattern of the wiring X, the wiring Y, the Cs line, and the backup wiring (for example, the Cs line defect mode, the defect pattern of the wiring X and the Cs line, the defect mode of the wiring Y and the Cs line, the wiring X and the backup wiring) The defect mode, the wiring Y and the defect pattern of the backup wiring) may be subjected to short-circuit processing, resistance measurement, and voltage application by appropriately adding a relay.

根據本實施形態,於進行電阻檢查前,使檢查對象之端子短路,暫使端子間所充電之電荷成為0,一直自帶電為0之狀態進行電阻測定,藉此可使初期狀態為固定,抑制收斂時間之變動或偏差。利用端子間判斷有無缺陷,於判斷為有缺陷時取得液晶面板2之短路路徑之電阻值。進而,藉由對液晶面板2施加基於該電阻值所特定之電壓,使缺陷部23或配線部之任一者充分發熱,故而於紅外線檢查時可容易地識別缺陷之位置。 According to the present embodiment, before the resistance inspection, the terminals to be inspected are short-circuited, and the electric charge charged between the terminals is temporarily set to zero. The electric resistance is measured in a state where the charging is 0, whereby the initial state can be fixed and suppressed. Variation or deviation in convergence time. The presence or absence of a defect is determined between the terminals, and when it is determined that there is a defect, the resistance value of the short-circuit path of the liquid crystal panel 2 is obtained. Further, by applying a voltage specific to the resistance value to the liquid crystal panel 2, any one of the defective portion 23 or the wiring portion is sufficiently heated, so that the position of the defect can be easily recognized at the time of infrared inspection.

再者,本實施形態中係說明如下方法:於測定閘極線、源極線、Cs線之配線或配線間之電阻時,使閘極線、源極線、Cs線之配線或配線間之全部端子預短路後,例如進行閘極線與源極線之電阻測定,繼而再次使閘極線、源極線、Cs線之配線或配線間之全部端子預短路後,此次進行閘極線與Cs線之電阻測定,如上述般於每次將要進行電阻測定前使成為測定對象之全部端子預短路。於該方法之情形時,因每次使全部端子間短路並放電,故電容器之帶電相對於任一配線均一直為0,且因亦除去靜電,故測定時間之偏差極小而較為理想。然而,並非限定於該方法,例 如亦可為如下方法:如於測定閘極線與源極線之電阻前,僅使閘極線與源極線預短路而進行電阻測定等般,每次僅使測定對象之配線彼此預短路 In the present embodiment, a method is described in which the wiring of the gate line, the source line, the Cs line, or the wiring is made when measuring the resistance between the gate line, the source line, the Cs line wiring, or the wiring. After pre-short-circuiting all the terminals, for example, the resistance measurement of the gate line and the source line is performed, and then all the terminals of the gate line, the source line, the Cs line wiring or the wiring line are pre-short-circuited again, and then the gate line is performed this time. The resistance measurement with the Cs line is pre-short-circuited to all the terminals to be measured before the resistance measurement is performed as described above. In the case of this method, since all the terminals are short-circuited and discharged each time, the charging of the capacitor is always 0 with respect to any of the wirings, and since static electricity is also removed, the variation of the measurement time is extremely small, which is preferable. However, it is not limited to this method, for example For example, before the resistance of the gate line and the source line is measured, only the gate line and the source line are pre-short-circuited, and resistance measurement is performed, and only the wirings of the measurement target are pre-short-circuited each time.

再者,亦可於步驟S5或步驟S8中之至少一個步驟之後,進而實施使配線之端子間短路之步驟。結束步驟S5中所實施之電阻值測定後之短路步驟可將藉由步驟S5中所實施之電阻值測定而對液晶面板2充電之電荷放電。或,結束步驟S8中所實施之缺陷位置特定後之短路步驟可將藉由步驟S8中所實施之電壓施加而對液晶面板2充電之電荷放電。藉由該短路步驟,由配線缺陷檢查裝置100檢查後搬出裝置外之母基板1成為已放電之狀態。其結果,可防止母基板1之靜電破壞或顯示品質劣化等。 Furthermore, the step of short-circuiting the terminals of the wiring may be further performed after at least one of the steps S5 or S8. The short-circuiting step after the measurement of the resistance value performed in the step S5 is completed, and the electric charge charged to the liquid crystal panel 2 by the resistance value measurement performed in the step S5 can be discharged. Alternatively, the short-circuiting step after the defect position specified in the step S8 is terminated may discharge the electric charge charged to the liquid crystal panel 2 by the voltage application applied in the step S8. By the short-circuiting step, the wiring defect inspection apparatus 100 inspects the state in which the mother substrate 1 outside the unloading apparatus is discharged. As a result, it is possible to prevent electrostatic breakdown of the mother substrate 1 or deterioration in display quality.

<實施形態2> <Embodiment 2>

實施形態1中,已對如圖1所示般設置有攝影缺陷部23之紅外線相機5之構成進行了說明,但亦可為僅具備進行電阻測定而檢查有無缺陷之功能之構成。圖12係表示實施形態2之配線缺陷裝置200之構成的方塊圖。除未包含圖1所示之用於取得紅外線圖像之紅外線相機5、及使紅外線相機5於液晶面板2上移動之相機移動機構6以外,均與實施形態1之構成相同。 In the first embodiment, the configuration of the infrared camera 5 in which the photographic defect portion 23 is provided as shown in FIG. 1 has been described. However, the configuration may be such that only the resistance measurement is performed to check for the presence or absence of a defect. Fig. 12 is a block diagram showing the configuration of the wiring defect device 200 of the second embodiment. The configuration of the first embodiment is the same as that of the first embodiment except that the infrared camera 5 for obtaining an infrared image shown in FIG. 1 and the camera moving mechanism 6 for moving the infrared camera 5 on the liquid crystal panel 2 are not included.

圖13係使用實施形態2之配線缺陷檢查裝置200之配線缺陷檢查方法的流程圖。如圖13所示,本實施形態之配線缺陷檢查方法係藉由步驟S91~步驟S97之步驟,對形成於母基板1上之複數個液晶面板2依次實施配線缺陷檢查。 Fig. 13 is a flowchart showing a wiring defect inspection method using the wiring defect inspection device 200 of the second embodiment. As shown in FIG. 13, in the wiring defect inspection method of this embodiment, the wiring defect inspection is sequentially performed on the plurality of liquid crystal panels 2 formed on the mother substrate 1 by the steps S91 to S97.

首先,於步驟S91中,將母基板1載置於配線缺陷檢查裝置200之對準載物台11上,以與XY座標軸平行之方式調整基板之位置。繼而,於步驟S92中,利用探針移動機構4將探針3移動至成為檢查對象之液晶面板2之上部,使探針21a~21d與液晶面板2之端子部19a~19d接觸。此處,於步驟S93中,使成為測定對象之配線或配線間之全部端子預短路。 First, in step S91, the mother substrate 1 is placed on the alignment stage 11 of the wiring defect inspection device 200, and the position of the substrate is adjusted so as to be parallel to the XY coordinate axis. Then, in step S92, the probe moving mechanism 4 moves the probe 3 to the upper portion of the liquid crystal panel 2 to be inspected, and the probes 21a to 21d are brought into contact with the terminal portions 19a to 19d of the liquid crystal panel 2. Here, in step S93, all the terminals of the wiring to be measured or the wiring are pre-short-circuited.

其次,於步驟S94中,與各種缺陷模式對應地,選擇用於進行電阻檢查之配線或配線間,並進行導通之探針21之切換。於步驟S95中進行電阻檢查。步驟S95中,測定選出之配線或配線間之電阻值,藉由將該電阻值與無缺陷之情形時之電阻值進行比較,檢查有無缺陷。於步驟S96中,就檢查中之液晶面板2,判斷各種缺陷模式之所有檢查是否結束,於有未檢查之缺陷模式時,返回步驟S93。並且,使測定對象之全部端子預短路後,重複進行缺陷檢查。於步驟S97中,就檢查中之母基板1,判斷所有液晶面板2之缺陷檢查是否結束,若殘留未檢查之液晶面板2時,返回步驟S92。並且,將探針移動至成為下一檢查對象之液晶面板2,重複進行缺陷檢查。 Next, in step S94, in accordance with various defect modes, the wiring or the wiring for performing the resistance inspection is selected, and the probe 21 that is turned on is switched. A resistance check is performed in step S95. In step S95, the resistance value of the selected wiring or wiring is measured, and the resistance value is compared with the resistance value in the case of no defect, and the presence or absence of the defect is checked. In step S96, it is judged whether or not all the inspections of the various defect modes have been completed in the liquid crystal panel 2 under inspection, and when there is an unchecked defect mode, the flow returns to step S93. Then, after all the terminals of the measurement target are pre-short-circuited, the defect inspection is repeated. In step S97, the mother substrate 1 under inspection is judged whether or not the defect inspection of all the liquid crystal panels 2 is completed. If the unchecked liquid crystal panel 2 remains, the flow returns to step S92. Then, the probe is moved to the liquid crystal panel 2 which is the next inspection target, and the defect inspection is repeated.

藉由如此構成,因於其他裝置中實施電阻測定,故可並行進行電阻測定與紅外線相機攝像,而可提高處理能力。 According to this configuration, since the resistance measurement is performed in another device, the resistance measurement and the infrared camera imaging can be performed in parallel, and the processing capability can be improved.

<實施形態3> <Embodiment 3>

再者,本發明當然亦可藉由如下方式達成:將記錄有實現上述實施形態之功能之軟體之程式碼的記錄媒體供給至 其他系統或裝置,由該系統或裝置之電腦CPU讀出並執行儲存於紀錄媒體中之程式碼。 Furthermore, the present invention can of course be achieved by supplying a recording medium on which a program code for realizing the function of the above-described embodiment is recorded to Other systems or devices from which the computer CPU of the system or device reads and executes the code stored in the recording medium.

該情形時,自紀錄媒體讀出之程式碼自身實現上述實施形態之功能,記錄有該程式碼之紀錄媒體構成本發明。又,上述程式碼亦可為經由如通信網路般之傳輸媒體,自其他電腦系統下載至記錄裝置等者。 In this case, the program code read from the recording medium itself realizes the functions of the above embodiment, and the recording medium on which the code is recorded constitutes the present invention. Moreover, the above code may be downloaded to a recording device from another computer system via a transmission medium such as a communication network.

又,毋庸贅言,藉由電腦執行讀出之程式碼,不僅可實現上述實施形態之功能,亦包含基於該程式碼之指示,由電腦上運行之OS(Operating System,作業系統)等進行一部分或全部之實際處理,藉由該處理而實現上述實施形態之功能之情形。 Moreover, it goes without saying that the function of the above-described embodiment can be realized not only by the execution of the code read by the computer, but also by an OS (Operating System) running on the computer or the like based on the instruction of the code. All of the actual processing, by the processing, realizes the function of the above embodiment.

進而,毋庸贅言,亦包含如下情形:將自紀錄媒體讀出之程式碼寫入至插入電腦中之功能擴充板或連接於電腦之功能擴充單元所具備之記憶體後,基於該程式碼之指示,由該功能擴充板或功能擴充單元所具備之CPU等進行一部分或全部之實際處理,藉由該處理而實現上述實施形態之功能。 Further, it goes without saying that the program code read from the recording medium is written to the memory of the function expansion board inserted in the computer or the function expansion unit connected to the computer, based on the instruction of the code. The CPU or the like provided in the function expansion board or the function expansion unit performs some or all of the actual processing, and the functions of the above-described embodiments are realized by the processing.

將本發明應用於上述紀錄媒體之情形時,於該紀錄媒體中儲存與之前說明之流程對應之程式碼。 When the present invention is applied to the above-described recording medium, the program code corresponding to the previously described flow is stored in the recording medium.

以上,已就本發明之實施形態進行了說明,但本發明並非限定於上述實施形態者。於本請求項所示之範圍內可進行各種變更,適當組合不同之實施形態所分別揭示之技術手段所得之實施形態亦包含於本發明之技術範圍內。 Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. Various modifications may be made without departing from the spirit and scope of the invention as described in the appended claims.

(本發明之總結) (summary of the invention)

本發明之配線缺陷檢查方法之特徵在於:其係進行半導體基板之配線短路部之檢測者,且進行如下步驟:預短路步驟,其係使檢查對象之配線之端子間短路;及電阻值測定步驟,其係於上述預短路步驟之後測定上述檢查對象之配線之電阻值,藉此判定有無上述配線短路部。 The wiring defect inspection method according to the present invention is characterized in that the detection of the short-circuit portion of the wiring of the semiconductor substrate is performed as follows: a pre-short step of short-circuiting between the terminals of the wiring to be inspected; and a resistance value measuring step After the pre-short step, the resistance value of the wiring to be inspected is measured to determine the presence or absence of the wiring short-circuit portion.

又,上述預短路步驟亦可以使檢查對象之全部端子間短路為特徵。又,上述電阻值測定步驟中,亦可以於上述配線之電阻測定器之指示值穩定前決定上述電阻值為特徵。又,上述電阻值測定步驟中,亦可以根據上述指示值之變化率決定上述電阻值為特徵。又,上述電阻值測定步驟中,亦可以藉由測定出之上述指示值與自測定開始起算之測定時間而算出上述變化率為特徵,或亦可以自不同時間之上述指示值算出上述變化率為特徵。又,上述電阻值測定步驟亦可以於上述變化率小於特定值時判定為有上述配線短路部為特徵。進而,亦可以包括以下步驟為特徵:發熱步驟,其係對上述電阻值測定步驟中判定為有上述配線短路部之上述半導體基板之包含該配線短路部之短路路徑施加電壓,使該短路路徑發熱;及位置特定步驟,其係利用紅外線攝像上述發熱步驟中發熱之短路路徑,而特定上述配線短路部之位置。又,亦可以包括於上述電阻值測定步驟或位置特定步驟中之至少一個步驟之後使配線之端子間短路之步驟為特徵。 Further, the pre-short step may be characterized by short-circuiting all the terminals of the inspection object. Further, in the resistance value measuring step, the resistance value may be determined before the indication value of the resistance measuring device of the wiring is stabilized. Further, in the resistance value measuring step, the resistance value may be determined based on a rate of change of the indication value. Further, in the resistance value measuring step, the change rate may be calculated by measuring the measured value and the measurement time from the start of the measurement, or the rate of change may be calculated from the indicated value at different times. feature. Further, the resistance value measuring step may be characterized in that the wiring short-circuit portion is determined when the change rate is less than a specific value. Furthermore, the step of generating a voltage for applying a voltage to the short-circuit path including the short-circuit portion of the semiconductor substrate in the resistance-measurement step determined to have the wiring short-circuit portion, and causing the short-circuit path to be generated And a position-specific step of specifying the position of the short-circuit portion of the wiring by infrared imaging of a short-circuit path of heat generated in the heat-generating step. Further, it may be characterized by a step of short-circuiting the terminals of the wiring after at least one of the resistance value measuring step or the position specifying step.

本發明之配線缺陷檢查裝置之特徵在於:其係進行半導體基板之配線短路部之檢測者,且包含:預短路部,其使 檢查對象之配線之端子間短路;電壓施加部,其對上述檢查對象之配線施加電壓;電阻測定部,其測定上述配線之電阻值;及控制部,其控制上述電壓施加部;且基於藉由上述電阻測定部所測定之電阻值,判定有無上述配線短路部。又,上述配線缺陷檢查裝置亦可以進而包含攝像部為特徵。 A wiring defect inspection device according to the present invention is characterized in that it is a detector for detecting a short-circuit portion of a semiconductor substrate, and includes a pre-short circuit portion a voltage between the terminals of the inspection target; a voltage application unit that applies a voltage to the wiring of the inspection target; a resistance measurement unit that measures a resistance value of the wiring; and a control unit that controls the voltage application unit; The resistance value measured by the resistance measuring unit determines whether or not the wiring short-circuit portion is present. Further, the wiring defect inspection device may further include an imaging unit.

本發明之配線缺陷檢查程式之特徵在於:其係使上述配線缺陷檢查裝置進行動作者,且將電腦作為上述各機構而發揮功能。 The wiring defect inspection program according to the present invention is characterized in that the wiring defect inspection device is operated by an operator and the computer functions as the above-described respective mechanisms.

本發明之配線缺陷檢查程式紀錄媒體之特徵在於:記錄有上述之配線缺陷檢查程式。 The wiring defect inspection program recording medium of the present invention is characterized in that the wiring defect inspection program described above is recorded.

[產業上之可利用性] [Industrial availability]

本發明可用於檢查液晶面板等之具有配線之半導體基板之配線狀態。 The present invention can be used to inspect a wiring state of a semiconductor substrate having wiring such as a liquid crystal panel.

1‧‧‧母基板 1‧‧‧ mother substrate

2‧‧‧液晶面板 2‧‧‧LCD panel

3‧‧‧探針 3‧‧‧ probe

4‧‧‧探針移動機構 4‧‧‧Probe moving mechanism

5a‧‧‧紅外線相機 5a‧‧‧Infrared camera

5b‧‧‧紅外線相機 5b‧‧‧Infrared camera

6‧‧‧相機移動機構 6‧‧‧ Camera moving mechanism

7‧‧‧主控制部 7‧‧‧Main Control Department

8‧‧‧電阻測定部 8‧‧‧Resistance Measurement Department

9‧‧‧電壓施加部 9‧‧‧Voltage application department

10‧‧‧預短路部 10‧‧‧Pre-short circuit

11‧‧‧對準載物台 11‧‧‧Aligning the stage

12‧‧‧光學相機 12‧‧‧Optical camera

13a‧‧‧導軌 13a‧‧‧rail

13b‧‧‧導軌 13b‧‧‧rail

13c‧‧‧導軌 13c‧‧‧rail

13d‧‧‧導軌 13d‧‧‧rails

13e‧‧‧導軌 13e‧‧‧rail

13f‧‧‧導軌 13f‧‧‧rail

14a‧‧‧安裝部 14a‧‧‧Installation Department

14b‧‧‧安裝部 14b‧‧‧Installation Department

14c‧‧‧安裝部 14c‧‧‧Installation Department

14d‧‧‧安裝部 14d‧‧‧Installation Department

16‧‧‧光學相機 16‧‧‧Optical camera

17‧‧‧像素部 17‧‧‧Pixel Department

18‧‧‧周邊配線部 18‧‧‧Circuit wiring department

19a‧‧‧端子部 19a‧‧‧Terminal Department

19b‧‧‧端子部 19b‧‧‧Terminal Department

19c‧‧‧端子部 19c‧‧‧Terminal Department

19d‧‧‧端子部 19d‧‧‧Terminal Department

21a‧‧‧探針部 21a‧‧‧Probe Department

21b‧‧‧探針部 21b‧‧‧Probe Department

21c‧‧‧探針部 21c‧‧‧ Probe Department

21d‧‧‧探針部 21d‧‧‧ Probe Department

23‧‧‧缺陷部(配線短路部) 23‧‧‧Defects (wiring short circuit)

51‧‧‧開關 51‧‧‧ switch

52‧‧‧開關 52‧‧‧ switch

53‧‧‧電阻 53‧‧‧resistance

54‧‧‧電容器 54‧‧‧ capacitor

55‧‧‧電阻 55‧‧‧resistance

56‧‧‧節點 56‧‧‧ nodes

57‧‧‧節點 57‧‧‧ nodes

59‧‧‧定電壓電源 59‧‧‧ Constant voltage power supply

100‧‧‧配線缺陷檢查裝置 100‧‧‧Wiring defect inspection device

415‧‧‧電阻測定器 415‧‧‧resistance tester

416‧‧‧電源 416‧‧‧Power supply

P1~P8‧‧‧液晶面板 P1~P8‧‧‧ LCD panel

圖1(a)、(b)係表示本發明之實施形態1之配線缺陷檢查裝置之構成的方塊圖與表示具有液晶面板之母基板之構成的立體圖。 1 (a) and (b) are a block diagram showing a configuration of a wiring defect inspection device according to a first embodiment of the present invention, and a perspective view showing a configuration of a mother substrate having a liquid crystal panel.

圖2係表示上述配線缺陷檢查裝置之構成的立體圖。 Fig. 2 is a perspective view showing the configuration of the wiring defect inspection device.

圖3(a)、(b)係本發明之實施形態中所使用之液晶面板及探針的俯視圖。 3(a) and 3(b) are plan views of a liquid crystal panel and a probe used in the embodiment of the present invention.

圖4係表示本發明之實施形態1之配線缺陷檢查方法的流程圖。 Fig. 4 is a flow chart showing a method of inspecting a wiring defect according to the first embodiment of the present invention.

圖5(a)、(b)係以等效電路表示本發明之實施形態者。 5(a) and 5(b) show an embodiment of the present invention in an equivalent circuit.

圖6(a)、(b)、(c)係說明本發明之實施形態之經過時間與電流值的圖。 6(a), (b) and (c) are diagrams showing the elapsed time and current values in the embodiment of the present invention.

圖7係說明本發明之實施形態之電阻值測定步驟的圖。 Fig. 7 is a view for explaining a resistance value measuring step in the embodiment of the present invention.

圖8係表示本發明之實施形態之電阻值測定步驟中所使用之變化率與電阻值之關係的圖。 Fig. 8 is a graph showing the relationship between the rate of change and the resistance value used in the resistance value measuring step in the embodiment of the present invention.

圖9(a)、(b)、(c)係表示本發明之實施形態中所使用之像素部之缺陷的模式圖。 Figs. 9(a), (b) and (c) are schematic views showing defects of a pixel portion used in the embodiment of the present invention.

圖10係說明本發明之實施形態1之與3個缺陷模式對應之繼電器之接線的圖。 Fig. 10 is a view for explaining the wiring of the relay corresponding to the three defect modes in the first embodiment of the present invention.

圖11係表示本發明之實施形態1之繼電器之開關的表格。 Fig. 11 is a table showing a switch of a relay according to the first embodiment of the present invention.

圖12係表示本發明之實施形態2之配線缺陷檢查裝置之構成的方塊圖。 Fig. 12 is a block diagram showing the configuration of a wiring defect inspection device according to a second embodiment of the present invention.

圖13係表示本發明之實施形態2之配線缺陷檢查方法的流程圖。 Fig. 13 is a flow chart showing a method of inspecting a wiring defect according to the second embodiment of the present invention.

圖14係說明先前之配線缺陷檢測方法的圖。 Fig. 14 is a view for explaining a prior art wiring defect detecting method.

圖15係說明先前之配線缺陷檢測方法的圖。 Fig. 15 is a view for explaining a prior art wiring defect detecting method.

1‧‧‧母基板 1‧‧‧ mother substrate

2‧‧‧液晶面板 2‧‧‧LCD panel

3‧‧‧探針 3‧‧‧ probe

4‧‧‧探針移動機構 4‧‧‧Probe moving mechanism

5‧‧‧紅外線相機 5‧‧‧Infrared camera

6‧‧‧相機移動機構 6‧‧‧ Camera moving mechanism

7‧‧‧主控制部 7‧‧‧Main Control Department

8‧‧‧電阻測定部 8‧‧‧Resistance Measurement Department

9‧‧‧電壓施加部 9‧‧‧Voltage application department

10‧‧‧預短路部 10‧‧‧Pre-short circuit

100‧‧‧配線缺陷檢查裝置 100‧‧‧Wiring defect inspection device

P1~P8‧‧‧液晶面板 P1~P8‧‧‧ LCD panel

Claims (6)

一種配線缺陷檢查方法,其特徵在於:其係進行半導體基板中之配線短路部之檢測者,且進行如下步驟:預短路步驟,其係使檢查對象之配線之端子間短路;及電阻值測定步驟,其係於上述預短路步驟之後測定上述檢查對象之配線之電阻值,藉此判定有無上述配線短路部。 A method for inspecting a wiring defect, characterized in that it is a method of detecting a short-circuit portion of a wiring in a semiconductor substrate, and performing a pre-shorting step of short-circuiting between terminals of a wiring to be inspected; and a resistance value measuring step After the pre-short step, the resistance value of the wiring to be inspected is measured to determine the presence or absence of the wiring short-circuit portion. 如請求項1之配線缺陷檢查方法,其中上述預短路步驟係使檢查對象之全部端子間短路。 The wiring defect inspection method of claim 1, wherein the pre-short circuit step short-circuits all of the terminals of the inspection object. 如請求項1或2之配線缺陷檢查方法,其中於上述電阻值測定步驟中,根據上述指示值之變化率決定上述電阻值。 The wiring defect inspection method according to claim 1 or 2, wherein in the resistance value measuring step, the resistance value is determined based on a rate of change of the indication value. 如請求項1之配線缺陷檢查方法,其包括:發熱步驟,其係對上述電阻值測定步驟中判定為有上述配線短路部之上述半導體基板之包含該配線短路部之短路路徑施加電壓,使該短路路徑發熱;及位置特定步驟,其係利用紅外線拍攝上述發熱步驟中發熱之短路路徑,而特定上述配線短路部之位置。 The wiring defect inspection method of claim 1, comprising: a heat generating step of applying a voltage to a short-circuit path including the wiring short-circuit portion of the semiconductor substrate having the wiring short-circuit portion in the resistance value measuring step; The short-circuit path generates heat; and the position-specific step of photographing the short-circuit path of the heat generation in the heat-generating step by infrared rays, and specifying the position of the short-circuit portion of the wiring. 如請求項4之配線缺陷檢查方法,其包括於上述電阻值測定步驟或位置特定步驟中之至少一個步驟之後使配線之端子間短路之步驟。 The wiring defect inspection method of claim 4, comprising the step of short-circuiting the terminals of the wiring after at least one of the resistance value measuring step or the position specifying step. 一種配線缺陷檢查裝置,其特徵在於:其係進行半導體基板中之配線短路部之檢測者,且包含: 預短路部,其使檢查對象之配線之端子間短路;電壓施加部,其對上述檢查對象之配線施加電壓;電阻測定部,其測定上述配線之電阻值;及控制部,其控制上述電壓施加部;且基於藉由上述電阻測定部所測定之電阻值,判定有無上述配線短路部。 A wiring defect inspection device characterized in that it is a detector for a short-circuit portion of a wiring in a semiconductor substrate, and includes: a short-circuiting portion that short-circuits between terminals of the wiring to be inspected, a voltage applying portion that applies a voltage to the wiring to be inspected, a resistance measuring portion that measures a resistance value of the wiring, and a control portion that controls the voltage application And determining whether or not the wiring short-circuit portion is present based on a resistance value measured by the resistance measuring unit.
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