JP2013108826A - Semiconductor substrate inspection method, wiring defect inspection program, and wiring defect inspection program recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring defect inspection method, a wiring defect inspection program, and a wiring defect inspection program recording medium which allow measurement time to be reduced and allow defects to be inspected accurately and efficiently in an appropriate measurement time when detecting defects of a semiconductor substrate such as a TFT array substrate.SOLUTION: In a wiring defect inspection method, a short-circuit part between plural kinds of wirings of a semiconductor substrate is detected by measuring a resistance value with voltage applied between the wirings. Detection of the short-circuit part is performed by measuring the resistance value with voltage applied between two kinds of the wirings, and measurement of the resistance value is performed by determining the order of application between the plural kinds of wirings and applying voltage between the wirings so as to shorten a measurement time.

Description

    The present invention relates to an inspection method, an inspection program, and an inspection program recording medium for inspecting a semiconductor substrate.

  Generally, in a liquid crystal panel manufacturing process, a liquid crystal panel is manufactured through a TFT array process, a cell process, a module process, and the like. Among these, in the TFT array process, a plurality of gate lines functioning as TFT scanning lines are arranged in parallel on a transparent substrate, and a plurality of auxiliary capacitance lines (hereinafter referred to as Cs lines). A plurality of source lines, which are arranged in parallel to the gate lines and further function as signal lines, are arranged perpendicular to the gate lines and covered with a protective film, and then a transparent electrode is formed. Thereafter, an array inspection is performed, and the presence or absence of a short circuit of the electrode or the wiring is inspected.

  Patent Document 1 discloses a method in which a short circuit between a plurality of types of wirings arranged on a substrate is detected by electrical inspection, and when a short circuit is detected, an infrared inspection is performed to identify a short circuit position. It is disclosed. In the electrical inspection disclosed in Patent Document 1, a voltage is applied between wires and a short circuit is determined based on resistance value measurement.

Japanese Patent Laid-Open No. 2-64594 (published on March 5, 1990)

  However, in the method of measuring resistance between a plurality of types of wirings arranged on a substrate and inspecting a short circuit between the wirings as shown in Patent Document 1, the measured value is measured after starting resistance measurement. It takes time to fluctuate and converge stably. This is due to the presence of a capacitance component that is not intended by the designer, i.e., stray capacitance, generated by the physical structure of the electronic component or electronic circuit.

  For example, FIG. 15 shows a general equivalent circuit in the case of resistance measurement. The stray capacitance is described as corresponding to the charge capacitance value of the capacitor 1502. The resistance value of the resistor 1501 is a resistance component connected in parallel with the capacitor 1502. The resistance value of the resistor 1505 is a resistance component connected in series with the capacitor 1502. Here, the total value of the electric resistances of the resistor 1501 and the resistor 1505 is measured. As a result, electrostatic capacity is generated via adjacent wirings on the substrate or an insulating layer between the wirings, which affects the resistance measurement operation.

  Specifically, in FIG. 15, when the switch 1503 is closed and the power supply 1504 applies a voltage to start resistance measurement, a stray capacitance is present immediately after the switch 1503 is closed, so that the apparent value is obtained regardless of the resistance value of the resistor 1501. Current flows as if the nodes 1506 and 1507 at both ends of the upper capacitor 1502 are short-circuited. First, a current flows through the capacitor 1502, then a current flows through the capacitor 1502 and the resistor 1501, and when the capacitor 1502 is charged, a current flows only through the resistor 1501. After charging of the capacitor 1502, the total value of the electric resistances of the resistor 1501 and the resistor 1505 can be accurately measured.

  Further, the capacitor 1502 may be somewhat charged in advance due to resistance measurement between other wirings or static electricity. For example, when the precharged direction is opposite to the polarity of the power supply 1504, that is, when the node 1507 has a higher potential than the node 1506, the node 1507 has a lower potential than the node 1506. As a result, it takes a long time until the capacitor 1502 is completely charged, which leads to a decrease in inspection efficiency.

  The present invention has been made in view of the above-mentioned problems, and its purpose is to shorten the measurement time and detect accurately and efficiently in a suitable measurement time in detecting a defect of a semiconductor substrate such as a TFT array substrate. An object is to provide a wiring defect inspection method, a wiring defect inspection program, and a wiring defect inspection program recording medium capable of inspecting defects.

  A wiring defect inspection method according to the present invention is a wiring defect inspection method for measuring a resistance value by applying a voltage between wirings to detect a short circuit between a plurality of types of wirings of a semiconductor substrate. The detection is performed by applying a voltage between the two types of wiring and measuring the resistance value. The order of application between the plurality of types of wiring is determined, and the voltage is applied between the wirings. The resistance value is measured so that the measurement time is shortened.

  Further, as the plurality of types of wiring, the first type wiring, the second type wiring having a lower rank than the first type wiring, and the third type wiring having a lower rank than the second type terminal portion. A first step of measuring a resistance value between the first type wiring and the second type wiring; and between the second type wiring and the third type wiring. After the second step of measuring the resistance value of the first type and the second type of step, the third type of measuring the resistance value between the first type of wiring and the third type of wiring Steps may be included.

  Furthermore, the wiring defect inspection method according to the present invention may include an infrared inspection step of identifying a defective portion by detecting temperature or infrared rays.

  An inspection program according to the present invention is an inspection program for operating the wiring defect inspection method described above, and causes a computer to function as each step described above.

  The inspection recording program described above is recorded on the program recording medium according to the present invention.

  According to the present invention, in the defect detection of a semiconductor substrate such as a TFT array substrate, the measurement time can be shortened, and the defect can be inspected accurately and efficiently in an appropriate measurement time. A program and a wiring defect inspection program recording medium can be provided.

It is a block diagram for demonstrating the main structures of the test | inspection apparatus in this invention. It is the figure which showed the wiring of the TFT substrate typically. It is a figure showing the step of the wiring defect inspection method which concerns on one embodiment of this invention. In Example 1, it is the figure which showed the equivalent circuit before a voltage application part and a resistance measuring device are connected to each pad. In Example 1, it is a figure for demonstrating a mode that a voltage application part and a resistance measuring device are connected between a source pad and a gate pad. In Example 1, it is the figure showing the relationship between time passage after a voltage application part and a resistance measuring device were connected between the source pad and the gate pad, and resistance value. In Example 1, it is a figure for demonstrating a mode that a voltage application part and a resistance measuring device are connected between a gate pad and Cs pad. In Example 1, it is a figure for demonstrating a mode that a voltage application part and a resistance measuring device are connected between a source pad and Cs pad. In Example 1, it is the figure showing the time passage after a voltage application part and a resistance measuring device were connected between a source pad and a Cs pad, and an example of each electric potential. In Example 2, it is the figure which showed the equivalent circuit before a voltage application part and a resistance measuring device are connected to each pad. In Example 2, it is a figure for demonstrating a mode that a voltage application part and a resistance measuring device are connected between a source pad and a gate pad. In Example 2, it is the figure showing the mode of the circuit after removing the voltage application part and resistance measuring instrument which were connected between the source pad and the gate pad. In Example 2, it is a figure for demonstrating a mode that a voltage application part and a resistance measuring device are connected between a gate pad and Cs pad. In Example 2, it is a figure for demonstrating a mode that a voltage application part and a resistance measuring device are connected between a source pad and Cs pad. It is a figure explaining the conventional wiring defect detection method.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a main configuration of a defect inspection apparatus 100 according to the present embodiment. The defect inspection apparatus 100 detects a short-circuit defect such as wiring of a plurality of TFT substrates 2 formed on the mother substrate 1. The defect inspection apparatus 100 includes a probe 3, a probe moving unit 4, an infrared camera 5, a camera moving unit 6, a control unit 7, a voltage application unit 8, a resistance measuring device 9, and a storage unit 10. The probe 3 is a short needle that electrically connects the voltage application unit 8 and the resistance measuring device 9 to the wiring of the TFT substrate 2. The probe moving unit 4 and the camera moving unit 6 are mechanisms for moving the probe 3 and the infrared camera 5 onto the respective TFT substrates 2. The voltage application unit 8 applies a voltage to the wiring of the TFT substrate 2 through the probe 3. The resistance measuring device 9 measures a resistance value between the wirings of the liquid crystal panel 2 by measuring a current value generated by a voltage applied to the wirings.

  The control unit 7 determines whether or not there is a short circuit in the wiring by comparing the measured resistance value with a normal resistance value stored in advance in the storage unit 10. The normal resistance value is a threshold value for determining whether or not there is a short circuit defect. A resistance value measured between wirings without a short circuit is called an insulation resistance, and is a large value of several hundred MΩ or more. Therefore, this several hundred MΩ or more may be stored as a normal resistance value. Further, when the measured resistance value is lower than this insulation resistance, that is, even when the wiring is slightly short-circuited, if there is no problem in the quality of the substrate, it may be determined that there is no short-circuit defect. Therefore, in this case, the normal resistance value is smaller than several hundred MΩ, for example, 100 kΩ. When the control unit 7 determines that a short circuit defect has occurred, the voltage application unit 8 applies a voltage between the wirings in which the short circuit has occurred to generate heat, and the infrared camera 5 causes the TFT to generate heat. By taking an infrared image of the substrate 2, it is possible to specify in detail the position of the short-circuit defect portion that has generated heat. The storage unit 10 is connected to the control unit 7 and stores image data, the order of voltage application to the probe 3, and the like. The control unit 7 controls the probe moving unit 4, the infrared camera 5, the camera moving unit 6, and the voltage applying unit 8.

  FIG. 2 is a diagram schematically showing the wiring of the TFT substrate 2. The TFT substrate 2 includes a source line 21, a gate line 22, and a Cs line 23, and a source pad 24, a gate pad 25, and a Cs pad 26 to which the respective wirings are connected. The first type wiring, the second type wiring, and the third type wiring in the present invention correspond to the source line 21, the gate line 22, and the Cs line 23, respectively.

  The source line 21, the gate line 22, and the Cs line 23 are arranged in a grid pattern on the TFT substrate 2, and the number of these lines depends on the size and type of the substrate. For example, in FIG. The number of lines 21 is 29, the number of gate lines 22 is 10, and the number of Cs lines 23 is 9. The 29 source lines 21, 10 gate lines 22, and 9 Cs lines 23 are connected to a source pad 24, a gate pad 25, and a Cs pad 26, respectively. The probe 3 is brought into contact with the source pad 24, the gate pad 25, and the Cs pad 26, a voltage is applied from the voltage application unit 8, and the resistance value is measured by the resistance measuring device 9. Of course, the source pad 24, the gate pad 25, and the Cs pad 26 are not essential to the present invention. If the resistance value can be measured by combining the respective wirings into one, the outside of the TFT substrate 2 can be used. The wiring may be drawn out to the source line 21, and any configuration may be used as long as a voltage can be applied to the source line 21, the gate line 22, and the Cs line 23.

  FIG. 3 is a diagram showing steps of a wiring defect inspection method according to an embodiment of the present invention. First, the source pad 24 is connected to the positive electrode of the voltage application unit, and the gate pad 25 is connected to the negative electrode, and the resistance value is measured (S31. Step 31 is denoted as S31. The same applies hereinafter). When the measurement is completed, the voltage application unit 8 is electrically disconnected from the source pad 24 and the gate pad. Similarly, after measuring the resistance value between the two pads, the voltage application unit 8 is electrically disconnected. Next, the resistance value is measured by connecting the positive electrode of the voltage application unit 8 to the gate pad 25 and the negative electrode to the Cs pad 26 (S32). When the measurement is completed, the voltage application unit 8 is electrically disconnected from the gate pad 25 and the Cs pad 26. Further, the resistance value is measured by connecting the positive electrode of the voltage application unit 8 to the source pad 24 and the negative electrode to the Cs pad 26 (S33). When the measurement is completed, the voltage application unit 8 is electrically disconnected from the source pad 24 and the Cs pad 26.

  Then, it is determined whether or not there is a short circuit in the wiring by comparing the measured resistance value with a normal resistance value stored in advance in the storage unit 10 (S34). When it is determined that there is a short-circuit defect (S34: YES), the short-circuit defect portion is heated by applying a voltage between the wirings in which the short-circuit is generated by the voltage application unit 8, and the infrared camera 5 causes the TFT substrate 2 to generate heat. Infrared inspection for specifying in detail the position of the short-circuit defect portion that has generated heat is performed (S35). When it is determined that there is no short-circuit defect (S34: NO), the inspection is terminated when the infrared inspection of S35 is completed.

Here, the principle of the wiring defect inspection method according to the present invention will be described. The present invention is characterized in that the order of resistance measurement is determined in advance so that the time until the resistance value stably converges becomes shorter. That is, in consideration of changes in the potential of each pad due to resistance measurement, the positive electrode of the voltage application unit 8 is connected to a pad having a high potential, and the negative electrode of the voltage application unit 8 is connected to a pad having a low potential. As compared with the case where the positive and negative electrodes are connected to each other, the amount of change until the potential of each pad settles to a constant value can be reduced, and the time until the resistance value stably converges can be shortened.
[Example 1]
Hereinafter, the wiring defect inspection method according to the present embodiment and the effects thereof will be described in detail. In this embodiment, a resistance value between wirings of the TFT substrate 2 is measured, and as a result, a change in potential of each pad and a time required for measuring the resistance value when there is no short-circuit defect between the wirings will be described.

  4 to 9 are diagrams for explaining a state in which the voltage applying unit 8 and the resistance measuring device 9 are connected to the source pad 24, the gate pad 25, and the Cs pad 26, and in particular, between the wirings of the TFT substrate 2. FIG. It is a figure for demonstrating the case where there was no defect.

  FIG. 4 is a diagram for explaining a state before the voltage applying unit 8 and the resistance measuring device 9 are connected to the source pad 24, the gate pad 25, and the Cs pad 26. 4A shows the potential and order of the source pad 24, the gate pad 25, and the Cs pad 26, and FIG. 4B shows an equivalent circuit between the source pad 24, the gate pad 25, and the Cs pad 26. Represents. The potential of each pad is based on the potential of the gate pad 25, the potential of the gate pad 25 is represented by 0, and the potential difference between the source pad 24 and the Cs pad 26 is described as a potential. For example, when the source pad 24 is higher than the gate pad 25 by X (V), the source pad 24 is described as X (V). Hereinafter, similarly, the potential difference from the gate pad 25 is described as a potential.

  The order of each pad is used to determine which of the positive and negative electrodes of the voltage application unit 8 is connected when measuring the resistance value between the two pads. In the present embodiment, the positive electrode of the voltage application unit 8 is connected to the pad with higher rank, and the negative electrode is connected to the pad with lower rank.

  As shown in FIG. 4A, the potentials and ranks of the source pad 24, the gate pad 25, and the Cs pad 26 are, in order, X (V), 1st place, 0 (V), 2nd place, and Y (V), respectively. And third place. Here, X (V) and Y (V) are unknown values representing potentials due to charges stored in the source pad 24 and the Cs pad 26 in advance.

  Further, as shown in FIG. 4B, it can be considered that capacitors 41 to 43 are connected between the source pad 24, the gate pad 25, and the Cs pad 26, respectively. That is, it can be considered that the capacitor 41 is connected between the source pad 24 and the gate pad 25, the capacitor 42 is connected between the gate pad 25 and the Cs pad 26, and the capacitor 43 is connected between the source pad 24 and the Cs pad 26. .

  Further, the potential of the gate pad 25 is 0 (V) because it is a reference value. The potentials of the source pad 24 and the Cs pad 26 are X (V) and Y (V) by charging the capacitors 41 to 43, respectively.

  Here, the capacitors 41 to 43 represent stray capacitances that are not intended by the designer, and an accurate value cannot be measured if a direct current flows during resistance measurement. On the other hand, a capacitor is charged when a direct current flows, and charges are stored until the potential difference between the parallel plates of the capacitor becomes equal to the applied voltage. is there. That is, the capacitors 41 to 43 have a constant potential difference after a certain amount of time has elapsed after the voltage is applied, so that no current flows through the capacitors 41 to 43, and an accurate resistance value between the pads can be measured. Become.

  In the defect inspection method according to the present embodiment, first, the order is determined for the source pad 24, the gate pad 25, and the Cs pad 26. That is, when applying a voltage between two different pads, the voltage application unit 8 applies a voltage by connecting a positive electrode to a pad having a lower order number and a negative electrode to a larger pad, and the source pad 24 and the gate pad 25. The resistance values are measured in the order between the gate pad 25 and the Cs pad 26 and between the source pad 24 and the Cs pad 26. By doing so, the potential due to the charge remaining in the capacitors 41 to 43 can be predicted by measuring the resistance value, the positive electrode of the voltage application unit 8 is connected to a pad having a higher potential, and the voltage application unit 8 is connected to a pad having a lower potential. By connecting the negative electrode, the measurement time can be shortened, and the defect can be inspected accurately and efficiently in an appropriate measurement time.

  FIG. 5 is a diagram for explaining how the voltage applying unit 8 and the resistance measuring device 9 are connected between the source pad 24 and the gate pad 25. FIG. 5A is a diagram showing the potential and order of the source pad 24, the gate pad 25, and the Cs pad 26. FIG. 5B is a diagram between the source pad 24, the gate pad 25, and the Cs pad 26. It is a figure explaining a mode that the voltage application part 8 and the resistance measuring device 9 were connected. As shown in FIG. 5B, the source pad 24 is connected to the positive electrode of the voltage application unit 8, and the gate pad 25 is connected to the negative electrode.

  In this embodiment, the voltage application unit 8 generates a potential difference of E (V) between the positive and negative electrodes. Since the potential of the gate pad 25 is 0 (V), the potential of the source pad 24 is changed from X (V) to E (V) as shown in FIG. V). Similarly, the potential on the source pad 24 side of the capacitors 41 and 43 changes to E (V).

  When the potential on the source pad 24 side of the capacitor 41 becomes a constant value, that is, E (V), no current flows theoretically through the capacitor 41. That is, since the current value is 0, the resistance value between the source pad 24 and the gate pad 25 is theoretically R = V / I = E / 0 = ∞. Actually, since a weak current flows, the resistance value between the source pad 24 and the gate pad 25 is several hundred (MΩ), for example. As described above, when the resistance value is normal, for example, 100 (kΩ) or more, it is determined that there is no short circuit.

FIG. 6 is a diagram showing the relationship between the elapsed time after the voltage application unit 8 and the resistance measuring instrument 9 are connected between the source pad 24 and the gate pad 25 and the measured value of the resistance measuring instrument 9. The horizontal axis represents time (seconds), and the vertical axis represents the resistance value (kΩ). As shown in FIG. 6, the resistance value that was initially 0 (kΩ) increases with time, and reaches 100 (kΩ) at the time t ₀ (seconds). That is, it can be determined that there is no short-circuit defect between the source pad 24 and the gate pad 25 at time t ₀ (seconds).

  The voltage application unit 8 and the resistance measuring device 9 are electrically disconnected from the source pad 24 and the gate pad 25 after measuring the resistance value. Of course, the potential of the source pad 24 remains E (V) even after cutting.

  FIG. 7 is a diagram for explaining how the voltage applying unit 8 and the resistance measuring device 9 are connected between the gate pad 25 and the Cs pad 26. FIG. 7A is a diagram showing the potential and order of the source pad 24, the gate pad 25, and the Cs pad 26, and FIG. 7B is a diagram between the source pad 24, the gate pad 25, and the Cs pad 26. It is a figure explaining a mode that the voltage application part 8 and the resistance measuring device 9 were connected.

  As shown in FIG. 7B, the positive electrode of the voltage application unit 8 is connected to the gate pad 25, and the negative electrode is connected to the Cs pad 26. Since the potential of the gate pad 25 is 0 (V), the potential of the Cs pad 26 is changed from Y (V) to −E as shown in FIG. Change to (V). Similarly, the potential on the Cs pad 26 side of the capacitors 42 and 43 changes to -E (V). The resistance value between the gate pad 25 and the Cs pad 26 becomes a sufficiently large value, and it can be determined that there is no short circuit.

  The voltage application unit 8 and the resistance measuring device 9 are electrically disconnected from the gate pad 25 and the Cs pad 26 after measuring the resistance value. Of course, the potential of the Cs pad 26 remains E (V) even after cutting.

  FIG. 8 is a diagram for explaining a state in which the voltage application unit 8 and the resistance measuring device 9 are connected between the source pad 24 and the Cs pad 26. FIG. 8A is a diagram showing the potential and order of the source pad 24, the gate pad 25, and the Cs pad 26, and FIG. 8B is a diagram between the source pad 24, the gate pad 25, and the Cs pad 26. It is a figure explaining a mode that the voltage application part 8 and the resistance measuring device 9 were connected.

  As shown in FIG. 8B, the positive electrode of the voltage application unit 8 is connected to the source pad 24, and the negative electrode is connected to the Cs pad 26. Here, the potential of the source pad 24 before connecting the voltage application unit 8 is E (V), the potential of the Cs pad 26 is −E (V), that is, the potential difference between the source pad 24 and the Cs pad 26 is 2E (. V). Since the voltage application unit 8 acts so as to set the potential difference between the positive and negative electrodes to E (V), as shown in FIG. 8A, the potential of the Cs pad 26 is a certain potential α (−) from −E (V). When the voltage changes to V), the potential of the source pad 24 changes from E (V) to α + E (V). Similarly, the potential on the source pad 24 side of the capacitors 41 and 43 changes to α + E (V), and the potential on the Cs pad 26 side of the capacitors 42 and 43 changes to α (V). The resistance value between the source pad 24 and the Cs pad 26 becomes a sufficiently large value, and it can be determined that there is no short circuit.

  Next, advantages of the wiring defect inspection method according to the present embodiment will be described with reference to FIG.

  FIG. 9 is a diagram illustrating an example of the time elapsed since the voltage applying unit 8 and the resistance measuring device 9 were connected between the source pad 24 and the Cs pad 26 in S33, and respective potentials. The curve indicated by the solid line represents the potential when the positive electrode of the voltage application unit 8 is connected to the source pad 24 and the negative electrode is connected to the Cs pad 26 as described with reference to FIG. The curve indicated by the broken line indicates that the positive and negative electrodes of the voltage application unit 8 described with reference to FIG. 8 are connected in reverse, that is, the negative electrode of the voltage application unit 8 is connected to the source pad 24 and the positive electrode is connected to the Cs pad 26. Represents the potential of the case.

Here, when the positive electrode of the voltage application unit 8 is connected to the source pad 24 and the negative electrode is connected to the Cs pad 26, it takes t ₁ (seconds) and t ₂ (seconds) until the potential becomes constant. When t ₁ <t ₂ , in order to measure the correct resistance values of the source pad 24 and the Cs pad 26, it is necessary to wait t ₂ (seconds) after connecting the voltage application unit 8.

On the other hand, when the negative electrode of the voltage application unit 8 is connected to the source pad 24 and the positive electrode is connected to the Cs pad 26, it takes t ₃ (seconds) and t ₄ (seconds) until the potential becomes constant, respectively. If t ₃ <t ₄ , it is necessary to wait t ₄ (seconds) after connecting the voltage application unit 8 in order to measure the correct resistance values of the source pad 24 and the Cs pad 26.

  As shown by the broken line in FIG. 9, when the positive and negative electrodes of the voltage application unit 8 are connected in reverse, the potential difference of 2E (V) must be changed to E (V) in the reverse direction, that is, the source pad 24 And the potential of the Cs pad 26 must be changed by 3E (V).

On the other hand, as shown by the solid line in FIG. 9, when the positive and negative electrodes of the voltage application unit 8 are connected with the high and low potentials in the order of the pads, the potentials of the source pad 24 and the Cs pad 26 are matched. Since it is only necessary to change E (V), the time t ₂ (seconds) until the potential becomes constant is shorter than the time t ₄ (seconds) required when connecting in the reverse direction.

In other words, this is a wiring defect inspection method in which a short-circuit portion between wirings of a semiconductor substrate is detected by bringing a probe into contact with a plurality of terminal portions each including a plurality of wirings and measuring a resistance value between the terminal portions. Then, the level of the potential applied in the resistance value measurement between the terminal portions is determined for each combination of the terminal portions, and by applying a voltage according to the height, the measurement time is shortened and accurately at an appropriate measurement time, In addition, defects can be inspected efficiently.
[Example 2]
In this embodiment, a resistance value between wirings of the TFT substrate 2 is measured, and as a result, a change in potential of each pad and a time required for measuring the resistance value when there is a short-circuit defect between the wirings will be described.

  10 to 14 are diagrams for explaining a state in which the voltage applying unit 8 and the resistance measuring device 9 are connected to the source pad 24, the gate pad 25, and the Cs pad 26, and in particular, between the wirings of the TFT substrate 2. It is a figure for demonstrating the case where there exists a defect.

  FIG. 10 is a diagram for explaining a state before the voltage application unit 8 and the resistance measuring device 9 are connected to the source pad 24, the gate pad 25, and the Cs pad 26. 10A shows the potential and order of the source pad 24, the gate pad 25, and the Cs pad 26. FIG. 10B shows an equivalent circuit between the source pad 24, the gate pad 25, and the Cs pad 26. Represent.

  As shown in FIG. 10A, the potentials and ranks of the source pad 24, the gate pad 25, and the Cs pad 26 are, in order, 0 (V), 1st place, 0 (V), 2nd place, and Z (V), respectively. And third place. Here, Z (V) is an unknown value representing the potential due to the charge stored in advance in the Cs pad 26.

  Further, as shown in FIG. 10B, it can be considered that capacitors 41 to 43 are connected between the source pad 24, the gate pad 25, and the Cs pad 26, respectively. That is, it can be considered that the capacitor 41 is connected between the source pad 24 and the gate pad 25, the capacitor 42 is connected between the gate pad 25 and the Cs pad 26, and the capacitor 43 is connected between the source pad 24 and the Cs pad 26. .

  Further, the potential of the gate pad 25 is 0 (V) because it is a reference value. The Cs pad 26 has a potential of Z (V) by charging the capacitors 41 to 43.

  Furthermore, the short-circuit defect portion between the source line 21 and the gate line 22 of the TFT substrate 2 can be regarded as a short-circuit resistor 51 connected between the source pad 24 and the gate pad 25. For this reason, the potential of the source pad 24 becomes the same value as the potential of the gate pad 25, that is, 0 (V) through the short-circuit resistor 51.

In the present embodiment, the resistance value of the short-circuit resistor 51 is R ₁ (Ω). Here, R ₁ is a value of about 1 (kΩ), and is not more than 100 (kΩ: kiloohm) determined as no short circuit.

  FIG. 11 is a diagram for explaining a state in which the voltage application unit 8 and the resistance measuring device 9 are connected between the source pad 24 and the gate pad 25. FIG. 11A is a diagram showing the potential and order of the source pad 24, the gate pad 25, and the Cs pad 26, and FIG. 11B is a diagram between the source pad 24, the gate pad 25, and the Cs pad 26. It is a figure explaining a mode that the voltage application part 8 and the resistance measuring device 9 were connected. As shown in FIG. 11B, the source pad 24 is connected to the positive electrode of the voltage application unit 8, and the gate pad 25 is connected to the negative electrode.

  In this embodiment, the voltage application unit 8 generates a potential difference of E (V) between the positive and negative electrodes. Since the potential of the gate pad 25 is 0 (V), the potential of the source pad 24 is changed from 0 (V) to E (E) as shown in FIG. V). Similarly, the potential on the source pad 24 side of the capacitors 41 and 43 changes to E (V).

When the potential on the source pad 24 side of the capacitor 41 becomes a constant value, that is, E (V), almost no current flows through the capacitor 41 and current flows through the short-circuit resistor 51. That is, the resistance value between the source pad 24 and the gate pad 25 may be determined becomes R _1, and there defect.

  Next, in order to replace the voltage application unit 8, it is removed from the source pad 24 and the gate pad 25. After the voltage application unit 8 is removed, the potentials of the source pad 24 and the gate pad 25 change. Therefore, a change in potential when replacing the voltage application unit 8 will be described below.

  FIG. 12A is a diagram for explaining the state of the circuit immediately after the voltage application unit 8 connected to the source pad 24 and the gate pad 25 is removed, and FIG. 12B is a diagram illustrating the voltage application unit 8 and the resistor. It is the figure explaining the mode of the circuit after time passed for a while since the measuring device 9 was removed.

  As shown in FIG. 12A, immediately after the voltage application unit 8 connected to the source pad 24 and the gate pad 25 is removed, the charge stored on the source pad 24 side of the capacitor 41 passes through the short-circuit resistor 51. And flows out to the gate pad 25. That is, a current flows counterclockwise on the paper surface. Then, as shown in FIG. 12B, the electric charge stored in the capacitor 41 is immediately discharged, and the potential of the source pad 24 becomes 0 (V), which is the same as that of the gate pad 25.

  FIG. 13 is a diagram for explaining how the voltage applying unit 8 and the resistance measuring device 9 are connected between the gate pad 25 and the Cs pad 26. FIG. 13A is a diagram showing the potentials and rankings of the source pad 24, the gate pad 25, and the Cs pad 26, and FIG. 13B is a diagram between the source pad 24, the gate pad 25, and the Cs pad 26. It is a figure explaining a mode that the voltage application part 8 and the resistance measuring device 9 were connected.

  As shown in FIG. 13B, the positive electrode of the voltage application unit 8 is connected to the gate pad 25, and the negative electrode is connected to the Cs pad 26. Since the potential of the gate pad 25 is 0 (V), the potential of the Cs pad 26 is changed from Z (V) to −E as shown in FIG. Change to (V). Similarly, the potential on the Cs pad 26 side of the capacitors 42 and 43 changes to -E (V). The resistance value between the gate pad 25 and the Cs pad 26 becomes a sufficiently large value, and it can be determined that there is no short circuit.

  The voltage application unit 8 and the resistance measuring device 9 are electrically disconnected from the gate pad 25 and the Cs pad 26 after measuring the resistance value. Of course, the potential of the Cs pad 26 remains -E (V) even after cutting.

  FIG. 14 is a diagram for explaining how the voltage applying unit 8 and the resistance measuring device 9 are connected between the source pad 24 and the Cs pad 26. FIG. 14A is a diagram showing the potential and order of the source pad 24, the gate pad 25, and the Cs pad 26, and FIG. 14B is a diagram between the source pad 24, the gate pad 25, and the Cs pad 26. It is a figure explaining a mode that the voltage application part 8 and the resistance measuring device 9 were connected.

  As shown in FIG. 14B, the positive electrode of the voltage application unit 8 is connected to the source pad 24, and the negative electrode is connected to the Cs pad 26. Here, the potential of the source pad 24 before connecting the voltage application unit 8 is 0 (V), the potential of the Cs pad 26 is −E (V), that is, the potential difference between the source pad 24 and the Cs pad 26 is E ( V). This is equal to the potential difference between the positive and negative electrodes of the voltage application unit 8. Therefore, the resistance value between the source pad 24 and the Cs pad 26 can be measured immediately. The resistance value between the source pad 24 and the Cs pad 26 becomes a sufficiently large value, and it can be determined that there is no short circuit.

  The wiring defect inspection method according to the present embodiment has an effect that the inspection time can be further reduced by using the short-circuit defect when there is a short-circuit defect portion between the wirings.

  The above is the description of the embodiments and examples of the present invention, but the present invention is not limited only to the above-described embodiments and examples. For example, in the second embodiment, as shown in FIG. 12B, when there is a short-circuit defect between the source line 21 and the gate line 22, the potential of the source pad 24 is the same as that of the gate pad 25 (0). V), the potential of the source pad 24 is not limited to 0 (V) and may be 0 (V) or more and E (V) or less. That is, the time from when the voltage application unit 8 connected to the source pad 24 and the gate pad 25 is disconnected to when the voltage application unit 8 and the resistance measuring device 9 are connected between the gate pad 25 and the Cs pad 26 is This is a case where the time required for the discharge is shorter. Even in this case, after applying a voltage to the gate pad 25 and the Cs pad 26, the potential difference between the source pad 24 and the Cs pad 26 is close to E (V), so that the measurement time can be shortened.

  In the present invention, the control unit 7 and the storage unit 10 may be realized in hardware by a logic circuit formed on an integrated circuit (IC chip), or using a CPU (central processing unit). It may be realized by software. In the latter case, a CPU that executes instructions of a control program that realizes each function, a ROM (read only memory) that stores the control program, a RAM (random access memory) that expands the control program, a control program and various data A storage medium such as a memory to be stored is provided.

  An object of the present invention is to provide a recording medium in which a program code (execution format program, intermediate code program, source program) of a control program, which is software that realizes the functions described above, is recorded so as to be readable by a computer. This can also be achieved by (or CPU or MPU (microprocessor unit)) reading and executing the program code recorded on the recording medium.

  Recording media include, for example, tapes such as magnetic tapes and cassette tapes, magnetic disks such as floppy (registered trademark) disks / hard disks, CD-ROMs (compact disc read-only memory) / MO (magneto-optical) / MD (Mini Disc, registered trademark) / DVD (digital versatile disk) / discs including optical discs such as CD-R (CD Recordable), IC cards (including memory cards) / cards such as optical cards, mask ROM / EPROM (Erasable programmable read-only memory) / EEPROM (electrically erasable and programmable read-only memory) / semiconductor memories such as flash ROM, or logic circuits such as PLD (Programmable logic device) and FPGA (Field Programmable Gate Array) Can be used.

  Furthermore, it is also possible to implement the present invention by uploading software that realizes the above-described functions so as to be accessible to the Internet, a shared server, etc., and the user downloading the software and installing it in the inspection apparatus.

  The inspection apparatus of the present invention is suitable for detecting a short-circuit defect of wiring in a substrate on which a plurality of wirings are formed, and is not limited to a semiconductor substrate, a liquid crystal display device, an organic EL display device, or a solar cell panel. It can be employed for inspection of various substrates.

DESCRIPTION OF SYMBOLS 1 Mother board | substrate 2 TFT board | substrate 3 Probe 4 Probe moving means 5 Infrared camera 6 Camera moving means 7 Control part 8 Voltage application part 9 Resistance measuring device 10 Storage part 21 Source line 22 Gate line 23 Cs line 24 Source pad 25 Gate pad 26 Cs pad 41, 42, 43 Capacitor 51 Short-circuit resistance 100 Defect inspection device

Claims (5)

A wiring defect inspection method for measuring a resistance value by applying a voltage between wirings to detect a short circuit between a plurality of types of wirings of a semiconductor substrate,
The detection of the short circuit part is performed by applying a voltage between the two types of wirings and measuring the resistance value,
A wiring defect inspection method in which the order of application between the plurality of types of wirings is determined, a voltage is applied between the wirings, and resistance value measurement is performed so that the measurement time is shortened. As the plurality of types of wiring, there are a first type wiring, a second type wiring having a lower rank than the first type wiring, and a third type wiring having a lower rank than the second type terminal portion. In semiconductor substrates,
A first step of measuring a resistance value between the first type wiring and the second type wiring;
A second step of measuring a resistance value between the second type wiring and the third type wiring;
The wiring defect according to claim 1, further comprising a third type step of measuring a resistance value between the first type wiring and the third type wiring after the first type and second type steps. Inspection method.   The wiring defect inspection method according to claim 1, further comprising an infrared inspection step of identifying a defective portion by detecting temperature or infrared. An inspection program for operating the wiring defect inspection method according to claim 1,
An inspection program that causes a computer to function as each of the steps described above. A computer-readable program recording medium on which the inspection program according to claim 4 is recorded.