TW201306201A - Package structure and fabrication method thereof - Google Patents

Package structure and fabrication method thereof Download PDF

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Publication number
TW201306201A
TW201306201A TW100125400A TW100125400A TW201306201A TW 201306201 A TW201306201 A TW 201306201A TW 100125400 A TW100125400 A TW 100125400A TW 100125400 A TW100125400 A TW 100125400A TW 201306201 A TW201306201 A TW 201306201A
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Taiwan
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plating layer
trace
metal carrier
layer
package structure
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TW100125400A
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Chinese (zh)
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TWI441296B (en
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林邦群
蔡岳穎
陳泳良
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矽品精密工業股份有限公司
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Priority to TW100125400A priority Critical patent/TWI441296B/en
Priority to CN201110229563.4A priority patent/CN102891124B/en
Publication of TW201306201A publication Critical patent/TW201306201A/en
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Publication of TWI441296B publication Critical patent/TWI441296B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

Disclosed are a package structure and a fabrication method thereof, the package structure including a chip mounting pad, traces, electrical interconnects, a first electroplating layer, a second electroplating layer, a third electroplating layer, a semiconductor chip, a packaging layer and a solder mask layer, wherein the thickness of the traces is smaller than that of the electrical interconnects; the first electroplating layer is formed on the traces and one surface of the electrical interconnects; the second electroplating layer is formed on the other surface of the electrical interconnects and the chip-mounting pad; the third electroplating layer is formed on the other surface of the traces; the semiconductor is disposed on the chip-mounting pad; the packaging material is for encapsulating the semiconductor chip, the solder wire, the first electroplating layer, parts of side surfaces of the traces, and partial side surfaces of the electrical interconnects; and the solder mask layer encapsulates the third electroplating layer, the packaging material, partial side surfaces of the traces, and partial side surfaces of the electrical interconnects, thereby preventing traces from bridging with the solder material of the electrical interconnects and also preventing formation of bubbles on the solder mask layer due to the popcorn effect.

Description

封裝結構及其製法Package structure and its manufacturing method

本發明係有關於一種封裝結構及其製法，尤指一種四方扁平無導腳之封裝結構及其製法。The invention relates to a package structure and a preparation method thereof, in particular to a package structure of a quad flat flat guideless foot and a preparation method thereof.

隨著半導體封裝技術的演進，除了傳統打線式(wire bonding)半導體封裝技術以外，目前的半導體封裝結構已經發展出多種封裝型態，例如四方扁平無導腳(Quad Flat No-lead，簡稱QFN)半導體封裝結構，其係直接將半導體晶片接置於一導線架或承載板上並加以打線，再以封裝材料包覆該半導體晶片與銲線，並於封裝結構底部露出做為連接外部電子裝置的電性接點。此種半導體封裝結構能縮減整體體積並提昇電性功能，遂成為一種封裝的趨勢。With the evolution of semiconductor packaging technology, in addition to the traditional wire bonding semiconductor packaging technology, the current semiconductor package structure has developed a variety of package types, such as Quad Flat No-lead (QFN). a semiconductor package structure, which directly connects a semiconductor wafer to a lead frame or a carrier board and wires the same, and then covers the semiconductor wafer and the bonding wire with a packaging material, and is exposed at the bottom of the package structure as an external electronic device. Electrical contact. Such a semiconductor package structure can reduce the overall volume and enhance electrical functions, and becomes a packaging trend.

請參閱第1A圖，係習知四方扁平無導腳半導體封裝結構之剖視圖。如圖所示，傳統如第6,238,952、6,306,685、6,700,188、或7,060,535號美國專利所揭露之四方扁平無導腳半導體封裝結構係將其部分之線路層做為跡線(trace)11，而另一部份之線路層做為電性接點(terminal)12，然而，由於跡線11與電性接點12之間的距離通常很小，所以很容易發生銲料13橋接(solder bridge)的現象，而造成不良品的產生，如第1A圖左下或右下的跡線11與電性接點12的狀況。Please refer to FIG. 1A, which is a cross-sectional view of a conventional quad flat no-lead semiconductor package structure. As shown, the quad flat no-lead semiconductor package structure disclosed in U.S. Patent Nos. 6,238,952, 6, 306, 685, 6,700, 188, or U.S. Patent No. 7, 060, 535, the portion of the circuit layer as a trace 11 and the other The circuit layer of the portion serves as an electrical terminal 12. However, since the distance between the trace 11 and the electrical contact 12 is usually small, the solder 13 bridge bridge phenomenon easily occurs. The occurrence of defective products, such as the condition of the trace 11 and the electrical contact 12 in the lower left or lower right of Fig. 1A.

為了避免上述銲料橋接之問題，遂有將防銲層形成於該跡線與電性接點之間的方式，如第1B圖之另一種習知四方扁平無導腳半導體封裝結構之剖視圖所示，但是由於跡線11與電性接點12之間的距離過小，在填入該防銲層14時容易有氣泡15在其間產生，這些氣泡15會在後續製程中導致爆米花效應(popcorn effect)，進而嚴重影響整體良率。In order to avoid the above problem of solder bridging, a solder resist layer is formed between the trace and the electrical contact, as shown in the cross-sectional view of another conventional quad flat no-lead semiconductor package structure of FIG. 1B. However, since the distance between the trace 11 and the electrical contact 12 is too small, bubbles 15 are likely to be generated during the filling of the solder resist layer 14, and these bubbles 15 may cause popcorn effect in subsequent processes (popcorn effect). ), which in turn seriously affects overall yield.

因此，如何避免上述習知技術中之種種問題，俾使四方扁平無導腳半導體封裝結構不易發生銲料橋接現象或爆米花效應，實已成為目前亟欲解決的課題。Therefore, how to avoid the various problems in the above-mentioned prior art, so that the quad flat unguided semiconductor package structure is less prone to solder bridging or popcorn effect, has become a problem to be solved at present.

有鑒於上述習知技術之缺失，本發明提供一種封裝結構，係包括：置晶墊、複數跡線及複數電性接點，其各自具有相對之第一表面與第二表面，該置晶墊、跡線及電性接點係於該第一表面彼此齊平，且該跡線之第二表面係凹陷於該置晶墊及電性接點之第二表面；第一電鍍層，係形成於該跡線的第一表面與該電性接點的第一表面上；第二電鍍層，係形成於該電性接點之第二表面與該置晶墊之第二表面上；第三電鍍層，係形成於該跡線之第二表面上；半導體晶片，係設於該置晶墊上，且電性連接至該第一電鍍層；封裝材料，係包覆該半導體晶片、第一電鍍層、跡線的部分側表面、與電性接點的部分側表面；以及防銲層，係由該第二表面側覆蓋該第三電鍍層、封裝材料、跡線的部分側表面、與電性接點的部分側表面，且具有外露該第二電鍍層的防銲層開孔。In view of the above-mentioned shortcomings of the prior art, the present invention provides a package structure including: a pad, a plurality of traces, and a plurality of electrical contacts each having an opposite first surface and a second surface, the crystal pad The traces and the electrical contacts are flush with each other on the first surface, and the second surface of the trace is recessed on the second surface of the crystal pad and the electrical contact; the first plating layer is formed On the first surface of the trace and the first surface of the electrical contact; a second plating layer is formed on the second surface of the electrical contact and the second surface of the crystal pad; a plating layer is formed on the second surface of the trace; a semiconductor wafer is disposed on the crystal pad and electrically connected to the first plating layer; and the encapsulating material covers the semiconductor wafer, the first plating a layer, a portion of the side surface of the trace, and a portion of the side surface of the electrical contact; and a solder resist layer covering the third plating layer, the encapsulating material, a portion of the side surface of the trace, and the electricity by the second surface side a portion of the side surface of the contact, and having a solder resist layer exposed to expose the second plating layer .

本發明復提供一種封裝結構之製法，係包括：準備一具有相對之第一表面與第二表面之金屬承載板，該金屬承載板具有置晶墊，於該第一表面上形成第一阻層，該第一阻層具有外露部分該金屬承載板的第一圖案化開口區；移除該第一圖案化開口區中的該金屬承載板，而構成第一凹部，並定義出跡線凸部與電性接點凸部；移除該第一阻層；於該第二表面上形成第二阻層，該第二阻層具有外露部分該金屬承載板的第二圖案化開口區，該第二圖案化開口區之位置係對應該跡線凸部；移除該第二圖案化開口區中的該金屬承載板，而構成第二凹部；移除該第二阻層；於該跡線凸部與電性接點凸部之頂面上形成第一電鍍層，並於該第二表面上形成對應該置晶墊與電性接點凸部的第二電鍍層，且於該第二凹部中形成第三電鍍層；於該置晶墊上設置一半導體晶片；將該半導體晶片電性連接至該第一電鍍層；於該金屬承載板上形成包覆該半導體晶片與第一電鍍層的封裝材料；從該第二表面移除未被該第二電鍍層與該第三電鍍層所覆蓋的該金屬承載板，而形成複數跡線與複數電性接點；從該第二表面之側形成覆蓋該第二電鍍層、第三電鍍層、封裝材料與金屬承載板的防銲層；以及移除部分該防銲層，以形成外露該第二電鍍層的防銲層開孔。The invention provides a method for fabricating a package structure, comprising: preparing a metal carrier plate having a first surface and a second surface opposite to each other, the metal carrier plate having a crystal pad to form a first resist layer on the first surface The first resist layer has an exposed portion of the first patterned opening region of the metal carrier plate; removing the metal carrier plate in the first patterned opening region to form a first recess and defining a trace protrusion And the electrical contact protrusion; removing the first resistive layer; forming a second resistive layer on the second surface, the second resistive layer having a second patterned opening region of the exposed portion of the metal carrier plate, the first Positioning the second patterned opening region corresponds to the trace protrusion; removing the metal carrier plate in the second patterned opening region to form a second recess; removing the second resist layer; Forming a first plating layer on a top surface of the portion and the electrical contact protrusion, and forming a second plating layer corresponding to the pad and the electrical contact protrusion on the second surface, and in the second recess Forming a third plating layer; disposing a semiconductor wafer on the crystal pad; The semiconductor wafer is electrically connected to the first plating layer; forming a packaging material covering the semiconductor wafer and the first plating layer on the metal carrier board; removing the second plating layer from the second surface The metal carrying plate covered by the third plating layer forms a plurality of traces and a plurality of electrical contacts; forming a second plating layer, a third plating layer, a packaging material and a metal carrier plate from the side of the second surface a solder resist layer; and removing a portion of the solder resist layer to form a solder mask opening that exposes the second plating layer.

本發明復提供另一種封裝結構之製法，係包括：準備一具有相對之第一表面與第二表面之金屬承載板，該金屬承載板具有置晶墊；從該第一表面側移除部分該金屬承載板，以構成第一凹部，並定義出跡線凸部與電性接點凸部；從該第二表面側移除部分該金屬承載板，以構成第二凹部，該第二凹部之位置係對應該跡線凸部；於該置晶墊上設置一半導體晶片；將該半導體晶片電性連接至該跡線凸部與電性接點凸部；於該金屬承載板上形成包覆該半導體晶片、跡線凸部與電性接點凸部的封裝材料；從該第二表面移除未對應該置晶墊、跡線凸部與電性接點凸部的該金屬承載板，而形成複數跡線與複數電性接點；從該第二表面之側形成覆蓋該封裝材料與金屬承載板的防銲層；以及移除部分該防銲層，以形成外露該置晶墊與電性接點的防銲層開孔。The present invention provides a method of fabricating another package structure, comprising: preparing a metal carrier plate having opposite first and second surfaces, the metal carrier plate having a crystal pad; removing the portion from the first surface side a metal carrier plate to form a first recess and defining a trace protrusion and an electrical contact protrusion; removing a portion of the metal carrier from the second surface side to form a second recess, the second recess The position is corresponding to the trace convex portion; a semiconductor wafer is disposed on the crystal pad; the semiconductor wafer is electrically connected to the trace convex portion and the electrical contact convex portion; forming a cladding on the metal carrier plate a packaging material of the semiconductor wafer, the trace protrusion and the electrical contact protrusion; removing the metal carrier board that does not correspond to the pad, the trace protrusion and the electrical contact protrusion from the second surface, and Forming a plurality of traces and a plurality of electrical contacts; forming a solder resist layer covering the package material from the metal carrier plate from a side of the second surface; and removing a portion of the solder resist layer to form the exposed pad and the electricity The solder joint of the contact is opened.

由上可知，本發明之封裝結構係將跡線的厚度減少，以使得跡線與電性接點之間的距離增加，因此後續覆蓋之防銲層較容易填滿於跡線與電性接點之間，而不易有氣泡產生，最終能達成不會銲料橋接與不會造成爆米花效應的雙重優點，且良率也因而提高。It can be seen from the above that the package structure of the present invention reduces the thickness of the trace so that the distance between the trace and the electrical contact increases, so that the subsequently covered solder resist layer is easier to fill the trace and the electrical connection. Between the points, there is no easy bubble generation, and finally the double advantage of not bridging the solder and not causing the popcorn effect can be achieved, and the yield is thus improved.

以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「頂」、「底」、「側」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "top", "bottom", "side" and "one" are used in this description for convenience of description and are not intended to limit the invention. The scope, the change or adjustment of the relative relationship, is also considered to be within the scope of the invention.

請參閱第2A至2K圖，係本發明之封裝結構及其製法之剖視圖，其中，第2K’圖係第2K圖的另一實施態樣。2A to 2K are cross-sectional views showing a package structure of the present invention and a method of manufacturing the same, wherein the 2K' diagram is another embodiment of the 2Kth diagram.

首先，如第2A圖所示，準備一具有相對之第一表面20a與第二表面20b之金屬承載板20，該金屬承載板20具有置晶墊20c，於該第一表面20a上形成第一阻層21，該第一阻層21具有外露部分該金屬承載板20的第一圖案化開口區210。First, as shown in FIG. 2A, a metal carrier 20 having an opposite first surface 20a and a second surface 20b is prepared. The metal carrier 20 has a pad 20c formed on the first surface 20a. The resistive layer 21 has a first patterned opening region 210 of the metal carrier plate 20 exposed.

如第2B圖所示，移除該第一圖案化開口區210中的部分該金屬承載板20，而構成第一凹部202、以及該置晶墊20c上的置晶凹部201，並定義出跡線凸部203a與電性接點凸部203b。As shown in FIG. 2B, a portion of the metal carrier 20 in the first patterned opening region 210 is removed to form a first recess 202, and a crystal recess 201 on the crystal pad 20c, and define a trace. The line convex portion 203a and the electrical contact convex portion 203b.

如第2C圖所示，移除該第一阻層21。The first resist layer 21 is removed as shown in FIG. 2C.

如第2D圖所示，於該第二表面20b上形成第二阻層22，該第二阻層22具有外露部分該金屬承載板20的第二圖案化開口區220，該第二圖案化開口區220之位置係對應該跡線凸部203a。As shown in FIG. 2D, a second resist layer 22 is formed on the second surface 20b, and the second resist layer 22 has a second patterned opening region 220 of the exposed portion of the metal carrier 20, the second patterned opening The position of the area 220 corresponds to the trace convex portion 203a.

如第2E圖所示，移除該第二圖案化開口區220中的部分該金屬承載板20，而構成第二凹部204。As shown in FIG. 2E, a portion of the metal carrier plate 20 in the second patterned opening region 220 is removed to form a second recess 204.

如第2F圖所示，移除該第二阻層22。The second resist layer 22 is removed as shown in FIG. 2F.

如第2G圖所示，於該跡線凸部203a與電性接點凸部203b之頂面上形成第一電鍍層23，並於該第二表面20b上形成對應該置晶凹部201與電性接點凸部203b的第二電鍍層24，且於該第二凹部204中形成第三電鍍層25；其中，上述形成該第一電鍍層23、第二電鍍層24與第三電鍍層25的方式係可先形成具有開口區的阻層，並於該開口區中進行電鍍，最後再移除該阻層而完成，惟前述電鍍形成法應為所屬技術領域之通常知識者所能瞭解，故在此未加以圖示與詳述。As shown in FIG. 2G, a first plating layer 23 is formed on the top surface of the trace convex portion 203a and the electrical contact convex portion 203b, and a corresponding crystal concave portion 201 is formed on the second surface 20b. a second plating layer 24 of the contact bump 203b, and a third plating layer 25 is formed in the second recess 204; wherein the first plating layer 23, the second plating layer 24 and the third plating layer 25 are formed as described above. The method can firstly form a resist layer having an open region, perform electroplating in the open region, and finally remove the resist layer, but the foregoing electroplating formation method should be known to those of ordinary skill in the art. Therefore, it is not illustrated and described in detail herein.

如第2H圖所示，提供一半導體晶片26，該半導體晶片26具有相對之作用面26a與非作用面26b，藉由黏著層27以將該非作用面26b接置於該置晶凹部201中，並藉由複數銲線28將該半導體晶片26電性連接至該第一電鍍層23，且於該金屬承載板20上形成包覆該半導體晶片26、銲線28與第一電鍍層23的封裝材料29。As shown in FIG. 2H, a semiconductor wafer 26 is provided. The semiconductor wafer 26 has an opposite active surface 26a and an inactive surface 26b. The adhesive layer 27 is used to connect the non-active surface 26b to the crystal concave portion 201. The semiconductor wafer 26 is electrically connected to the first plating layer 23 by a plurality of bonding wires 28, and a package covering the semiconductor wafer 26, the bonding wires 28 and the first plating layer 23 is formed on the metal carrier board 20. Material 29.

如第2I圖所示，從該第二表面20b移除未被該第二電鍍層24與該第三電鍍層25所覆蓋的該金屬承載板20，而形成複數跡線205與複數電性接點206。As shown in FIG. 2I, the metal carrier 20 not covered by the second plating layer 24 and the third plating layer 25 is removed from the second surface 20b to form a plurality of traces 205 and a plurality of electrical connections. Point 206.

如第2J圖所示，從該第二表面20b之側形成覆蓋該第二電鍍層24、第三電鍍層25、封裝材料29與金屬承載板20的防銲層30。As shown in FIG. 2J, a solder resist layer 30 covering the second plating layer 24, the third plating layer 25, the encapsulating material 29, and the metal carrier 20 is formed from the side of the second surface 20b.

如第2K圖所示，移除部分該防銲層30，以形成外露該第二電鍍層24的防銲層開孔300，於本實施態樣中，該第三電鍍層25之底面最終係凸出於該封裝材料29之底面；或者，於如第2K’圖所示之另一實施態樣中，該第三電鍍層25之底面最終係與該封裝材料29之底面齊平。As shown in FIG. 2K, a portion of the solder resist layer 30 is removed to form a solder resist layer opening 300 exposing the second plating layer 24. In this embodiment, the bottom surface of the third plating layer 25 is finally The bottom surface of the encapsulating material 29 is protruded from the bottom surface of the encapsulating material 29; or, in another embodiment as shown in FIG. 2K', the bottom surface of the third plating layer 25 is finally flush with the bottom surface of the encapsulating material 29.

於前述之製法中，移除該金屬承載板20的方式可為蝕刻。In the foregoing method, the metal carrier 20 can be removed by etching.

本發明復揭露一種封裝結構，係包括：置晶墊20c、複數跡線205及複數電性接點206，其各自具有相對之第一表面20a與第二表面20b，該置晶墊20c、跡線205及電性接點206係於該第一表面20a彼此齊平，且該跡線205之第二表面20b係凹陷於該置晶墊20c及電性接點206之第二表面20b；第一電鍍層23，係形成於該跡線205的第一表面20a與該電性接點206的第一表面20a上；第二電鍍層24，係形成於該電性接點206之第二表面20b與該置晶墊20c之第二表面20b上；第三電鍍層25，係形成於該跡線205之第二表面20b上；半導體晶片26，係設於該置晶墊20c上，且電性連接至該第一電鍍層23；封裝材料29，係包覆該半導體晶片26、第一電鍍層23、跡線205的部分側表面、與電性接點206的部分側表面；以及防銲層30，係由該第二表面20b側覆蓋該第三電鍍層25、封裝材料29、跡線205的部分側表面、與電性接點206的部分側表面，且具有外露該第二電鍍層24的防銲層開孔300。The present invention further discloses a package structure, comprising: a pad 20c, a plurality of traces 205, and a plurality of electrical contacts 206, each having an opposite first surface 20a and a second surface 20b, the spacer 20c, the trace The second surface 20b of the trace 205 is recessed on the second surface 20b of the crystal pad 20c and the electrical contact 206; A plating layer 23 is formed on the first surface 20a of the trace 205 and the first surface 20a of the electrical contact 206. The second plating layer 24 is formed on the second surface of the electrical contact 206. 20b and the second surface 20b of the crystal pad 20c; a third plating layer 25 is formed on the second surface 20b of the trace 205; the semiconductor wafer 26 is disposed on the crystal pad 20c, and is electrically Is electrically connected to the first plating layer 23; the encapsulating material 29 covers the semiconductor wafer 26, the first plating layer 23, a portion of the side surface of the trace 205, and a portion of the side surface of the electrical contact 206; and solder resist The layer 30 covers the third plating layer 25, the encapsulating material 29, a part of the side surface of the trace 205, and the electrical connection by the second surface 20b side. A portion of the side surface of the point 206 has a solder mask opening 300 that exposes the second plating layer 24.

依上所述之封裝結構，於該置晶墊20c可形成有連通至該第一表面20a之置晶凹部201，且該半導體晶片26係可設於該置晶凹部201中。According to the package structure, the crystal pad 20c can be formed with a crystal recess 201 connected to the first surface 20a, and the semiconductor wafer 26 can be disposed in the crystal recess 201.

於前述之封裝結構中，該第三電鍍層25之底面係可與該封裝材料29之底面齊平，或者，該第三電鍍層25之底面係可凸出於該封裝材料29之底面。In the above package structure, the bottom surface of the third plating layer 25 may be flush with the bottom surface of the packaging material 29, or the bottom surface of the third plating layer 25 may protrude from the bottom surface of the packaging material 29.

又於本發明之封裝結構中，該半導體晶片26係可藉由複數銲線28電性連接至該第一電鍍層23。In the package structure of the present invention, the semiconductor wafer 26 can be electrically connected to the first plating layer 23 by a plurality of bonding wires 28.

綜上所述，相較於習知技術，本發明之封裝結構係藉由減少跡線的厚度以加大跡線與電性接點之間的距離，因此後續的防銲層較容易填滿，而不易有氣泡產生，最終即達成不會銲料橋接與不會造成爆米花效應的雙重優點，並大幅提高良率。In summary, compared with the prior art, the package structure of the present invention increases the distance between the trace and the electrical contact by reducing the thickness of the trace, so that the subsequent solder resist layer is easier to fill. It is not easy to have bubbles, and finally the double advantage of not bridging the solder and not causing the popcorn effect is achieved, and the yield is greatly improved.

上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

11．．．跡線11. . . Trace

12．．．電性接點12. . . Electrical contact

13．．．銲料13. . . solder

14、30．．．防銲層14, 30. . . Solder mask

15．．．氣泡15. . . bubble

20．．．金屬承載板20. . . Metal carrier board

20a．．．第一表面20a. . . First surface

20b．．．第二表面20b. . . Second surface

20c．．．置晶墊20c. . . Crystal pad

201．．．置晶凹部201. . . Crystal recess

202．．．第一凹部202. . . First recess

203a．．．跡線凸部203a. . . Trace convex

203b．．．電性接點凸部203b. . . Electrical contact protrusion

204．．．第二凹部204. . . Second recess

205．．．跡線205. . . Trace

206．．．電性接點206. . . Electrical contact

21．．．第一阻層twenty one. . . First resistive layer

210．．．第一圖案化開口區210. . . First patterned open area

22．．．第二阻層twenty two. . . Second resistive layer

220．．．第二圖案化開口區220. . . Second patterned opening area

23．．．第一電鍍層twenty three. . . First plating

24．．．第二電鍍層twenty four. . . Second plating

25．．．第三電鍍層25. . . Third plating

26．．．半導體晶片26. . . Semiconductor wafer

26a．．．作用面26a. . . Action surface

26b．．．非作用面26b. . . Non-active surface

27．．．黏著層27. . . Adhesive layer

28．．．銲線28. . . Welding wire

29．．．封裝材料29. . . Packaging material

300．．．防銲層開孔300. . . Solder mask opening

第1A圖係一種習知四方扁平無導腳半導體封裝結構之剖視圖；1A is a cross-sectional view of a conventional quad flat no-lead semiconductor package structure;

第1B圖係另一種習知四方扁平無導腳半導體封裝結構之剖視圖；以及1B is a cross-sectional view of another conventional quad flat no-lead semiconductor package structure;

第2A至2K圖係本發明之封裝結構及其製法之剖視圖，其中，第2K’圖係第2K圖的另一實施態樣。2A to 2K are cross-sectional views showing a package structure of the present invention and a method of manufacturing the same, wherein the 2K' diagram is another embodiment of the 2Kth diagram.

20．．．金屬承載板20. . . Metal carrier board

20a．．．第一表面20a. . . First surface

20b．．．第二表面20b. . . Second surface

20c．．．置晶墊20c. . . Crystal pad

201．．．置晶凹部201. . . Crystal recess

202．．．第一凹部202. . . First recess

203a．．．跡線凸部203a. . . Trace convex

203b．．．電性接點凸部203b. . . Electrical contact protrusion

205．．．跡線205. . . Trace

206．．．電性接點206. . . Electrical contact

23．．．第一電鍍層twenty three. . . First plating

24．．．第二電鍍層twenty four. . . Second plating

25．．．第三電鍍層25. . . Third plating

26．．．半導體晶片26. . . Semiconductor wafer

26a．．．作用面26a. . . Action surface

26b．．．非作用面26b. . . Non-active surface

27．．．黏著層27. . . Adhesive layer

28．．．銲線28. . . Welding wire

29．．．封裝材料29. . . Packaging material

30．．．防銲層30. . . Solder mask

300．．．防銲層開孔300. . . Solder mask opening

Claims (13)

一種封裝結構，係包括：置晶墊、複數跡線及複數電性接點，其各自具有相對之第一表面與第二表面，該置晶墊、跡線及電性接點係於該第一表面彼此齊平，且該跡線之第二表面係凹陷於該置晶墊及電性接點之第二表面；第一電鍍層，係形成於該跡線的第一表面與該電性接點的第一表面上；第二電鍍層，係形成於該電性接點之第二表面與該置晶墊之第二表面上；第三電鍍層，係形成於該跡線之第二表面上；半導體晶片，係設於該置晶墊上，且電性連接至該第一電鍍層；封裝材料，係包覆該半導體晶片、第一電鍍層、跡線的部分側表面、與電性接點的部分側表面；以及防銲層，係由該第二表面側覆蓋該第三電鍍層、封裝材料、跡線的部分側表面、與電性接點的部分側表面，且具有外露該第二電鍍層的防銲層開孔。A package structure includes: a pad, a plurality of traces, and a plurality of electrical contacts each having a first surface and a second surface, wherein the pad, the trace, and the electrical contact are a surface is flush with each other, and a second surface of the trace is recessed on the second surface of the crystal pad and the electrical contact; the first plating layer is formed on the first surface of the trace and the electrical a second plating layer formed on the second surface of the electrical contact and the second surface of the crystal pad; the third plating layer is formed on the second surface of the trace a semiconductor wafer disposed on the crystal pad and electrically connected to the first plating layer; the encapsulation material covering the semiconductor wafer, the first plating layer, a portion of the side surface of the trace, and the electrical property a portion of the side surface of the contact; and a solder resist layer covering the third plating layer, the encapsulating material, a portion of the side surface of the trace, and a portion of the side surface of the electrical contact by the second surface side, and having the exposed surface The solder resist layer of the second plating layer is opened. 如申請專利範圍第1項所述之封裝結構，其中，於該置晶墊形成有連通至該第一表面之置晶凹部，且該半導體晶片係設於該置晶凹部中。The package structure of claim 1, wherein the crystal pad is formed with a crystal recess that communicates with the first surface, and the semiconductor wafer is disposed in the crystal recess. 如申請專利範圍第1項所述之封裝結構，其中，該第三電鍍層之底面係與該封裝材料之底面齊平。The package structure of claim 1, wherein the bottom surface of the third plating layer is flush with the bottom surface of the packaging material. 如申請專利範圍第1項所述之封裝結構，其中，該第三電鍍層之底面係凸出於該封裝材料之底面。The package structure of claim 1, wherein a bottom surface of the third plating layer protrudes from a bottom surface of the packaging material. 如申請專利範圍第1項所述之封裝結構，其中，該半導體晶片係藉由複數銲線電性連接至該第一電鍍層。The package structure of claim 1, wherein the semiconductor wafer is electrically connected to the first plating layer by a plurality of bonding wires. 一種封裝結構之製法，係包括：準備一具有相對之第一表面與第二表面之金屬承載板，該金屬承載板具有置晶墊，於該第一表面上形成第一阻層，該第一阻層具有外露部分該金屬承載板的第一圖案化開口區；移除該第一圖案化開口區中的該金屬承載板，而構成第一凹部，並定義出跡線凸部與電性接點凸部；移除該第一阻層；於該第二表面上形成第二阻層，該第二阻層具有外露部分該金屬承載板的第二圖案化開口區，該第二圖案化開口區之位置係對應該跡線凸部；移除該第二圖案化開口區中的該金屬承載板，而構成第二凹部；移除該第二阻層；於該跡線凸部與電性接點凸部之頂面上形成第一電鍍層，並於該第二表面上形成對應該置晶墊與電性接點凸部的第二電鍍層，且於該第二凹部中形成第三電鍍層；於該置晶墊上設置一半導體晶片；將該半導體晶片電性連接至該第一電鍍層；於該金屬承載板上形成包覆該半導體晶片與第一電鍍層的封裝材料；從該第二表面移除未被該第二電鍍層與該第三電鍍層所覆蓋的該金屬承載板，而形成複數跡線與複數電性接點；從該第二表面之側形成覆蓋該第二電鍍層、第三電鍍層、封裝材料與金屬承載板的防銲層；以及移除部分該防銲層，以形成外露該第二電鍍層的防銲層開孔。A method for fabricating a package structure includes: preparing a metal carrier plate having a first surface and a second surface opposite to each other, the metal carrier plate having a crystal pad, and forming a first resist layer on the first surface, the first The resist layer has an exposed portion of the first patterned opening region of the metal carrier plate; removing the metal carrier plate in the first patterned opening region to form a first recess, and defining a trace protrusion and an electrical connection Pointing a convex portion; removing the first resistive layer; forming a second resistive layer on the second surface, the second resistive layer having a second patterned opening region of the exposed portion of the metal carrier plate, the second patterned opening The position of the region is corresponding to the trace protrusion; the metal carrier plate in the second patterned opening region is removed to form a second recess; the second resist layer is removed; the trace protrusion and the electrical property are Forming a first plating layer on a top surface of the contact protrusion, forming a second plating layer corresponding to the crystal pad and the electrical contact protrusion on the second surface, and forming a third layer in the second recess a plating layer; a semiconductor wafer is disposed on the crystal pad; the semiconductor crystal Electrically connecting to the first plating layer; forming an encapsulation material covering the semiconductor wafer and the first plating layer on the metal carrier plate; removing the second plating layer and the third plating from the second surface The metal carrier plate covered by the layer forms a plurality of traces and a plurality of electrical contacts; forming a solder mask covering the second plating layer, the third plating layer, the encapsulating material and the metal carrier plate from the side of the second surface And removing a portion of the solder resist layer to form a solder mask opening that exposes the second plating layer. 如申請專利範圍第6項所述之封裝結構之製法，其中，移除該第一圖案化開口區中的該金屬承載板復包括於該置晶墊中構成置晶凹部，且該半導體晶片係設於該置晶凹部中。The method of manufacturing the package structure of claim 6, wherein removing the metal carrier plate in the first patterned opening region comprises forming a crystal recess in the crystal pad, and the semiconductor chip system It is disposed in the crystal recess. 如申請專利範圍第6項所述之封裝結構之製法，其中，該第三電鍍層之底面係與該封裝材料之底面齊平。The method of fabricating the package structure according to claim 6, wherein the bottom surface of the third plating layer is flush with the bottom surface of the packaging material. 如申請專利範圍第6項所述之封裝結構之製法，其中，該第三電鍍層之底面係凸出於該封裝材料之底面。The method of fabricating a package structure according to claim 6, wherein a bottom surface of the third plating layer protrudes from a bottom surface of the packaging material. 如申請專利範圍第6項所述之封裝結構之製法，其中，該半導體晶片係藉由複數銲線電性連接至該第一電鍍層。The method of fabricating a package structure according to claim 6, wherein the semiconductor wafer is electrically connected to the first plating layer by a plurality of bonding wires. 一種封裝結構之製法，係包括：準備一具有相對之第一表面與第二表面之金屬承載板，該金屬承載板具有置晶墊；從該第一表面側移除部分該金屬承載板，以構成第一凹部，並定義出跡線凸部與電性接點凸部；從該第二表面側移除部分該金屬承載板，以構成第二凹部，該第二凹部之位置係對應該跡線凸部；於該置晶墊上設置一半導體晶片；將該半導體晶片電性連接至該跡線凸部與電性接點凸部；於該金屬承載板上形成包覆該半導體晶片、跡線凸部與電性接點凸部的封裝材料；從該第二表面移除未對應該置晶墊、跡線凸部與電性接點凸部的該金屬承載板，而形成複數跡線與複數電性接點；從該第二表面之側形成覆蓋該封裝材料與金屬承載板的防銲層；以及移除部分該防銲層，以形成外露該置晶墊與電性接點的防銲層開孔。A method for fabricating a package structure includes: preparing a metal carrier plate having opposite first and second surfaces, the metal carrier plate having a crystal pad; removing a portion of the metal carrier plate from the first surface side to Forming a first recess and defining a trace protrusion and an electrical contact protrusion; removing a portion of the metal carrier from the second surface side to form a second recess, the position of the second recess being corresponding to the trace a semiconductor wafer is disposed on the crystal pad; the semiconductor wafer is electrically connected to the trace protrusion and the electrical contact protrusion; and the semiconductor wafer and the trace are formed on the metal carrier board a packaging material of the convex portion and the electrical contact convex portion; removing the metal carrier plate not corresponding to the crystal pad, the trace convex portion and the electrical contact convex portion from the second surface to form a plurality of traces and a plurality of electrical contacts; forming a solder resist layer covering the encapsulating material and the metal carrier plate from a side of the second surface; and removing a portion of the solder resist layer to form an exposed exposed pad and an electrical contact The weld layer is opened. 如申請專利範圍第11項所述之封裝結構之製法，其中，從該第一表面側移除部分該金屬承載板復包括於該置晶墊中構成置晶凹部，且該半導體晶片係設於該置晶凹部中。The method of manufacturing the package structure of claim 11, wherein the portion of the metal carrier plate removed from the first surface side is included in the crystal pad to form a crystal recess, and the semiconductor chip is In the crystal recess. 如申請專利範圍第11項所述之封裝結構之製法，其中，該半導體晶片係藉由複數銲線電性連接至該跡線凸部與電性接點凸部。The method of fabricating a package structure according to claim 11, wherein the semiconductor wafer is electrically connected to the trace protrusion and the electrical contact protrusion by a plurality of bonding wires.
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