CN102891124A - Package structure and method for fabricating the same - Google Patents
Package structure and method for fabricating the same Download PDFInfo
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- CN102891124A CN102891124A CN2011102295634A CN201110229563A CN102891124A CN 102891124 A CN102891124 A CN 102891124A CN 2011102295634 A CN2011102295634 A CN 2011102295634A CN 201110229563 A CN201110229563 A CN 201110229563A CN 102891124 A CN102891124 A CN 102891124A
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- electrodeposited coating
- trace
- electrical contact
- loading plate
- metal loading
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- 238000000034 method Methods 0.000 title claims description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 239000000463 material Substances 0.000 claims abstract description 28
- 238000002360 preparation method Methods 0.000 claims abstract description 5
- 239000011248 coating agent Substances 0.000 claims description 66
- 238000000576 coating method Methods 0.000 claims description 66
- 239000002184 metal Substances 0.000 claims description 44
- 238000003466 welding Methods 0.000 claims description 26
- 238000000059 patterning Methods 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 230000000994 depressogenic effect Effects 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 10
- 235000002017 Zea mays subsp mays Nutrition 0.000 abstract description 7
- 241000482268 Zea mays subsp. mays Species 0.000 abstract description 7
- 229910000679 solder Inorganic materials 0.000 abstract description 5
- 238000004806 packaging method and process Methods 0.000 abstract description 4
- 239000013078 crystal Substances 0.000 abstract 3
- 238000005538 encapsulation Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
A packaging structure and its preparation method, the packaging structure includes putting the crystal cushion, trace, electric contact, the first electroplated layer, the second electroplated layer, the third electroplated layer, the semiconductor chip, encapsulated material and solder mask, the thickness of the trace is smaller than the thickness of the electric contact, the first electroplated layer is formed on one surface of the trace and the electric contact, the second electroplated layer is formed on another surface of the electric contact and the crystal cushion, the third electroplated layer is formed on another surface of the trace, the semiconductor chip is set on the crystal cushion, the encapsulated material coats the semiconductor chip, the first electroplated layer, partial side surface of the trace and partial side surface of the electric contact, the solder mask covers the third electroplated layer, encapsulated material, partial side surface of the trace and partial side surface of the electric contact. The invention can avoid the solder bridging between the trace and the electrical contact, and can prevent the solder mask layer from generating bubbles which can cause popcorn effect.
Description
Technical field
The present invention is relevant for a kind of encapsulating structure and method for making thereof, and espespecially a kind of quad flat is without encapsulating structure and the method for making thereof of lead foot.
Background technology
Evolution along with semiconductor packaging, except traditional routing type (wire bonding) semiconductor packaging, present semiconductor package has developed multiple encapsulation kenel, for example quad flat is without lead foot (Quad Flat No-lead, be called for short QFN) semiconductor package, it places on a lead frame or the loading plate and routing in addition by directly semiconductor chip being connect, coat this semiconductor chip and bonding wire with encapsulating material again, and expose as the electrical contact that connects external electronic in the encapsulating structure bottom.This kind semiconductor package can reduce overall volume and promote electrical functionality, then becomes a kind of trend of encapsulation.
See also Figure 1A, existing quad flat is without the cutaway view of lead foot semiconductor package.As shown in the figure, tradition as the 6th, 238,952,6,306,685,6,700,188, or 7,060, No. 535 U.S.As enclose the disclosed quad flat of patent without the lead foot semiconductor package with the line layer of its part as trace (trace) 11, and line layer of another part is as electrical contact (terminal) 12, yet, because the distance between trace 11 and the electrical contact 12 is usually very little, so be easy to occur the phenomenon of scolder 13 bridge joints (solder bridge), and cause the generation of defective products, such as the trace 11 of Figure 1A lower-left or bottom right and the situation of electrical contact 12.
Problem for fear of above-mentioned scolder bridge joint, then have welding resisting layer is formed at mode between this trace and the electrical contact, another kind such as Figure 1B has quad flat now without shown in the cutaway view of lead foot semiconductor package, but because the distance between trace 11 and the electrical contact 12 is too small, when inserting this welding resisting layer 14, easily there is bubble 15 to produce betwixt, these bubbles 15 can cause popcorn effect (popcorn effect) in successive process, and then have a strong impact on whole yield.
Therefore, how to avoid above-mentioned variety of problems of the prior art, so that quad flat is difficult for occuring scolder bridge joint phenomenon or popcorn effect without the lead foot semiconductor package, the real problem of desiring most ardently at present solution that become.
Summary of the invention
Because the disappearance of above-mentioned prior art, main purpose of the present invention is to provide a kind of encapsulating structure and method for making thereof, avoiding the scolder bridge joint of this trace and electrical contact, and makes this welding resisting layer be difficult for the bubble that generation can cause popcorn effect.
Encapsulating structure provided by the present invention comprises: put brilliant pad, many traces and a plurality of electrical contact, it has relative first surface and second surface separately, this is put brilliant pad, trace and electrical contact and flushes each other in this first surface, and the second surface of this trace is depressed in the second surface that this puts brilliant pad and electrical contact; The first electrodeposited coating is formed on the first surface of the first surface of this trace and this electrical contact; The second electrodeposited coating is formed at the second surface of this electrical contact and this is put on the second surface of brilliant pad; The 3rd electrodeposited coating is formed on the second surface of this trace; Semiconductor chip is located at this and is put on the brilliant pad, and is electrically connected to this first electrodeposited coating; Encapsulating material coats the part side surface of this semiconductor chip, the first electrodeposited coating, trace and the part side surface of electrical contact; And welding resisting layer, cover the part side surface of the 3rd electrodeposited coating, encapsulating material, trace and the part side surface of electrical contact by this second surface side, and have the welding resisting layer perforate that exposes this second electrodeposited coating.
The present invention also provides a kind of method for making of encapsulating structure, comprise: preparation one has the metal loading plate of relative first surface and second surface, this metal loading plate has puts brilliant pad, form the first resistance layer on this first surface, this first resistance layer has the first patterning open region of this metal loading plate of exposed parts; Remove this metal loading plate in this first patterning open region, and consist of the first recess, and define trace protuberance and electrical contact protuberance; Remove this first resistance layer; Form the second resistance layer on this second surface, this second resistance layer has the second patterning open region of this metal loading plate of exposed parts, and the position of this second patterning open region is to should the trace protuberance; Remove this metal loading plate in this second patterning open region, and consist of the second recess; Remove this second resistance layer; On the end face of this trace protuberance and electrical contact protuberance, form the first electrodeposited coating, and on this second surface, form should putting the second electrodeposited coating of brilliant pad and electrical contact protuberance, and in this second recess, form the 3rd electrodeposited coating; Put on the brilliant pad in this semiconductor chip is set; This semiconductor chip is electrically connected to this first electrodeposited coating; On this metal loading plate, form the encapsulating material that coats this semiconductor chip and the first electrodeposited coating; Remove not this metal loading plate that is covered by this second electrodeposited coating and the 3rd electrodeposited coating from this second surface, and form many traces and a plurality of electrical contact; Form the welding resisting layer that covers this second electrodeposited coating, the 3rd electrodeposited coating, encapsulating material and metal loading plate from the side of this second surface; And remove this welding resisting layer of part, expose the welding resisting layer perforate of this second electrodeposited coating with formation.
The present invention also provides the method for making of another kind of encapsulating structure, comprising: preparation one has the metal loading plate of relative first surface and second surface, and this metal loading plate has puts brilliant pad; Except this metal loading plate of part, consisting of the first recess, and define trace protuberance and electrical contact protuberance from this first surface sidesway; Except this metal loading plate of part, consisting of the second recess, the position of this second recess is to should the trace protuberance from this second surface sidesway; Put on the brilliant pad in this semiconductor chip is set; This semiconductor chip is electrically connected to this trace protuberance and electrical contact protuberance; On this metal loading plate, form the encapsulating material that coats this semiconductor chip, trace protuberance and electrical contact protuberance; Remove should putting this metal loading plate of brilliant pad, trace protuberance and electrical contact protuberance from this second surface, and form many traces and a plurality of electrical contact; Form the welding resisting layer that covers this encapsulating material and metal loading plate from the side of this second surface; And remove this welding resisting layer of part, expose the welding resisting layer perforate that this puts brilliant pad and electrical contact with formation.
As from the foregoing, encapsulating structure of the present invention reduces by the thickness with trace, so that the distance between trace and the electrical contact increases, therefore the welding resisting layer of follow-up covering is easier to be filled between trace and the electrical contact, and be difficult for that Bubble formation is arranged, finally can reach not can scolder bridge joint and the two-fold advantage that can not cause popcorn effect, and yield also thereby improve.
Description of drawings
Figure 1A is that a kind of existing quad flat is without the cutaway view of lead foot semiconductor package;
Figure 1B is that another kind of existing quad flat is without the cutaway view of lead foot semiconductor package; And
Fig. 2 A to Fig. 2 K is the cutaway view of encapsulating structure of the present invention and method for making thereof, and wherein, Fig. 2 K ' is another embodiment of Fig. 2 K.
The primary clustering symbol description
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.
Notice, the appended graphic structure that illustrates of this specification, ratio, size etc., equal contents in order to cooperate specification to disclose only, understanding and reading for those skilled in the art, be not to limit the enforceable qualifications of the present invention, therefore the technical essential meaning of tool not, the adjustment of the modification of any structure, the change of proportionate relationship or size, not affecting under the effect that the present invention can produce and the purpose that can reach, all should still drop on disclosed technology contents and get in the scope that can contain.Simultaneously, quote in this specification as " on ", " top ", " end ", " side " reach terms such as " one ", also only for ease of understanding of narrating, but not in order to limit the enforceable scope of the present invention, change or adjustment that it closes relatively, under without essence change technology contents, also ought be considered as the enforceable category of the present invention.
See also Fig. 2 A to Fig. 2 K, the cutaway view of encapsulating structure of the present invention and method for making thereof, wherein, Fig. 2 K ' is another embodiment of Fig. 2 K.
At first, shown in Fig. 2 A, prepare one and have relative first surface 20a and the metal loading plate 20 of second surface 20b, this metal loading plate 20 has puts brilliant pad 20c, in upper first resistance layer 21 that forms of this first surface 20a, this first resistance layer 21 has the first patterning open region 210 of this metal loading plate 20 of exposed parts.
Shown in Fig. 2 B, remove this metal loading plate 20 of part in this first patterning open region 210, put the brilliant recess 201 of putting on the brilliant pad 20c and consist of the first recess 202 and this, and define trace protuberance 203a and electrical contact protuberance 203b.
Shown in Fig. 2 C, remove this first resistance layer 21.
Shown in Fig. 2 D, in upper second resistance layer 22 that forms of this second surface 20b, this second resistance layer 22 has the second patterning open region 220 of this metal loading plate 20 of exposed parts, and the position of this second patterning open region 220 is to should trace protuberance 203a.
Shown in Fig. 2 E, remove this metal loading plate 20 of part in this second patterning open region 220, and consist of the second recess 204.
Shown in Fig. 2 F, remove this second resistance layer 22.
Shown in Fig. 2 G, on the end face of this trace protuberance 203a and electrical contact protuberance 203b, form the first electrodeposited coating 23, and form should putting the second electrodeposited coating 24 of brilliant recess 201 and electrical contact protuberance 203b in this second surface 20b is upper, and in this second recess 204, form the 3rd electrodeposited coating 25; Wherein, the mode of this first electrodeposited coating 23 of above-mentioned formation, the second electrodeposited coating 24 and the 3rd electrodeposited coating 25 is for can form first the resistance layer with open region, and in this open region, electroplate, remove again this resistance layer at last and finish, the knowledgeable that usually knows of technical field can understand under aforementioned plating forming method should be, therefore at this not in addition icon and detailed description.
Shown in Fig. 2 H, semiconductor chip 26 is provided, this semiconductor chip 26 has relative acting surface 26a and non-acting surface 26b, place this to put brilliant recess 201 by adhesion coating 27 should non-acting surface 26b to connect, and by a plurality of bonding wires 28 this semiconductor chip 26 is electrically connected to this first electrodeposited coating 23, and on this metal loading plate 20, form the encapsulating material 29 that coats this semiconductor chip 26, bonding wire 28 and the first electrodeposited coating 23.
Shown in Fig. 2 I, remove this metal loading plate 20 that is not covered by this second electrodeposited coating 24 and the 3rd electrodeposited coating 25 from this second surface 20b, and form many traces 205 and a plurality of electrical contacts 206.
Shown in Fig. 2 J, form the welding resisting layer 30 of this second electrodeposited coating 24 of covering, the 3rd electrodeposited coating 25, encapsulating material 29 and metal loading plate 20 from that side of this second surface 20b.
Shown in Fig. 2 K, remove this welding resisting layer 30 of part, expose the welding resisting layer perforate 300 of this second electrodeposited coating 24 with formation, in the present embodiment, the bottom surface of the 3rd electrodeposited coating 25 finally protrudes from the bottom surface of this encapsulating material 29; Perhaps, in another embodiment shown in Fig. 2 K ', the bottom surface of the 3rd electrodeposited coating 25 finally flushes with the bottom surface of this encapsulating material 29.
In aforesaid method for making, the mode that removes this metal loading plate 20 can be etching.
The present invention also discloses a kind of encapsulating structure, comprise: put brilliant pad 20c, many traces 205 and a plurality of electrical contact 206, it has relative first surface 20a and second surface 20b separately, this is put brilliant pad 20c, trace 205 and electrical contact 206 and flushes each other in this first surface 20a, and the second surface 20b of this trace 205 is depressed in the second surface 20b that this puts brilliant pad 20c and electrical contact 206; The first electrodeposited coating 23 is formed on the first surface 20a of the first surface 20a of this trace 205 and this electrical contact 206; The second electrodeposited coating 24 is formed at the second surface 20b of this electrical contact 206 and this is put on the second surface 20b of brilliant pad 20c; The 3rd electrodeposited coating 25 is formed on the second surface 20b of this trace 205; Semiconductor chip 26 is located at this and is put on the brilliant pad 20c, and is electrically connected to this first electrodeposited coating 23; Encapsulating material 29 coats the part side surface of this semiconductor chip 26, the first electrodeposited coating 23, trace 205 and the part side surface of electrical contact 206; And welding resisting layer 30, cover the part side surface of the 3rd electrodeposited coating 25, encapsulating material 29, trace 205 and the part side surface of electrical contact 206 by this second surface 20b side, and have the welding resisting layer perforate 300 that exposes this second electrodeposited coating 24.
According to the above encapsulating structure, put brilliant pad 20c in this and can be formed with and be communicated to the brilliant recess 201 of putting of this first surface 20a, and this semiconductor chip 26 can be located at this and put in the brilliant recess 201.
In aforesaid encapsulating structure, the bottom surface of the 3rd electrodeposited coating 25 can flush with the bottom surface of this encapsulating material 29, and perhaps, the bottom surface of the 3rd electrodeposited coating 25 can protrude from the bottom surface of this encapsulating material 29.
In encapsulating structure of the present invention, this semiconductor chip 26 can be electrically connected to this first electrodeposited coating 23 by a plurality of bonding wires 28 again.
In sum, compared to prior art, encapsulating structure of the present invention passes through to reduce the thickness of trace to strengthen the distance between trace and the electrical contact, therefore follow-up welding resisting layer is easier to fill up, and be difficult for that Bubble formation is arranged, final namely reach not can the scolder bridge joint with can not cause the two-fold advantage of popcorn effect, and significantly improve yield.
Above-described embodiment is only in order to illustrative principle of the present invention and effect thereof, but not is used for restriction the present invention.Any those skilled in the art all can under spirit of the present invention and category, make amendment to above-described embodiment.So the scope of the present invention, should be listed such as claims.
Claims (13)
1. encapsulating structure comprises:
Put brilliant pad, many traces and a plurality of electrical contact, it has relative first surface and second surface separately, this is put brilliant pad, trace and electrical contact and flushes each other in this first surface, and the second surface of this trace is depressed in the second surface that this puts brilliant pad and electrical contact;
The first electrodeposited coating is formed on the first surface of the first surface of this trace and this electrical contact;
The second electrodeposited coating is formed at the second surface of this electrical contact and this is put on the second surface of brilliant pad;
The 3rd electrodeposited coating is formed on the second surface of this trace;
Semiconductor chip is located at this and is put on the brilliant pad, and is electrically connected to this first electrodeposited coating;
Encapsulating material coats the part side surface of this semiconductor chip, the first electrodeposited coating, trace and the part side surface of electrical contact; And
Welding resisting layer covers the part side surface of the 3rd electrodeposited coating, encapsulating material, trace and the part side surface of electrical contact by this second surface side, and has the welding resisting layer perforate that exposes this second electrodeposited coating.
2. encapsulating structure according to claim 1 is characterized in that, put brilliant pad in this and be formed with and be communicated to the brilliant recess of putting of this first surface, and this semiconductor chip is located at this and is put in the brilliant recess.
3. encapsulating structure according to claim 1 is characterized in that, the bottom surface of the 3rd electrodeposited coating flushes with the bottom surface of this encapsulating material.
4. encapsulating structure according to claim 1 is characterized in that, the bottom surface of the 3rd electrodeposited coating protrudes from the bottom surface of this encapsulating material.
5. encapsulating structure according to claim 1 is characterized in that, this semiconductor chip is electrically connected to this first electrodeposited coating by a plurality of bonding wires.
6. the method for making of an encapsulating structure comprises:
Preparation one has the metal loading plate of relative first surface and second surface, and this metal loading plate has puts brilliant pad, forms the first resistance layer on this first surface, and this first resistance layer has the first patterning open region of this metal loading plate of exposed parts;
Remove this metal loading plate in this first patterning open region, and consist of the first recess, and define trace protuberance and electrical contact protuberance;
Remove this first resistance layer;
Form the second resistance layer on this second surface, this second resistance layer has the second patterning open region of this metal loading plate of exposed parts, and the position of this second patterning open region is to should the trace protuberance;
Remove this metal loading plate in this second patterning open region, and consist of the second recess;
Remove this second resistance layer;
On the end face of this trace protuberance and electrical contact protuberance, form the first electrodeposited coating, and on this second surface, form should putting the second electrodeposited coating of brilliant pad and electrical contact protuberance, and in this second recess, form the 3rd electrodeposited coating;
Put on the brilliant pad in this semiconductor chip is set;
This semiconductor chip is electrically connected to this first electrodeposited coating;
On this metal loading plate, form the encapsulating material that coats this semiconductor chip and the first electrodeposited coating;
Remove not this metal loading plate that is covered by this second electrodeposited coating and the 3rd electrodeposited coating from this second surface, and form many traces and a plurality of electrical contact;
Form the welding resisting layer that covers this second electrodeposited coating, the 3rd electrodeposited coating, encapsulating material and metal loading plate from the side of this second surface; And
Remove this welding resisting layer of part, expose the welding resisting layer perforate of this second electrodeposited coating with formation.
7. the method for making of encapsulating structure according to claim 6 is characterized in that, remove this metal loading plate in this first patterning open region and also be included in this and put to consist of in the brilliant pad and put brilliant recess, and this semiconductor chip is located at this and is put in the brilliant recess.
8. the method for making of encapsulating structure according to claim 6 is characterized in that, the bottom surface of the 3rd electrodeposited coating flushes with the bottom surface of this encapsulating material.
9. the method for making of encapsulating structure according to claim 6 is characterized in that, the bottom surface of the 3rd electrodeposited coating protrudes from the bottom surface of this encapsulating material.
10. the method for making of encapsulating structure according to claim 6 is characterized in that, this semiconductor chip is electrically connected to this first electrodeposited coating by a plurality of bonding wires.
11. the method for making of an encapsulating structure comprises:
Preparation one has the metal loading plate of relative first surface and second surface, and this metal loading plate has puts brilliant pad;
Except this metal loading plate of part, consisting of the first recess, and define trace protuberance and electrical contact protuberance from this first surface sidesway;
Except this metal loading plate of part, consisting of the second recess, the position of this second recess is to should the trace protuberance from this second surface sidesway;
Put on the brilliant pad in this semiconductor chip is set;
This semiconductor chip is electrically connected to this trace protuberance and electrical contact protuberance;
On this metal loading plate, form the encapsulating material that coats this semiconductor chip, trace protuberance and electrical contact protuberance;
Remove should putting this metal loading plate of brilliant pad, trace protuberance and electrical contact protuberance from this second surface, and form many traces and a plurality of electrical contact;
Form the welding resisting layer that covers this encapsulating material and metal loading plate from the side of this second surface; And
Remove this welding resisting layer of part, expose the welding resisting layer perforate that this puts brilliant pad and electrical contact with formation.
12. the method for making of encapsulating structure according to claim 11 is characterized in that, put to consist of the brilliant pad and put brilliant recess except this metal loading plate of part also is included in this from this first surface sidesway, and this semiconductor chip is located at this and is put in the brilliant recess.
13. the method for making of encapsulating structure according to claim 11 is characterized in that, this semiconductor chip is electrically connected to this trace protuberance and electrical contact protuberance by a plurality of bonding wires.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100125400A TWI441296B (en) | 2011-07-19 | 2011-07-19 | Package structure and fabrication method thereof |
| TW100125400 | 2011-07-19 |
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| CN102891124A true CN102891124A (en) | 2013-01-23 |
| CN102891124B CN102891124B (en) | 2015-04-15 |
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| TW (1) | TWI441296B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104241232A (en) * | 2013-06-21 | 2014-12-24 | 矽品精密工业股份有限公司 | Quad flat non-leaded package and method for fabricating the same |
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| US20010019854A1 (en) * | 2000-02-29 | 2001-09-06 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
| US6306685B1 (en) * | 2000-02-01 | 2001-10-23 | Advanced Semiconductor Engineering, Inc. | Method of molding a bump chip carrier and structure made thereby |
| US20090230526A1 (en) * | 2008-03-14 | 2009-09-17 | Chien-Wen Chen | Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof |
| US20110042794A1 (en) * | 2008-05-19 | 2011-02-24 | Tung-Hsien Hsieh | Qfn semiconductor package and circuit board structure adapted for the same |
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| US6306685B1 (en) * | 2000-02-01 | 2001-10-23 | Advanced Semiconductor Engineering, Inc. | Method of molding a bump chip carrier and structure made thereby |
| US20010019854A1 (en) * | 2000-02-29 | 2001-09-06 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
| US20090230526A1 (en) * | 2008-03-14 | 2009-09-17 | Chien-Wen Chen | Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof |
| US20110042794A1 (en) * | 2008-05-19 | 2011-02-24 | Tung-Hsien Hsieh | Qfn semiconductor package and circuit board structure adapted for the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104241232A (en) * | 2013-06-21 | 2014-12-24 | 矽品精密工业股份有限公司 | Quad flat non-leaded package and method for fabricating the same |
| CN104241232B (en) * | 2013-06-21 | 2017-05-17 | 矽品精密工业股份有限公司 | Quad flat non-leaded package and method for fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102891124B (en) | 2015-04-15 |
| TW201306201A (en) | 2013-02-01 |
| TWI441296B (en) | 2014-06-11 |
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