TW201236156A - Semiconductor package with reduced on-resistance and top metal spreading resistance with application to power transistor packaging - Google Patents

Semiconductor package with reduced on-resistance and top metal spreading resistance with application to power transistor packaging Download PDF

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Publication number
TW201236156A
TW201236156A TW100142019A TW100142019A TW201236156A TW 201236156 A TW201236156 A TW 201236156A TW 100142019 A TW100142019 A TW 100142019A TW 100142019 A TW100142019 A TW 100142019A TW 201236156 A TW201236156 A TW 201236156A
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TW
Taiwan
Prior art keywords
electrode
semiconductor package
control electrode
resistance
major surface
Prior art date
Application number
TW100142019A
Other languages
English (en)
Inventor
Rupert Burbidge
David Paul Jones
Original Assignee
Int Rectifier Corp
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Filing date
Publication date
Application filed by Int Rectifier Corp filed Critical Int Rectifier Corp
Publication of TW201236156A publication Critical patent/TW201236156A/zh

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Die Bonding (AREA)

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201236156 六、發明說明 相關之申請案 本申請案主張2011年1月10日所申請之命名爲“具 有應用至功率電晶體封裝的半導體封裝中之導通電阻及頂 金屬展布電阻的降低”，序號61Μ60,980的專利審查中 之臨時申請案的權益及優先權。在該專利審査中之臨時申 請案中的發明係全部結合於本申請案之內，以供參考。 【發明所屬之技術領域】 大致地’本發明有關半導體裝置。更特別地，本發明 有關半導體裝置封裝。- 【先前技術】 用於諸如MOSFET之功率裝置的習知封裝設計已強 調客戶集積之容易，做爲主要的商業優點。例如，諸如依 據 International Rectifier Corporation 之 DirectFET®封裝 的許多功率封裝已使用將控制接墊中央地定位於封裝之裝 置晶粒的較短尺寸中之封裝設計。例如，功率封裝可包含 中央疋位於垂直傳導FET之較短尺寸中的閘極接墊。藉 由此封裝所提供之縱向對稱可在當安裝至諸如印刷電路板 (PCB)的支撐表面之上時，促進焊料潤濕力在晶粒接墊上 的平衡。因而，客戶及末端使用者可更容易地以在諸如晶 粒傾斜、豎碑、未對齊、及其他集積誤差的問題上之更少 擔憂’而集積封裝之功率裝置。 201236156 不幸地，該控制接墊之中央定位會顯示若干缺點。一 缺點在於中央定位之控制接墊經常需要在晶粒上保留額外 的空間於該控制接墊周圍，以遵從用於可製造性及可靠度 之指明晶粒接墊與封裝邊界間的最小間隙之最佳實用設計 規則。另一缺點在於該封裝顯示由於阻隔電流流動之中央 閘極位置所造成之增大的頂金屬展布電阻，而不利地增加 整體裝置的導通電阻。 在過去，該頂金屬展布電阻僅占整體封裝之導通電阻 的小部分。然而，在封裝設計中之持續的發展和精製已降 其他因子對於功率封裝之整體導通電阻的貢獻，而致使該 頂金屬展布電阻藉以成爲封裝導通電阻之極大的比率。因 此，降低頂金屬展布電阻係目前之極爲迫切的問題。 雖然一提議之解決方法將使晶粒接墊上之頂金屬層變 厚以減輕展布電阻之效應，但該解決方法會非所欲地添加 成本且增加封裝之高度及形式因子。另一提議之解決方法 則將增加源極接墊的表面面積。惟，該解決方法會與如上 述之指明最小接墊間隙的最佳實用設計規則相互牴觸。 因此，爲了要符合對於改善之裝置效率及性能的商業 需求，需要獨特之成本有效解決方法以供降低頂金屬展布 電阻之用，且可藉以降低半導體封裝之整體的導通電阻， 尤其是功率電晶體封裝，而仍可堅守最佳實用設計規則。 【發明內容】 具有降低導通電阻及頂金屬展布電阻的應用至功率電 -6- 201236156 晶體封裝的半導體封裝係實質地如圖式之至少一者所示及 /或如與該等圖式之至少一者結合所述，且更完整地，係 如申請專利範圍中所陳明。 【實施方式】 本申請案係針對具有降低導通電阻及頂金屬展布電阻 的應用至功率電晶體封裝的半導體封裝。以下說明包含屬 於本發明之實施的特定資訊。熟習於本項技藝之人士將認 知的是’本發明可以以與本申請案中所特別討論之方式不 同的方式來加以實施。此外，爲不使本發明混淆，將不討 論本發明之特定的細節。惟’並未在本申請案中所敘述之 特定的細節係落在熟習於本項技藝之一般人士的知識之 內。 在本申請案中之圖式及其伴隨的詳細說明僅係針對本 發明之代表性實施例。爲了要維持簡明性，其中使用本發 明原理之本發明的其他實施例並不予以特別地敘述於本申 請案中，且亦不藉由本申請案之圖式來加以特別地描繪。 第1A圖描繪習知之半導體封裝的透視圖。第ία圖 之圖式100顯示包含導電夾128及FET裝置的封裝，該 FET裝置包含閘極接墊12〇、閘極匯流排122、和源極接 墊l26a及126b。雖然在圖式中所顯示之實例使用單一 FET做爲代表性封裝裝置，但亦可使用諸如二極體、 IGBT、或多重共同封裝之裝置的其他裝置組態。 第1A圖中所示之封裝的 FET可對應至來自 201236156
International Rectifier 所販售之 Hex 3 MX 晶粒。如第 ΙΑ 圖中所示地，封裝係組構使得在相反的主表面上之電極可 無需接合線地連接至平面支撐表面，如所讓渡給 Interational Rectifier之美國專利第6,624,522號中所敘述 地，而該發明將全部地結合於本文以供參考。更特別地， 假定晶粒（未顯示）的相反主表面包含與導電夾128接觸之 汲極接墊，則包含來自閘極接墊1 2 0的閘極、來自源極接 墊126a及126b的源極、以及來自導電夾128的汲極可藉 由焊料來直接機械性地且電性地附著至諸如印刷電路板 (PCB)之平面支撐表面，而無需使用接合線。由於包含可 接納裝置晶粒之扁平腹板部及可延伸自該扁平腹板部的邊 緣之周邊邊緣部的導電夾128之形狀，所以該直接附著可 連接汲極電極至平面支撐表面。 如第1 A圖中所示地，閘極接墊1 20係習知地定位於 晶粒之較短尺寸的中央，以使末端使用者之集積容易。閘 極接墊1 20亦連接至閘極匯流排1 22，而該閘極匯流排 122係在較長尺寸中跨越晶粒中央而延伸。第1A圖中所 示之封裝可視爲用於展布電阻測量模型的控制封裝，而所 測量出之頂金屬展布電阻被設定爲1 00%。用於第1 A至 1 D圖之代表性展布電阻測量模型可以以以下參數而組 構： 201236156 材料 電阻率（Ωιη) 厚度（|im) X Y z 焊料 1.45E-07 (X, Υ, Z) 90 銘(頂金屬） 2.56E-08 (X, Y, Z) 4 FET通道 〇〇 〇〇 0.665 1.5 矽 1.40E-05 (X, Y, Z) 200 黏晶 1.00E-06 (X, Y, Z) 30 導電夾(銅） 1.70E-08 (X, Y, Z) 250 第1表:用於展布電阻測量模型的典型參數》 其次，第1B、1C、及1D圖描繪依據本發明實施例 之半導體封裝的透視圖。首先，請翻閱至第1B圖，所影 響的改變係閘極接墊120在晶粒的可見主表面上之自中央 位置至轉角位置的位移。依據所施加至第1A及1B圖的 封裝組態之第1表中的上述測量模型之測試結果，至轉角 之閘極接墊的位移單獨地降低頂金屬展布電阻至大約 82%，亦即，約略降低1 8%。 請翻閱至第1C圖，因爲在第1B圖中之閘極接墊120 的位移未能連接閘極接墊1 20至閘極匯流排1 22，所以第 1C圖的封裝添加金屬分節121而延伸跨越晶粒，以連接 閘極接墊120至閘極匯流排122。第1C圖中所示的封裝 之所測量出的頂金屬展布電阻亦大約係控制封裝之所測量 出之電阻的8 2 %。 請翻閱至第1D圖，閘極接墊120的縱橫比係修正使 得閘極接墊1 20至少半途地延伸跨越該可見主表面的較短 尺寸。在此方式中，對閘極匯流排122的直接連接係無需 第1C圖之金屬分節121而被建立。在第1C圖與第1D圖 之間的閘極接墊1 20之表面面積可保持相似，而僅修正閘 極接墊1 20的縱橫比。在上述展布電阻測量模型下之第 -9 - 201236156 1 D圖中之封裝的測試產生控制封裝.之所測量出電阻之 7 8%的展布電阻，而自第1C圖之設計大約改善3%。 因此，來自上述展布電阻測量模型之結果說明的是， 並非在晶粒之較短尺寸的中央，而是在轉角中之閘極接墊 的定位可降低頂金屬展布電阻大約1 8 %，且使得閘極接墊 至少半途地延伸跨越晶粒的較短尺寸之閘極接墊縱橫比的 重訂尺寸可進一步降低該頂金屬展布電阻大約3%。 既然已明白轉角之閘極接墊定位在頂金屬展布電阻上 的功效，則雙層金屬（DLM)之頂金屬及各式各樣之晶粒接 墊配置可結合第2八、28'2(：、20、2£、及2?圖而予以 探討。請翻閱至第2A圖，第2A圖描繪使用其中可包含 0.6微米厚度之鋁的單層金屬（SLM)於頂金屬之習知半導 體封裝的透視圖。第2A之圖式200包含閘極接墊220, 閘極匯流排 222，源極接墊 224a及 224b，和導電夾 22 8。與第1 A圖相似地，第2A圖中所示之半導體封裝亦 可被使用做爲測試控制，且亦可包含來自International Rectifier所販售之Hex 3 MX晶粒。閘極接墊220可具有 1.01x0.91mm(毫米）的尺寸，源極接墊224a及224b可各 自地具有0.82x1.4〇mm的尺寸，以及閘極匯流排222可具 有114微米的寬度。用於第2A至2F圖之代表性展布電 阻測量模型可以以以下參數而組構： -10- 201236156 材料 電阻率 （Ωιη) X Υ Ζ 厚度（μιη) 焊料 1.45Ε-07 (X，Υ，Ζ) 90 鋁(頂金屬） 2.56Ε-08 (X, Υ, Ζ) SLM:6 DLM: 1.5 及 8 FET通道 ~ 〇〇 0.00481 1.5 (R*AA = lOmQinm2) 矽 1.40E-05 (X, Υ, Ζ) 200 黏晶 1.00Ε-06 (X, Υ, Ζ) 30 導電夾(銅） 1.70Ε-08 (X, Υ, Ζ) 250 第2表:用於展布電阻測量模型的典型參數。 第2C，2D，2E，及2F圖描繪依據本發明實施例之 半導體封裝的透視圖。請自第2A圖翻閱至第2B圖，現 在該半導體封裝使用雙層金屬（DLM)於頂金屬，而非使用 單層金屬（SLM)。更特別地，1.5微米的第一金屬厚度係 使用於閘極接墊220，以及8微米的第二金屬厚度係使用 於閘極匯流排，該閘極匯流排可跨越各自晶粒的較長尺寸 而延伸，但爲接墊配置之簡明起見，其係自第2B至2F 圖省略。當施加上述之展布電阻測量模型至第2A至2B 圖時，則第2A圖之半導體裝置封裝顯示〇·143πιΩ (毫歐 姆）的頂金屬展布電阻及1.097ιηΩ的總裝置電阻，而第2Β 圖之半導體裝置封裝顯示Ο.ΙΙΙιηΩ的頂金屬展布電阻及 0.9 9 7ιηΩ的總裝置電阻。從而，可瞭解的是，與相同晶粒 之SLM頂金屬組態相較地，該模型說明DLM頂金屬組 態可降低頂金屬展布電阻及導通電阻二者》 請自第2Β圖翻閱至第2C圖，半導體封裝現在取代 地使用轉角安置以供閘極接墊220之用，且使源極接墊 224a及224b的表面面積最大化。更特別地，可將源極接 墊224a的表面面積增加至1.19x1.99mm，且可將源極接 -11 - 201236156 墊224b的表面面積增加至1.19x3.44mm。當施加上述之 展布電阻測量模型至第2C圖時，則第2C圖之半導體裝 置封裝顯示〇.〇16ηιΩ的頂金屬展布電阻及0.890πιΩ的總 裝置電阻。因此，可觀察到頂金屬展布電阻急劇地降低至 比藉由第2Β圖的半導體裝置封裝所獲得之結果的1 5%更 小，且總裝置電阻亦進一步地降低》從而，與習知之定位 中央的閘極接墊組態及用於源極接墊之較小的表面面積相 較地，該模型說明轉角閘極接墊組態及用於源極接墊之較 大的表面面積可降低頂金屬展布電阻及導通電阻二者。不 幸地，源極接墊224a及224b之較大的表面面積及不平衡 和不對稱的接墊配置可使第2C圖之裝置封裝難以處理， 且當附著至支撐表面時，容易引起嚴重的集積誤差。 因此，請自第2C圖翻閱至第2D圖，半導體封裝回 到閘極接墊220之標準的中央安置，且取代地使用複數個 間隔接墊224a、224b、224c、224d、及224e以代替源極 接墊之兩個大的接墊。如第2D圖中所示地，閘極及源極 接墊係以2列x3行之格柵圖案而配置，但該等接墊可根 據特定封裝尺寸及其他參數，而以諸如2列x2行之格柵 圖案、3列x3行之格柵圖案、或任一另外之組態的任何所 欲方式來予以配置。閘極接墊220的尺寸亦被縮減至〇.6x 0.6mm，而提供距離圍繞的源極接墊2 2 4a至2 24e之更大 的間隙餘隙。源極接墊224a及22 4b係定尺寸爲1.19x 0.719mm，而源極接墊224c、224d、及224e則定尺寸爲 1.19x0.8 8mm。在第 2D圖中的半導體封裝之對稱和平衡 -12- 201236156 的配置以及合理尺寸的晶粒接墊可促進支撐表面上之容易 的集積。此外，當施加上述之展布電阻測量模型至第2D 圖時，則第2D圖之半導體裝置封裝顯示Ο.ΟΙΙπιΩ的頂金 屬展布電阻及〇.847m Ω的總裝置電阻。從而，可觀察到 的是，該模型說明第2D圖中的該等接墊之平衡的間隔接 墊組態仍可提供降低的頂金屬展布電阻及導通電阻，且同 時保持習知封裝設計之容易集積的優點。 請自第2D圖翻閱至第2E圖，閘極接墊220被移至 轉角位置，且源極接墊224 a及224b係重訂尺寸成爲與源 極接墊224c、224d、及224e的表面面積相同。當施加上 述之展布電阻測量模型至第2E圖時，則第2E圖之半導 體裝置封裝顯示〇.〇15ιηΩ的頂金屬展布電阻及〇·852ιηΩ 的總裝置電阻。雖然相較於第2D圖的結果，該頂金屬展 布及導通電阻係輕度地增加，但相較於第2Β圖的結果， 則整個的頂金屬展布及導通電阻仍係大大地降低。該輕度 的增加可歸因於源極接墊224a至224e在裝置晶粒上之輕 微的不均勻分佈。 請自第2E圖翻閱至第2F圖，源極接墊224a至224e 係重訂尺寸成爲1.15x0.65mm之較小的表面面積，而提供 更大的間隙間隔於接墊之間。該更大的間隙間隔可完成第 2F圖之容納半導體裝置封裝的支撐表面上之複數個通孔 的定位。更明確地說’在將半導體裝置封裝焊接至平面支 撐表面之後，可使用半導體裝置的該等接墊下面及之間的 平面支撐表面中所設置之通孔。例如，通孔的使用可提供 -13- 201236156 半導體裝置封裝增強之電和熱的性能。當施加上述之展布 電阻測量模型至第2F圖時，則第2F圖之半導體裝置封裝 顯示0.024ηιΩ的頂金屬展布電阻及0.859ηιΩ的總裝置電 阻。雖然相較於第2Ε圖的結果，該頂金屬展布及導通電 阻係輕度地增加，但相較於第2Β圖的結果，則整個的頂 金屬展布及導通電阻仍係大大地降低。該輕度的增加可歸 因於源極接墊224a至224e在裝置晶粒上之稍微較小的表 面面積。 既然已明白雙層金屬（DLM)頂金屬及各式各樣晶粒接 墊配置在頂金屬展布電阻及裝置導通電阻上的功效，第 3 A及3 B圖將探討實際製造各式各樣晶粒接墊配置，且同 時堅守最佳實用設計規則及對於目標設計及市場之大致可 接受的製造容許誤差之可行性。 第3A圖描繪依據本發明實施例之半導體封裝的槪略 視圖。半導體裝置封裝 3 1 0a、3 1 Ob、3 1 0c、3 1 0d、及 310e可各自包含例如，來自International Rectifier所販 售之 DirectFET®中型尺寸封裝，各自封裝具有 4.60x 3.90mm的內部晶粒接納區域，而該區域被縮減爲4.20x 3.50mm以提供至少200微米的足夠間隙於導電夾的壁邊 緣之間。此外，爲了可製造性之緣故，應將接墊定位於距 離導電夾的壁邊緣至少300微米處。在接墊間之X及Y 軸中的0.4mm及Z軸中的0.6 m m之最小間隙可加以實 施，而使通孔能安置於接墊之間。因而，半導體裝置封裝 3 1 0a至3 1 0e顯示順從上述設計考慮之各式各樣代表性的 -14- 201236156 晶粒接墊組態，而半導體裝置封裝3 1 0c及3 1 0d則專注於 進一步縮減之接墊尺寸。 請翻閱至第3B圖。第3B圖描繪用以接納第3A圖的 半導體封裝之支撐表面的槪略視圖。支撐表面 312a， 312b，312c，312d，及312e指示平面支撐表面上之要分 別接納第3A圖的半導體裝置封裝310a，3 10b，310c， 3 1 0 d，及3 1 0 e之所需的銅軌跡。如極小尺寸之間隙 314a(0.05mm)及間隙 314b(0.10mm)所示地，支撐表面 3 12a及3 12e之所需的軌跡組態要求製造精確度，而該製 造精確度可能不易達成且需至少〇.15mm之間隙於銅軌跡 之間。從而，使用目前技術之製造配合並非有利於半導體 裝置封裝3 1 0a及3 1 0e的接墊組態，且因此，可對半導體 裝置封裝3 1 Ob的接墊組態提出接納該封裝之對應平面支 撐表面的即時製造。 因而，已敘述包含半導體裝置之半導體裝置封裝，該 半導體裝置具有在相反的主表面上之電極，可無需接合線 而連接至平面支撐表面，以及在轉角位置中所設置的控制 電極，用以降低頂金屬展布電阻。藉由移動控制電極至轉 角位置，則可使用晶粒表面區域的更大部分於頂金屬，因 爲僅控制電極之兩個側邊必須與源極接墊間隔開，而非三 個側邊，該頂金屬展布電阻可藉以降低。縮減閘極接墊的 尺寸可進一步增加可用於頂金屬之區域，而亦降低頂金屬 展布電阻。藉由以格柵方式而將源極及閘極接墊間隔開， 則可進一步減少頂金屬展布電阻，且同時維持具有平衡及 -15- 201236156 對稱接墊組態的習知封裝設計之容易集積的優點。藉由增 加該格柵之間隔，亦可將通孔設置於接納半導體裝置封裝 之平面支撐表面中的晶粒接墊之間。藉由謹慎地遵守用於 可製造性及可靠度之最佳實用設計規則，則可透過由於頂 金屬展布電阻的降低所造成之降低的裝置導通電阻，而低 成本及高產能效率地，且同時仍增進裝置性能地製造出該 等半導體裝置封裝》 從上述本發明之說明顯示的是，可使用各式各樣的技 術以供實施本發明的槪念之用，而不會背離其範疇。此 外，雖然已特定地參照一些實施例來敘述本發明，但熟習 於本項技藝之一般人士將認知的是，可在形式及細節中做 成改變而不會背離本發明之精神及範疇。例如，所描述之 實施例將在各方面被視爲係描繪性且並非限制性。而且， 應瞭解的是，本發明並未受限於本文中所敘述之該等特定 的實施例，而是具有並未背離本發明範疇之許多的重新配 置例、修正例、及取代例。 【圖式簡單說明】 第1 A圖描繪習知之半導體封裝的透視圖； 第IB，1C及1D圖描繪依據本發明實施例之半導體 封裝的透視圖。 第2A圖描繪習知之半導體封裝的透視圖，該習知之 半導體封裝使用單層金屬（SLM)以供頂金屬之用； 第2B圖描繪習知之半導體封裝的透視圖，該習知之 -16- 201236156 半導體封裝使用雙層金屬（DLM)以供頂金屬之用； 第2C ’ 2D ’ 2E，及2F圖描繪依據本發明實施例之 半導體封裝的透視圖； 第3A圖描繪依據本發明實施例之半導體封裝的槪略 視圖， 第3B圖描繪用以接納第3A圖的半導體封裝之支撐 表面的槪略視圖。 【主要元件符號說明】 100， 200 ， 300 ：圖式 120，220 :閘極接墊 122，222 :閘極匯流排 126a ， 126b ， 224a ， 224b ， 224c ， 224d，224e :源極接墊 128，228 ：導電夾 1 2 1 :金屬分節 310a，310b，310c > 310d、310e:半導體裝置封裝 312a，312b，312c，312d、312e:支撐表面 314a ， 314b :間隙

Claims (1)

  1. 201236156 七、申請專利範園 1. —種半導體封裝，包含： 半導體裝置，具有第一主表面及第二主表面，該第一 主表面包含第一電極，及該第二主表面包含第二電極和控 制電極， 其中該控制電極係設置於該第二主表面的轉角；且 其中該.第一電極、該第二電極、及該控制電極係可電 性連接至平面支撐表面，而無需接合線。 2. 如申請專利範圍第1項之半導體封裝，其中該第 二電極包含複數個間隔接墊。 3 ·如申請專利範圍第2項之半導體封裝，其中該半 導體封裝係焊接至該平面支撐表面，該平面支撐表面具有 複數個通孔，該複數個通孔係設置在該複數個間隔接墊之 間。 4. 如申請專利範圍第1項之半導體封裝，其中該第 二電極及該控制電極形成格柵圖案於該第二主表面上。 5. 如申請專利範圍第1項之半導體封裝，其中該第 二電極及該控制電極形成格柵圖案於該第二主表面上，該 格柵圖案包含至少二列及至少二行。 6. 如申請專利範圍第1項之半導體封裝，其中該半 導體裝置包含場效應電晶體（FET)。 7. 如申請專利範圍第1項之半導體封裝，其中該第 一電極係汲極電極，該第二電極係源極電極，以及該控制 電極係閘極電極。 •18- 201236156 8 .如申請專利範圍第1項之半導體封裝，其中該控 制電極至少中途跨越該第二主表面的較短尺寸而延伸。 9. 如申請專利範圍第1項之半導體封裝，進一步包 含閘極匯流排，該閘極匯流排係連接至該控制電極，且跨 越該第二主表面的較長尺寸而設置。 10. 如申請專利範圍第1項之半導體封裝，其中該第 一電極、該第二電極、及該控制電極係使用焊料而電性且 機械性地連接至該平面支撐表面上之複數個軌跡。 11. —種半導體封裝，包含： 導電夾，具有扁平腹板部，及至少一周邊邊緣部，該 至少一周邊邊緣部係延伸自該扁平腹板部的邊緣；以及 半導體裝置，具有第一主表面及第二主表面，該第一 主表面包含電性連接至該腹板部之第一電極，及該第二主 表面包含第二電極和控制電極， 其中該控制電極係設置於該第二主表面的轉角；且 其中該至少一周邊邊緣部，該第二電極，及該控制電 極係可焊接至平面支撐表面。 12. 如申請專利範圍第11項之半導體封裝，其中該 第二電極包含複數個間隔接墊。 13. 如申請專利範圍第12項之半導體封裝，其中該 半導體封裝係焊接至該平面支撐表面，該平面支撐表面具 有複數個通孔，該複數個通孔係設置在該複數個間隔接墊 之間。 14. 如申請專利範圍第11項之半導體封裝，其中該 -19- 201236156 第二電極及該控制電極形成格柵圖案於該第二主表面上。 15. 如申請專利範圍第1 1項之半導體封裝，其中該 第二電極及該控制電極形成格柵圖案於該第二主表面上， 該格柵圖案包含至少二列及至少二行。 16. 如申請專利範圍第11項之半導體封裝，其中該 半導體裝置包含場效應電晶體（FET)。 17. 如申請專利範圍第11項之半導體封裝，其中該 第一電極係汲極電極，該第二電極係源極電極，以及該控 制電極係閘極電極。 18. 如申請專利範圍第11項之半導體封裝，其中該 控制電極至少中途跨越該第二主表面的較短尺寸而延伸。 19. 如申請專利範圍第1 1項之半導體封裝，進一步 包含閘極匯流排，該閘極匯流排係連接至該控制電極，且 跨越該第二主表面的較長尺寸而設置。 20. 如申請專利範圍第11項之半導體封裝，其中該 第一電極、該第二電極、及該控制電極係使用焊料而電性 且機械性地連接至該平面支撐表面上之複數個軌跡。 -20-
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CN104641459A (zh) * 2013-01-25 2015-05-20 富士电机株式会社 半导体装置
CN104641459B (zh) * 2013-01-25 2017-08-11 富士电机株式会社 半导体装置

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