TW201220465A - Multi-chip stack package structure - Google Patents
Multi-chip stack package structure Download PDFInfo
- Publication number
- TW201220465A TW201220465A TW099138064A TW99138064A TW201220465A TW 201220465 A TW201220465 A TW 201220465A TW 099138064 A TW099138064 A TW 099138064A TW 99138064 A TW99138064 A TW 99138064A TW 201220465 A TW201220465 A TW 201220465A
- Authority
- TW
- Taiwan
- Prior art keywords
- wafer
- semiconductor
- stacked
- carrier
- package structure
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/24146—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Description
201220465 六、發明說明: 【發明所屬之技術領域】 本發明是有關於一種晶片封裝結構’更詳而言之,是 關於一種防止導電膠發生斷路現象的晶片封裝結構改良。 【先前技術】 於晶片封裝製程中,晶片可藉由點膠技術而與基板完 成電性連接,再由封裝膠體包覆晶片而完成封裝。於第 20080303131、20090068790 及 20090230528 號美國專利公 開案中’皆已揭示之一種多晶片堆疊結構,舉例說明,請 參閱第1圖及第2圖所繪示,分別係為習知多晶片堆疊結 構之局部剖視圖及習知晶片封裝結構之局部俯視圖,於習 知多晶片堆疊結構中,基板1 〇中設置有複數電性連接墊 11,且基板10開設有曝露出電性連接墊U之開窗12,於 各晶片20上貼附有絕緣膠30’且各晶片20係以不妨礙電 性連接墊11之點膠作業為原則下,堆疊於基板10上,導 電膠40電性連接基板10之電性連接墊丨丨及各晶片20之 電極墊21,且導電膠40之一部分係填入於開窗12中。 惟,於習知晶片封裝結構中,由於基板1〇的表面不 完全平整,使得介於最底層晶片20及基板1〇之間的絕緣 膠30厚度需要較厚,(如第1圖所示),使得最底層晶片 20的電極墊21與基板10的電性連接墊11之間的高度落 差過大,於施行點膠作業後,令導電膠40在此處造成頸縮 的現象,或者由於毛細原理’使呈半液態之導電膠40填入 於開窗12中之部分,非常容易從開窗12之鄰近電性連接 4 111797 201220465 墊11處,溢流至開窗12之遠離電性連接墊11處,因而產 生膠寬頸縮效應,此效應令導電膠40在基板10與最底部 晶片20之間處產生如烘烤後發生之斷點或斷膠情況而導 致的電性斷路現象,使晶片封裝結構之導電性不良,如此, 會造成產品損壞或需重新點膠之問題,令產品良率及可靠 度降低。 綜上所述,如何提出一種可解決上述習知技術之缺失 之多晶片堆疊封裝結構,以防止導電膠發生斷路現象,實 為目前亟欲解決之技術問題。 【發明内容】 鑒於上述習知技術之缺點,本發明之主要目的在於提 供一種多晶片堆疊封裝結構,防止導電膠發生頸縮而導致 電性斷路,進而提升產品良率及可靠度。 為達上述及其他目的,本發明提供一種多晶片堆疊封 裝結構,係包括:晶片承載件,於該晶片承載件上設置有 至少一電性連接墊;複數個半導體晶片,各該半導體晶片 具有作用面及非作用面,且彼此以作用面朝上自該電性連 接墊旁依序以錯位方式堆疊於該晶片承載件上,以使各該 半導體晶片至少一部分之作用面係外露於堆疊其上之半導 體晶片’且各該經堆豐之該半導體晶片的外露作用面上設 有至少一電極墊;絕緣膠,設於該些半導體晶片之間及該 與晶片承載件黏接之半導體晶片與該晶片承載件之間;以 及導電膠,用以電性連接該電性連接墊及各該半導體晶片 上之電極墊,以藉由該導電膠使該等半導體晶片均電性連 5 111797 201220465 接該晶片承載件,其中,該晶片承載件上形成有拒銲層, 且該拒銲層開設有外露部分電性連接墊之開窗,以令外露 之該電性連接墊的輪廓,在鄰近該半導體晶片處向遠離該 半導體晶片處縮小。 在前述之多晶片堆疊封裝結構中,該晶片承載件為電 路板,又各該半導體晶片彼此以作用面朝上自該電性連接 墊旁依序以錯位方式堆疊於該晶片承載件上。更具體而 言,該等半導體晶片彼此以階梯狀方式或鋸齒狀方式堆 疊。惟,不論以何種方式堆疊,該與晶片承載件黏接之底 部半導體晶W之電極墊旁之晶片承載件上係設有電性連接 塾。 此外,本發明之多晶片堆疊封裝結構中,透過在晶片 承載件上形成之拒銲層,開設有外露部分電性連接墊之開 窗,以令外露之該電性連接墊的輪廓在鄰近該半導體晶片 處向遠離該半導體晶片處縮小。舉例而言,該開窗之形狀 係可為,但不限於梯形、τ字形、三角形、半圓形、半橢 圓形之其中之一者。 相較於習知技術,本發明之多晶片堆疊封裝結構,基 於供該導電膠附著其上之該電性連接墊的輪廓,在鄰近該 半導體晶片處向退離該半導體晶片處縮小’此時,由於自 然毛細原理,電性連接墊上之導電膠會依據所接觸之電性 連接墊外形,限制並防止呈半液態之導電膠向遠離半導體 晶片處溢流,使得膠寬緊縮效應減輕,防止導電膠在晶片 承載件與半導體晶片之間處如烘烤後發生之斷點或斷膠情 6 111797 201220465 - 況而導致的斷路現象,如此,不會造成產品損壞或需進行 . 重新點膠之問題,而能提升產品良率及可靠度。 【實施方式】 以下是藉由特定的具體實例說明本發明之技術内容, 熟悉此技藝之人士可由本說明書所揭示之内容輕易地瞭解 本發明之其他優點與功效。 須知’本說明書所附圖式所繪示之結構、比例、大小 等’均僅用以配合說明書所揭示之内容,以供熟悉此技藝 籲之人士之瞭解與閱讀,並非用以限定本發明可實施之限定 條件,故不具技術上之實質意義,任何結構之修都、比例 關係之改變或大小之調整,在不影響本發明所能產生之功 效及所能達成之目的下,均應仍落在本發明所揭示之技術 内容得能涵蓋之範圍内。 本發明提供一種多晶片堆疊封裝結構(Multi
Stacked-Die Packaging Structure),請參照第 3 圖及第 籲4圖所繪示,分別係為本發明之多晶片堆疊封裝結構之局 部侧剖視圖及局部俯視圖,於本實施例中,該多晶片堆疊 封裝結構包括晶片承載件剛、複數個半導體晶片_、絕 緣膠300及導電膠4〇〇。 a曰片承载件1〇0係例如為電路板,於晶片承載件1〇〇 上設置有至少-電性連接墊11〇,其具有導電性質,又該 電性連接墊11G曝露於該晶片承載件⑽之上方空間。 曰曰片係例如為主動式晶片,如中央處理器 晶片、快閃記憶體晶片、邏輯處理晶片;亦可為被動式晶 111797 7 201220465 片’如晶片式電容、晶片式電阻等,且各該半導體晶片200 具有作用面及非作用面,並於該半導體晶片200的作用面 上設有至少一電極墊210,又該絕緣膠300設於該些半導 體晶片200之間,較佳地,該絕緣膠300預先貼附於各該 半導體晶片200之非作用面,該絕緣膠300可例如為晶片 接著層(Die Attach Film, DAF),但不以此為限制,且各 該半導體晶片200彼此以作用面朝上及自該電性連接墊 110旁依序以錯位方式堆疊於該晶片承載件100上,以使 各該半導體晶片200至少一部分之作用面係外露於堆疊其 上之半導體晶片200。復進一步說明,該等半導體晶片200 的平面尺寸約略相同,該與晶片承載件100黏接之半導體 晶片200設置在鄰近該電性連接墊110之位置,上層之該 等半導體晶片200則分別以一預先設定的距離依序偏移下 層之該半導體晶片200而相互堆疊,且該等半導體晶片200 不致遮蔽相鄰接晶片之電極塾210及晶片承載件100之該 電性連接墊110。 故如前述,該經堆疊之各該半導體晶片200的外露作 用面上具有至少一電極墊210,且該電性連接墊110設於 該晶片承載件100上之位置係對應於該與晶片承載件100 黏接之半導體晶片200之電極墊旁。詳言之,係於各該半 導體晶片200上對應該電性連接墊110之同側處設置有至 少一電極墊210,且該電極墊210曝露於相鄰該半導體晶 片200之上方空間,意即上層之該半導體晶片200不致遮 蔽下層之該半導體晶片的該電極墊210,此時,該電性連 8 111797 201220465 接塾110係設置於該黑Η e i U 200 ^ 承載件l〇0上未黏接該半導體晶 片200之區域,该電極墊? η 係設置於該半導體晶片2〇〇 上未堆疊其他斜導體晶片2⑽之區域。 進#詳細說明該絕緣膠綱的設定 態,該絕緣膠300介於哕日u 罝及…稱t ^^^ιηηΑΑ "於°亥曰曰片承載件100及疊接在該晶片 ㈣半導體晶片2⑽之間,亦即,該絕緣勝300 3於該晶片承載件⑽及疊接在該晶片承載件剛的該
半導體晶片2GG之間’其用以將該晶片承载件⑽及該底 部半導體晶片2GG相互黏合而固定,並加以阻斷其之間的 電性連接,且同時,該絕緣膠3〇〇介於任二相疊接的該半 導體晶片200之間,亦即,該絕緣膠3〇〇復黏接於任二相 疊接的該半導體晶片200之間,其用以將該等半導體晶片 200相互黏合而固定,並加以阻斷其之間的電性連接。 此外’由於該晶片承載件1〇〇之表面不完全平整,令 介於該晶片承載件1〇〇及該底部半導體晶片2〇〇之間的該 絕緣膠300 ’其厚度需較厚,例如,25 // m,但不以此數值 為限定,而介於任二相疊接的該半導體晶片200之間的絕 緣膠300厚度相對上則可較薄,例如,1〇 Am,但不以此數 值為限定’此時,介於該晶片承載件100及疊接在該晶片 承載件100上的該半導體晶片200之間的絕緣膠300厚度 大於任二相疊接的該半導體晶片200之間的絕緣膠300厚 度。 導電膠400係以點膠方式而電性連接電性連接墊110 及各該半導體晶片200上之電極墊210,以藉由該導電膠 9 111797 201220465 400使該等半導體晶片200均電性連接該晶片承載件100, . 其中,供該導電膠400附著其上之該電性連接墊110的輪 廊》在鄰近該半導體晶片200處向遠離該半導體晶片200 處縮小,如第4圖所示。 在本實施例中,供該導電膠400附著其上之該電性連 接塾110的輪廊’在鄰近該半導體晶片200處向退離§亥半 導體晶片200處縮小之特徵,係透過在晶片承載件100上 形成有拒銲層130,且該拒銲層130開設有外露部分電性 連接墊110之開窗140,以令外露之該電性連接墊110的 # 輪廓,在鄰近該半導體晶片200處向遠離該半導體晶片200 處縮小。舉例而言,該開窗140之形狀係可如第5圖所示 之梯形、T字形、三角形、半圓形、半橢圓形之其中之一 者,但不以此些形狀為限。又,當開設有複數個開窗140 時,依據需求條件,此些開窗140之形狀可為相同或不同, 當形狀不同時,可加速辨識電性連接墊110之數目及位置。 此外,如第3圖所示,本發明之多晶片堆疊封裝結構 復可包括絕緣塗層600。該絕緣塗層600塗佈於該等半導 體晶片200或該晶片承載件100之外表,令整體結構對外 界之絕緣性更佳,即於電氣上更為安全,該絕緣塗層600 可為如聚對二曱苯(Parylene)之材質,且因具有固形性 質,使得堆疊結構的強度較佳,並且,該絕緣塗層600可 例如以雷射加工方式,而開設有複數窗孔6L0,又該等窗 孔610分別對應於該開窗140及該等電極墊210位置,使 得該開窗140及該等電極墊210不致被該絕緣塗層600所 10 111797 201220465 覆盍。 請參照第6圖及第圖所繪示’分別係本發明之多曰 堆疊封裝結構的其他實施例。 夕㈤ 如第6圖所示,該多晶片堆疊封裝結構係包括至少一 個半導體晶片200’各該半導體晶片200彼此以作用 上自該電性連接塾110旁依序以錯位方式堆叠於該曰 載件100上。具體而言,該等半導體晶片咖彼^^梯 狀方式堆疊’因此’形成單邊懸空之階梯狀晶片堆最纟士 1 如第7圖所示,該多晶片堆疊封裝結構係包括 導體晶片2GG’其中’該等半導體晶片咖彼此以 方式堆疊’但供該導電膠4GG附著其上之該電性 的輪廓’在鄰雜半導體晶片2〇〇處向遠_ 200處縮小,使得膠寬緊縮效應減輕,防止導電膠股曰曰片 承載件與半導體晶片之間處如烘烤後發生之斷點或=片 況而導致的斷路現象。 尺辦修馆 此外,如第6及7圖所示,本發明之多晶片堆最 結構復包括封裝樹脂500,覆蓋該晶片承载件ι〇 _ 晶片_、絕緣膠及導轉·,俾^^ ^有的保護該多^堆疊料結構不受外界=== 提升女全性,其中,其覆蓋方式兄 展 _,本發㈣晶==:二 =附著其上之該電性連接塾的輪靡,“ 曰曰片處向遠離該半導體晶片處縮小 ° +導體 原理’電性連触以冑冑 綠 ☆自然毛細 膠會依據所接觸之電性連接塾 111797 201220465 外形,限制並防止呈半液態之導電膠向遠離半導體晶片處 溢流,使得膠寬緊縮效應減輕,防止導電膠在晶片承载件 與半導體晶片之間處如烘烤後發生之斷點或斷膠情況而導 致的斷路現象’如此,不會造成產品損壞或f進行重新點 膠之問題,而能提升產品良率及可靠度。 上述實施例僅例示性說明本發明之原理及其功效,而 非用於限制本發明。任何熟習此項技藝之人士均可在不、λ 背本發明之精神及範訂,對上述實施例進行修飾血^ 變。因此,本發明之權利保護範圍,應如後述之申浐 範圍所列。 【圖式簡單說明】 第1圖係為習知多晶片堆疊結構之局部側剖視圖. 第2圖係第i圖習知多晶片堆疊結構之局部俯視圖; 第3圖係為本發明之多晶片堆疊封裝結構之局部剖視 圖; 第4圖係第3圖之多晶片堆疊封裝結構之局部俯視圖 其中,第4圖係省略視需要而塗佈地絕緣塗層; 第5圖係為本發明多晶片堆疊封裝結構之外露之 連接墊輪廓示意圖; 第6圖係為本發明之階梯狀多晶片堆疊封裝結構之八 意圖;以及 示 第7圖係為本發明之鋸齒狀多晶片堆疊封裝結構之八 意圖。 丁 【主要元件符號說明】 111797 12 201220465 - ίο 基板 11 電性連接墊 12 開窗 20 晶片 21 電極墊 30 絕緣膠 40 導電膠 100 晶片承載件 110 電性連接墊 130 拒鲜層 140 開窗 200 半導體晶片 210 電極塾 300 絕緣膠 400 導電膠 500 封裝樹脂 • 600 絕緣塗層 610 窗孔 111797
Claims (1)
- 201220465 七、申請專利範圍: 1. 一種多晶片堆疊封裝結構,係包括: 晶片承載件,於該晶片承載件上設置有至少一電性 連接墊; 複數個半導體晶片,各該半導體晶片具有作用面及 非作用面,且彼此以作用面朝上自該電性連接墊旁依序 以錯位方式堆疊於該晶片承載件上,以使各該半導體晶 片至少一部分之作用面係外露於堆疊其上之半導體晶 片,且各該經堆疊之該半導體晶片的外露作用面上設有 _ 至少一電極墊; 絕緣膠’設於該些半導體晶片之間及該與晶片承載 件黏接之半導體晶片與該晶片承載件之間;以及 導電膠,用以電性連接該電性連接墊及各該半導體 晶片上之電極墊,以藉由該導電膠使該等半導體晶片均 電性連接該晶片承載件,其中,該晶片承載件上形成有 拒銲層,且該拒銲層開設有外露部分電性連接墊之開 窗,以令外露之該電性連接墊的輪廓,在鄰近該半導體 ® 晶片處向遠離該半導體晶片處縮小。 2. 如申請專利範圍第1項所述之多晶片堆疊封裝結構,其 中*該晶片承載件為電路板。 3. 如申請專利範圍第1項所述之多晶片堆疊封裝結構,其 中,該等半導體晶片彼此以階梯狀方式堆疊。 4. 如申請專利範圍第1項所述之多晶片堆疊封裝結構,其 中,該等半導體晶片彼此以鋸齒狀方式堆疊。 14 111797 201220465 5. ”請專利範圍第】項所述之多晶片堆 .7電性連接塾設於該晶片承載件上之位置係二: 该與晶片承载件純之半導體晶片之電極塾旁。 6.如申請專㈣〗項所述之多晶騎#封裝 中’介於該晶>|承载件及疊接在該晶片承載件上的談丰 】=日片之_絕緣膠厚度大於任二相疊接的該半導 體日曰片之間的絕緣膠厚度。 鲁7·Γ=Γ範圍第1項所述之多晶片堆疊封裝結構,盆 中,该開由之形狀係為梯形、Τ字形、 半- 半橢圓形之其中之一者。 料+0形、 利範圍第1項所述之多晶片堆疊封裝結構,復 之外表。塗層,塗佈於該晶片承載件或該等半導體晶片 1 ΠίΓ_8項所述之多晶片堆_結構,其 :二:=複數窗孔,該等窗孔分別對應於 10’==:範圍第1項所述之多晶片堆4封裝結構,復 膠及導Ϊ:脂,覆蓋該晶片承載件、半導體晶片、絕緣 111797 15
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW099138064A TWI411090B (zh) | 2010-11-05 | 2010-11-05 | 多晶片堆疊封裝結構 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW099138064A TWI411090B (zh) | 2010-11-05 | 2010-11-05 | 多晶片堆疊封裝結構 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201220465A true TW201220465A (en) | 2012-05-16 |
TWI411090B TWI411090B (zh) | 2013-10-01 |
Family
ID=46553159
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW099138064A TWI411090B (zh) | 2010-11-05 | 2010-11-05 | 多晶片堆疊封裝結構 |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI411090B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103915408A (zh) * | 2013-01-03 | 2014-07-09 | 矽品精密工业股份有限公司 | 半导体封装件及其制法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI357640B (en) * | 2007-01-24 | 2012-02-01 | Siliconware Precision Industries Co Ltd | Multichip stacking structure and fabricating metho |
US8723332B2 (en) * | 2007-06-11 | 2014-05-13 | Invensas Corporation | Electrically interconnected stacked die assemblies |
CN103325764B (zh) * | 2008-03-12 | 2016-09-07 | 伊文萨思公司 | 支撑安装的电互连管芯组件 |
TWI378545B (en) * | 2008-12-16 | 2012-12-01 | Powertech Technology Inc | Chip stacked package having single-sided pads on chips |
-
2010
- 2010-11-05 TW TW099138064A patent/TWI411090B/zh not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103915408A (zh) * | 2013-01-03 | 2014-07-09 | 矽品精密工业股份有限公司 | 半导体封装件及其制法 |
Also Published As
Publication number | Publication date |
---|---|
TWI411090B (zh) | 2013-10-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI364820B (en) | Chip structure | |
TWI338941B (en) | Semiconductor package structure | |
TWI401785B (zh) | 多晶片堆疊封裝 | |
TWI415201B (zh) | 多晶片堆疊結構及其製法 | |
US8680686B2 (en) | Method and system for thin multi chip stack package with film on wire and copper wire | |
TW201238020A (en) | Package structure, fabrication method thereof and package stacked device thereof | |
TW200939447A (en) | Semiconductor package and multi-chip package using the same | |
CN102693965B (zh) | 封装堆迭结构 | |
TW200531241A (en) | Manufacturing process and structure for a flip-chip package | |
US8828796B1 (en) | Semiconductor package and method of manufacturing the same | |
TWI620258B (zh) | 封裝結構及其製程 | |
TW201247093A (en) | Semiconductor packaging method to form double side electromagnetic shielding layers and device fabricated from the same | |
TW201220465A (en) | Multi-chip stack package structure | |
KR20140141246A (ko) | 적층형 반도체 패키지 및 반도체다이 | |
TWI473243B (zh) | 多晶片堆疊封裝結構及其製程 | |
TWI429351B (zh) | 小基板記憶卡封裝構造 | |
TWI360877B (en) | Stackable window bga semiconductor package and sta | |
TWI592063B (zh) | 線路結構及其製法 | |
TW201533866A (zh) | 半導體封裝件及其製法 | |
TW200921885A (en) | Package on package structure | |
TWI426593B (zh) | 用於多晶片堆疊封裝之晶片及其堆疊封裝結構 | |
TW201135854A (en) | Wafer level clip and process of manufacture | |
TWI225290B (en) | Multi-chips stacked package | |
TW200908280A (en) | Multi-chip stacked device with a composite spacer layer | |
TW497231B (en) | Stack structure of semiconductor chips and its manufacturing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |