TW201213225A - Planar cavity MEMS and related structures, methods of manufacture and design structures - Google Patents

Abstract

A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a lower wiring layer on a substrate. The method further includes forming a plurality of discrete wires from the lower wiring layer. The method further includes forming an electrode beam over the plurality of discrete wires. The at least one of the forming of the electrode beam and the plurality of discrete wires are formed with a layout which minimizes hillocks and triple points in subsequent silicon deposition.

Description

201213225 VI. INSTRUCTIONS: The application of the relevant application also cites the priority of the application for the provisional application No. 61/3 58,621 of June 25, 2010. The contents of the provisional application are all cited by reference. Incorporated herein. TECHNICAL FIELD OF THE INVENTION The present invention relates to semiconductor structures and methods of fabrication, and more particularly to the present invention, which relates to a Micro-Electro-Mechanical System (MEMS) structure, fabrication and design structure for a flat cavity. The method. [Prior Art] The integrated circuit switch used in the integrated circuit can be formed by a solid structure (e.g., a transistor) or a passive line (MEMS). The mems switch is typically used because of the almost ideal insulation of MEMS switches and the low insertion loss (ie, resistance) of MEMS switches at 1 GHz and higher. This ideal insulation is a key requirement for (iv) electrical applications where MEMS % is used for mode switching of power amplifiers. The mems switch can be used in a variety of applications, primarily for analog and mixed-signal applications. One such example is a mobile phone chip. These mobile phone chips contain power amplification $ (PA) and circuitry for each broadcast mode. The integrated switch on the wafer will connect the PA to the appropriate circuitry so that one μ per mode is not required. Depending on the application and engineering guidelines, the mems structure can have many different forms of 201213225. For example, the MEMS can be implemented in the form of a cantilever beam structure by pulling the cantilever (an end-fixed suspension electrode) toward the fixed electrode by applying an actuation force. The electricity required to pull the suspension electrode to the solid electrode by electrostatic force is called the adsorption power (pun seven V〇Uage), and the adsorption electrode depends on several parameters including the length of the suspension electrode and the suspension electrode. The space or gap between the fixed electrode and the elastic constant of the suspended electrode, the (four) constant of the suspended electrode is a function of the material and the thickness of the material. Alternatively, the milk beam can be a bridge structure where both ends are fixed. MEMS can be fabricated in some ways using a number of different tools. In general, the method is used to form a small structure having a micron size 'where the switch size is approximately 5 microns thick, (10) microns wide and 200 microns long. In addition, the 'self-integrated circuit plus ton of her d to (four)... called technology uses many of the methods used to fabricate MEMS (ie, technology). For example, almost all MEMS systems are built on wafers, and almost all MEMS systems are implemented in a film on the top of the wafer that is patterned by photolithographic processes. In particular, the fabrication of μ· uses three basic building blocks: (1) a film of deposited material on the substrate, (Π) a patterned mask on top of the film by photolithographic imaging, and (111) selection The film is etched to the mask. For example, in MEMS cantilever switches, a series of conventional photolithography processes, (4) processes, and deposition processes are commonly used to fabricate fixed and suspended electrodes. In one example, after the suspension electrode is formed, a layer of sacrificial material is deposited under the MEMS structure (eg, by Whem, 201213225)

The spin-on polymer pMGI manufactured by Inc.) forms a cavity and deposits a layer of sacrificial material over the MEMS structure to form a cavity. A cavity above the mems is used to support the formation of a cover (e.g., a siN dome) to seal the MEMS structure. However, this has caused several drawbacks. For example,

It is well known that MEMS cavities formed using spin-on polymers such as PMGI are not flat. However, uneven MEMS cavities bring multiple depths including, for example, focal variability and are caused by dielectric breakdown.

The issue of package reliability. In addition, MEMS cavities formed using spin-on polymers need to be treated at low temperatures to avoid reflow or damage to the polymer; and poly-sigma can leave organic (ie, 'carbon-containing) residues in the open cavity in. Therefore, there is a need in the art to overcome the disadvantages and limitations described above. SUMMARY OF THE INVENTION In a first aspect of the invention, a method of forming at least one microelectromechanical system (MEMS) includes the steps of forming a lower wiring layer on a substrate. The method further comprises the step of forming a plurality of discrete lines from the lower wiring layer. The method further comprises the step of forming an electrode beam over the plurality of discrete lines. At least one of the steps of forming the electrode beam and the plurality of discrete lines is formed with a layout that minimizes protrusions and triple points in subsequent tantalum deposition. In still another departure of the present invention, the method of forming at least one microelectromechanical system (MEMS) comprises the steps of forming a lower wiring layer on a substrate. The method further includes the step of patterning the lower wiring layer, 201213225 to form a plurality of discrete lines. The method further includes the step of forming a MEMS beam over the lower wiring layer. At least one of the steps of forming the MEMS beam and the plurality of discrete lines forms a layout that minimizes the protrusions and triple points in subsequent depositions. In still another aspect of the invention, a structure includes a plurality of discrete lines 'the plurality of discrete lines on a substrate, and the plurality of discrete vias are formed by AlCu with Ti under and above to form TiA13. The structure further includes at least one MEMS beam. The at least one MEMS beam is formed in the cavity and placed over the plurality of discrete lines. At least one of the plurality of discrete lines and the at least one MEMS beam is formed with a perforated or slotted layout. In yet another aspect of the invention, the present invention provides a design structure for designing, manufacturing or testing an integrated circuit that is tangibly embodied in a machine readable storage medium. The design structure comprises the structure of the present invention. In a further embodiment, a hardware description language (HDL) design structure encoded on a machine readable data storage medium contains components that are processed in a computer aided design system.

. The device executable representation of the MEMS is generated when the components are equal, and the MEMS package 3 is the structure of the present invention. In a further embodiment, a method in a computer aided design system is provided to produce a functional design model of a MEMS. The method comprises the steps of generating a functional representation of the structural elements of the MEMS. In a specific aspect, the electrical function used to generate the MEMS functional design model

The brain-assisted design system is the following method: a functional representation of a plurality of discrete lines on a substrate with a perforated 201213225 or grooved layout. A plurality of discrete vias are formed by A1Cu with butadiene below and above to form TiAl3. The method further includes the step of generating a functional representation of at least one MEMS beam with a perforated or slotted layout formed in a cavity and placed over the plurality of discrete lines. [Embodiment] The present invention relates to semiconductor structures and methods of fabrication, and more particularly to a microcavity (MEMS) structure, fabrication and design structure for a flat cavity (eg, a flat or flat surface). The method. Advantageously, the methods of forming the structures reduce the total stress on the MEMS structure, and the methods reduce the material variability of the MEMS device. In an embodiment, the flat (e.g., flat or flat surface) mems

The structure and formation method of the device uses a sacrificial layer to form a working cavity adjacent to the MEMS beam. In a further embodiment, a reverse damascene process is used to form a flat (eg, flat or flat surface) structure to form a dual layer MEMS cavity . The MEMS structure of the present invention can be used in other devices such as single or double wire beam contact switches, double wire beam capacitor switches or single double wire beam air gap inductors. Figure 1 illustrates the starting structure and associated processing in accordance with aspects of the present invention. The structures disclosed in the next few paragraphs are MEMS electrical switches. However, the methods and structures are also applicable to other MEMS switches (such as ohms). Contact_), MEMS accelerometer, and the like, the 201213225 or other ohmic contact switch will not use a mems structure including, for example, substrate 1G. In an embodiment, the substrate is electrically enamel = any layer of the device. In the embodiment, it may be m-, .. ^ noisy yen, the ruthenium wafer is coated with sulphur dioxide Xicheng | 九习本口t ” cooked ^ other insulators known to the skilled person ^ on the substrate 1 An interconnect 12 is provided within the crucible. The interconnect (4) may be, for example, a tungsten or copper stub formed in a via formed in a conventional manner. For example, familiar techniques may be used. Any of the conventional lithography used to form the stub, (4), and a deposition process (such as damascene) to form the interconnect 12. The interconnect 12 can contact other wiring layers, complementary MOS (c〇mplementary) Lose

Semic〇nductor; CM〇s) transistors or other active components, passive components, etc. known in the art. In Fig. 2, a wiring layer is formed on the substrate 1A using a conventional deposition and patterning process to form a plurality of turns 4. For example, the wiring layer can be deposited on the substrate to a depth of from about 5 microns to about 4 microns; however, other dimensions are also encompassed by the present invention. In an embodiment, the wiring layer 14 is deposited to a depth of 0.25 microns. Thereafter, the wiring layer is patterned to form lines (lower electrodes) 14, which have wiring intervals (gap) 14a between the lines. In the embodiment, the wiring aspect ratio is determined by the ratio of the height of the line 14 to the wiring interval 14a, as discussed in more detail with reference to FIG. 25, which can affect the material variability (for example, Morphology). For example, a low aspect ratio of 1:2 可由 can be formed by a line 14 having a height of 50 nm having a 1 〇〇〇 nm interval 14a; and a high aspect ratio of 1:1 can be formed by a line having a height of 500 nm having a spacing of 500 nm. This 201213225 will discuss the sacrificial film 18 (the first aspect ratio of the wiring interval. The equal aspect ratio is for reference only, and as shown in Figure 3) the conformality determines how at least one of the wires and interconnects is required. 12 contact (direct electrical contact). In an embodiment the 'line 14 may be aluminum or such as tantalum. , or the formation of the ship Si Ming alloy; however, the invention also covers other wiring materials. For example, in other wiring materials, the wire 14 may also be a refractory metal such as Ti, TiN, TiN, Ta, TaN & W4AiCu. In an embodiment, the turns may be doped with Si (e.g., i%) to prevent metal (e.g., A1) from reacting with the upper cavity material (e.g., helium). In an embodiment, the portion of the line may be doped with Cu (e.g., 〇 5%) to increase the electron transport resistance of the line. In practice, the wire may be formed from pure refractory metals such as TiN, W, Ta, and the like. The surface morphology of line 14 is determined by the atomic surface roughness and the presence of metal hillocks. The metal bumps are bumps in the metal, typically about 1 〇 11111 to 1000 nm wide and 1 〇 1 ^ to 1 〇〇〇 nm high. Typical aluminum protrusions can be 5〇 for aluminum wirings that are coated in TiN below and above (for example, 200 nm AlCU coated with 10/20 nm Ti/TiN and covered with 3〇nm (9)) Nm width and 1〇〇nm south. For a MEMS capacitor in which the wire 14 is coated with a dielectric and the wire 14 is used as a lower capacitor plate, since the gate electrode plate formed by the MEMS beam cannot be in close contact with the capacitor plate formed by the wire 14, The presence of protrusions or high value atomic surface roughness reduces the capacitance density. "T uses an atomic force microscope (AFM) or an optical profiler and several existing known methods for measuring and quantizing the width and height of the protrusions 10 201213225 to measure surface roughness. In the embodiment, 'by using AFM to measure the minimum height to the maximum height of the line region between 1 square micrometer and 10,000 square micrometers, and to calculate the maximum" by calculating the area with or without protrusions The root mean square (RMS) roughness is used to quantify the surface roughness. In one embodiment, the surface roughness is the RMS roughness of the 2 μιη 2 region without visible protrusions. Table 1 summarizes the metal protrusion and surface roughness data for various wire materials measured using AFM. The root mean square (RMS) roughness was measured in a region of approximately 2 μηη2 with no visible metal protrusions. The maximum peak-to-valley value is measured in the approximate 10,000 μΐη2 region. The pure refractory wire option has the lowest roughness and protrusion but the highest resistance. The wire with AlCu has a much lower resistance than the pure refractory wire but a much higher roughness and protrusion. Before or after patterning, sufficient Ti is added under and above Aicu and the wafer is annealed at 350 ° C to 450 ° C for a sufficient time to form TiAh lithiate (ie, annealed at 4 ° C) Hour) 'significantly reduces the minimum height of the protrusion to the maximum height while slightly increasing the RMS surface roughness due to the reduced amount of aluminum. In an exemplary embodiment, line i4 is annealed after patterning and line 4 is etched to reduce metal etching problems caused by TiAl3. Thinner Ti (e.g., 5 nm below and above A1Cu) has minimal or no effect on the reduction of protrusions; while 10 nm and i5 nm2Ti significantly reduce protrusions and 1〇11111 is equivalent to 15 nm of Ti. When Ti reacts with aluminum to form TiAh, the thickness of aluminum (for example, AlCu) decreases in an approximately 3:1 manner, that is, for every Ti of nm 11 201213225, 30 nm is consumed to form TiAl3; In order to leave some unreacted AlCu in the line, the Ti:AlCu thickness ratio needs to be less than 1:3 in the case where the Ti thickness includes a layer below and above the aicu. This condition means that the thickness of the deposited Ti should be greater than 5% of the thickness of the as-deposited AlCu and less than 25% of the thickness of the as-deposited AlCu for the optimum protrusion reduction and line resistance considering the thickness variability of the Ti and AlCu deposit states. . Table 1 Process (TiN=32 nm for each layer) AlCu Ta/TiN or Ta Thickness (nm) Ti thickness and lower Ti thickness RMS Roughness (nm) Maximum peak-valley protrusion (nm) Resistance (Ω /SQ) TiN/AlCu/T iN 200 ΝΑ 4.6 148 0.18 Ti/AlCu/Ti/ TiN 200 5 6.8 119 0.24 Ti/AlCu/Ti/ TiN 200 10 6.4 43 0.32 Ti/AlCu/Ti/ TiN 200 15 6.2 46 0.42 TiN 32 ΝΑ 2.3 27 100 12 201213225

The formation of the metal dog can also be caused by the layout of the 3rd 丨 匕""" Lift, use the groove, s·(26h _ s @ v ° is compared to ® and 26C) or hole Ή, (Fig. 26d) to solve the problem as a narrow line layout, and the whole item is given to the 'A whole block layout. (Fig.) will tend to have a larger number of metal protrusions and higher protrusions. More specifically, '帛26a图-第26d' shows a MEMS with a monolithic (W-th image), grooved τ ((10) and %th) and a holed "h" (Fig. 26d) layout Top view layout of capacitor plates. Layout with holes (Fig. 26d) H" can use diamonds (shown), octagons, circles, ovals, squares, plus signs or all symbolic symbols "H&quot ; Represents any shape from the layout cut. Both slotted and perforated layouts are designed to minimize protrusion formation and do not significantly increase the effective line resistance or reduce the capacitor plate area by removing the metal. If a slotted layout "s" (Fig. 26b) is used, the slot width is typically minimized so as not to reduce the capacitor plate area or increase the effective line resistance. For example, a groove having a groove width of i and placed at a pitch of 6 μηι can be used; or a similar ratio of the values (i.e., a groove width of 0.4 μm and a pitch of 2.4 μπ1). For the apertured version of Figure 26d, the amount of metal removed by the aperture will remain at about 2% or less' to substantially not increase the effective line resistance or reduce the capacitance. For example, a 1 μm 2 area hole occupying 20% of the bus area can be used. The amount of metal removed by the grooving or perforation line is also determined by the tendency to form the protrusions. For example, refractory metals are insensitive to the formation of protrusions and may not require grooving or perforating the refractory metal. As the thickness of the wire increases and the thickness of the refractory metal (i.e., TiAl3/TiN, TiN, etc.) is reduced, the tendency to form protrusions in the aluminum or aluminum alloy increases. For higher lines (eg '^ 1 μπι), the amount of metal that needs to be removed by grooving or perforation is preferred; for shorter lines (eg < 0.2 μηι), The amount of metal removed by grooving or perforation can be lower. The spacing is defined as the repeating line width + spacing. For having! The spacing of 5 μηι intervals of μιη is 'the line width will be 4 μηι. For the embodiment, the line width between the grooves will be 4 μm, and the spacing from the vertical end of the line to the edge of the line shape will also be 4 . The layout of the slot algorithm using the end of the slot in the closed state (shown in Figure 26b) is subject to protrusions at the end of the slot due to the effect caused by the increased local area or other geometry. This situation is illustrated in the figure, and Figure 26e illustrates an equally spaced A1 t closed slot layout with both between the slots and between the ends of the slots and the line shape. To reduce or eliminate the tendency to form protrusions in this position, the spacing between the vertical end of the groove and the end of the line shape can be reduced to less than the grooved line width as shown in Figure 26f, Figure 26f The line width A1 and the groove spacing A2 and A3 'A2 and A3 of the edge of the line or the edge of the groove are less than eight. This condition applies to the orthogonal groove (that is, the groove terminates at a vertical angle of 90 degrees) and the angled groove (That is, the slot terminates at 45 degrees or another angle, as shown in Figure 26. Another potential problem caused by the slotted line is the formation of triple points on the uncovered slots in subsequent tantalum deposits. When the groove or hole is not capped (as shown in the figure above or in the upper part of Figure 26d), the subsequent 矽 deposition can form a triple point on the end of the uncapped groove (marked in Figure 26c) ΤΡ., 14 201213225 thus producing defects in the wonderful surface 'The defect can be propagated to the subsequent wiring layer or other layers. To avoid this defect, as shown in Figure 26b, it can be covered or closed (as needed) The end of the slot. Similar to the three-point point defect can occur in the design of the hole, and this condition can be eliminated as the hole is closed. The open hole and the closed hole are shown in the upper part and the lower part of the figure 26d. Depending on the patterning of the wiring, voids or seams may be formed in the sacrificial material (eg, 矽) between and above the spaces between the lines during a later processing step as described below. The area in 7 of the gap between the underlying line or other topography's other morphologies, produced as by-products of the Shi's depositional appearance. These joints may contain impurities (such as oxygen) and these The seam may be due to the presence of cerium oxide or by chemical mechanical grinding (c Hemical mechanical polishing; CMP), wet chemical chemistry, reactive ion etching (RIE) or other downstream processes caused by cracking of the joints, causing subsequent problems. If the aspect ratio is high, then in the subsequent deposition process _ voids or seams can be formed on the lining. These lines or seams can be made of material (such as '矽) morphology, especially if there is insufficient grinding during the subsequent processing steps Or when overgrinding; or if the voids are oxidized during deposition of the subsequent film. Or 'If the post-insertion process or reverse damascene process is used for the wiring layer 14, the surface will be substantially flat' and the subsequent layers will not Sensitive to the formation of voids. In the case where the wire will be deposited and patterned, the reverse inlay process is followed by a process of dielectric deposition and planarization steps to expose the surface of the wire, but there is a flat interface between the wires. 15 201213225 In Fig. 3, an 'insulator layer (dielectric layer) 16 is formed on the exposed portions of the plurality of lines 14 and the substrate 10. In the embodiment, the insulator layer 1 is deposited to about 80. The oxide of nm; however, the present invention also covers other dimensions. The combined thickness of the lower MEMS capacitor insulator layer 6 and the subsequent upper MEMS capacitor insulator layer 34 shown in Figure 11 determines the breakdown voltage and time dependent dielectric collapse of the MEMS capacitor. (Ume dependent dielectric breakdown) property. For MEMS operation at 50 V, the breakdown voltage needs to be greater than 5 〇v (usually greater than loo V) to ensure high MEMS capacitor reliability. For 5 〇v operation, 160 nm The combined MEMS capacitor insulator thickness is sufficiently reliable. If the MEMS capacitor is being fabricated, the insulator layer 16 is required and the insulator layer 6 will form the lower capacitor plate dielectric. The insulator layer 16 also acts as a barrier between the metal (e.g., aluminum) in the wire 14 and the subsequent material 18 (i.e., 矽). The ruthenium and aluminum will react to form an intermetallic compound that is difficult to remove, and if the intermetallic compound is formed, the MEMS beam can be prevented from being activated by the barrier beam from being completely collapsed during actuation. The formation of this intermetallic compound can be prevented by a strong insulator layer 丨6. It should be noted that it is desirable to deposit at a temperature compatible with the aluminum wiring (e.g., at about 42 (at TC and preferably at about 4 Torr < t), to prevent the use of such a layer. Liquid phase chemicai deposition (lpcvd) Si〇2 height conformal

The electrical conformal dielectric system is deposited at temperatures well above about 42 〇〇c. The deposition selection for the insulator layer 16 includes one of the following or a method of the present invention. Plasma_enhance (J 16 201213225 chemical vapor deposition; PECVD), sub-atmospheric chemical (sub-atmospheric chemical) SACVD), atmospheric pressure chemical vapor deposition (APCVD), high density plasma chemical vapor deposition (HDPCVD), physical vapor deposition (physical vapor deposition; PVD) or atomic layer deposition (ALD). This layer will be discussed in more detail with reference to Figures 27a - 27c. A layer of sacrificial cavity material is deposited on insulator layer 16; or if insulator layer 1 is absent 6, depositing the layer of sacrificial cavity material 18 on layer 14. The sacrificial cavity material, such as stellite, tungsten, group, errone or subsequently can be selectively removed to the insulator layer 16 using, for example, XeF2 gas or Any material that is removed to the wire 14 without the insulator layer 16 is used in the embodiment, and is used for the layer 18. The temperature can be used to be compatible with the wiring 14. (eg, 420 C) any conventional vapor deposition (pVD), PECVD, rapid thermal chemical vapor deposition (RTCVD) or LPCVD to deposit layer 18. In one example, layer 18 is deposited to a dimension of about 微米"micron to 1 〇 micron, which is determined by MEMS gap requirements, and the layer is patterned using S-lithography and reactive ion etching (RIE) steps. An example would use a thickness of about 2.3 microns. The common RIE etch gas for germanium is SF6, where SF6 is diluted with other gases such as CF4, nitrogen or argon. The 18-cut deposition process can produce seams between the lines and at the edge of the line 2012201225. If the seams oxidize or have other impurities in the joints, the seams are during the etch layer 18 etching step Or it is difficult to etch during the final cavity opening etching. To avoid leaving a tantalum seam on the B circle after the Η layer button J, argon dilution and radio frequency (RF) bias can be used. Combination of pressure power' RF bias power is applied to the wafer for simultaneous sputtering and RIE etched surface. The voids may be formed above the interval l4a between the lines 14 due to the poor step coverage or conformality of the layer 18. The width of the gap 2, the distance from the substrate 1 and the distance from the surface of the stone 20a are determined by the aspect ratio of the line 14, the conformality of the tantalum deposition, and the shape of the insulator layer 16. Figures 27a-27c illustrate the shape of several insulator layers 16 above line 14. The line 14 shown in Fig. 27a is drawn as an undercut having AlCu under the upper TiN/TiAl3 layer 14. This undercut often occurs during metal RIE processing, and if such an undercut is present, the undercut increases the difficulty of obtaining good sidewall 14 sidewall coverage of one or more of the insulator layers 16. Figure 27a illustrates the formation of an insulator layer 16 using a conformal process (e.g., LPCVD, APCVD, or SACVD). These conformal deposition processes provide an almost uniform insulator thickness on top surface 16 A, side surface 16B, and bottom surface 16C. When performing these conformal deposition processes at temperatures compatible with aluminum or copper based wiring (eg, at 420 ° C), such conformal deposition processes can have poor capacitor dielectric properties, such as 'high leakage current, Low voltage friend > Bay' or bad time dependent dielectric breakdown (time dependent

Dielectric breakdown; TDDB) reliability. In addition, a step configuration 300 is provided in the void 20. Fig. 27b shows an external structure 3G5 using an insulator JS! A > 状 ” or " 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Despite these "bready, non-conformal, these """ "films" can have excellent capacitor dielectric voids due to the deposition of these films. It is desirable to have a cone as shown in Fig. 27c. The outer shaped layer 18 has a step coverage and reduces or eliminates the <RTI ID=0.0>>>> The voids and depressions 19 are formed by the spacing between the lines 14, and the voids and the depressions can vary, depending on the height of the layer 18 and the spacing of the lines 14 and/or the degree of rain. These recesses 19 may be deepened during subsequent processing, such as chemical mechanical processing,' as described below with reference to Figure 8. The recesses 19 and seams may be oxidized during subsequent processing such as exposure to humid air, oxidized ambient photoresist strips or plasma oxidative deposition, and such oxidized daylight regions are during the final residual or removal step Will not be removed. If this condition occurs, then such oxidized Daylight residues under the MEMS beam can block the MEMS beam from contacting the lower electrode (wire) 14, resulting in poor actuation (see, for example, element 19a in Figure 33). Making the insulator layer "outer tapered" (Fig. 27c) reduces or eliminates this effect by eliminating voids and depressions, such as by eliminating gaps by filling the gaps. It can be deposited by high density. An electropolymerized CVD oxide is used as part or all of the insulator layer 16 to shape the outer shape (Fig. 27c). Alternatively, an insulator deposition and one or more sputter etch backs and one or more subsequent passes 19 201213225 Bulk deposition can result in the same tapered shape of the insulator layer 16. Alternatively, as described below, the ruthenium deposition can be modified to form the iridium into a 45 degree cone by sputtering the ruthenium film in situ in the PVD 矽 deposition chamber. The insulator layer 16 above the wire 14 also acts as a reaction, alloying or interdiffusion of the material of the barrier wire 14 with the layer (cavity material) 18. For example, if the wire 14 contains aluminum, the aluminum can react with the ruthenium to form aluminum. The telluride, the alumite of the aluminum is difficult or impossible to remove during the subsequent layer 18 (sacrificial layer) opening or removal step. This aluminum telluride formation can occur in the upper line corner, for example 'because Insulator | 16 with retrograde deposition wheel gallery Figure 27b) or has a low coverage in the upper corners (帛27. Fig.), so that (4) deposits at layer 18. This can be reduced or eliminated by increasing the thickness of the insulator layer, but due to the use of lines 14 As a related reduction in the capacitance of the MEMS capacitor formed by the bottom plate, it is not always possible to increase the thickness. In addition, wire surface or corner defects (not shown) can block the insulator layer 16 from being completely coated with aluminum. The 矽 reaction can produce salientized whisker-like features of aluminum that can block or partially block MEMS beam actuation. To prevent this layer 16 from reacting with layer 18, a conformal barrier such as ALD Al2〇3 can be deposited ( Oxidation), (iv) bismuth pentoxide or combination of ALD Al2 〇3 and ALDTa 205. In an exemplary embodiment layer 16 consists of 80 nm HDPCVD oxide followed by 15 nm ALD alumina. The film has a very slow deposition rate, and although these ALD films can be used alone as MEMS capacitor dielectrics, this can be impractical due to long deposition times and high manufacturing costs. An ALD aluminum oxide film has every minute! (10) Shen 20 201213225 Accumulation rate 'This condition means that 80 nm film will be deposited; r ΟΛ 、, and buy 8 Q minutes. Therefore, it is best to use the combination of rapid deposition of Si〇2 and slow deposition of alumina. ALD oxide or similar film can be used under the oxide of 8 〇 Dnm; and the ALD oxide or similar film can also be used under the upper MEMS electrode 38 to block the reaction between the shi and the ± Mems electrode. In the Figure 3a, an optional processing step for forming a dielectric = sub- 16a (e.g., 'oxide nail) is illustrated in accordance with an aspect of the invention. In this optional step, an oxide nail can be formed prior to forming the sinker layer 16. 16a. For example, the oxide nail 16a can be a deposited pEcvDSi〇2 film which is etched on the wire 4 using a micro-patterning and a patterning process. Under this selection, the oxide nail 16a can be first patterned and etched, followed by wire meshing and silver etching; or the pattern 14 can be first patterned and silver, followed by oxide nail W deposition and (4) . Since the oxide between the turns is not etched during the oxidation (4)-(4), the pattern is patterned and the (10)j oxide nail 16a is prevented from being added before the pattern 14 is patterned and introduced into the . The aspect ratio of the deposit. In addition, if the pattern is patterned and the line 14 is patterned, and the oxide needle is patterned? —, the fluorinated carbon-based RIE chemistry of the oxide nail 16a can also be used to create a degraded surface and degraded capacitor electrical yield or reliability. The oxide needle forms a protective layer during MEMS operation when the oxide nail is placed over the gauge (10) actuator in the region away from the MEMS capacitor or contact head, which prevents the conductor in the MEMS beam from being electrically generated Arcing to 21 201213225 The MEMS beam does not need to be in close contact with the lower actuator electrode in the region of the lower electrode. Since the preferred process is to pattern and etch the oxide nails prior to patterning and etching lines 14, it is desirable to avoid having the spacers 14a between the wires 14 and the oxide nails. After the formation of the oxide nails 16a, the insulator layer 16 and the layer 18 can be formed as described above. As an optional processing step, layer 18 can be planarized using, for example, chemical mechanical polishing (CMp), after which additional material (矽) can be deposited on the ground layer 18 as needed to lower the MEMS cavity. A seamless layer of enamel is provided on the surface. It should be noted that conventional CMP and subsequent cleaning processes (such as brush cleaning, dilute hydrOfluoric acid (DHF), buffered hydrofluoric acid (BHF), BHF), low temperature cleaning, etc., will be performed after any CMP step. ) to remove the natural oxide formed on the surface of the crucible. For example, reference is made to the figure "depositing a layer 18 on insulator Ii 6 using a conventional deposition process such as 'P VD." As shown in Figure 4a, a void 20 can be formed in layer 18 between lines 14. Wherein a recess 19 is formed over the void 2〇. As shown in the servant diagram, a (eg) 18 is used, for example, by a CMP process. In FIG. 4c, a second layer of material 22 is deposited on the planarized layer 18, For example, Shi Xi. In the 4d®, use the conventional lithography and reactive ion silver engraving (RIE) steps to pattern the sap layer 18 and the sap layer 22 (the sap layer now forms a single layer (hereinafter referred to as For layer 18))»This work, ^ " this 矽 deposition, CMP and second deposition

The process eliminates the depressions in the surface of the crucible 1 Q, $ M core U丨9, eliminating the possibility of oxidizing the seam 2

Sexually, and partially or completely flattened due to the morphology of the surface of the stone on the surface of the stone due to 1/( a A intrusion line ι4 and line spacing 14a. 22 201213225 , 'and the example twin thickness will be 25 〇 nm high Line 14 4, line 1* between 500 nm interval 14a, 2 micron initial 矽18 deposition thickness line 14 above 400 nm 矽CMp removed to flatten the stage above the line 14⁄4, and 2 2 thick Subsequent Shishi deposition, the subsequent Shishi deposition is thick enough 'sufficient to remain partially on the wafer during the subsequent reverse oxide planarization process shown in Figures 5-8. In an exemplary embodiment The upper portion of the line 14 is removed from the upper portion of the line 14 and substantially removes less than 5 〇 nm of the space 14a between the lines, which partially flattens the line 14 and the area above the interval 14a. As is known in the art, 矽CMp is typically implemented to form deep trench dynamic random access memory (Dynamic Rand〇m8 "Memory" DRAM) capacitors. This type of 矽eMp 'cMp system is best used. To maximize the liner insulator (eg, Si〇2 or oxide) film on the wafer surface Selectivity, that is, maximizing the 矽 CMP rate and minimizing the oxide CMP rate, so that the oxide selectivity is 50: 1. This type of 矽 CMP process is optimal for ruthenium films using cvd deposition, However, this type of 矽 CMp process can cause problems for ruthenium films deposited using PVD. Films that are polished using conventional selective 矽 processes can have problems associated with defects in PVW films that can cause localized polishing rates. These pvD defects can cause the selective 矽 CMP process to leave under-polishing defects on the surface of the polished ruthenium, which may be caused by oxidized dreams, other impurities or ruthenium particle structures. In order to avoid these defects during the Shexi CMP, a lower selection 23 201213225 selective grinding process can be used, for example, using si〇2 polishing chemistry and CMP polishing chemistry and processes. The development process eliminates the surface defects of these polished spots. An example of selective grinding is the use of a rare earth oxide abrasive with sufficient acidity, ie, >12). Sex Quality (such as 'Telemethyl amm〇nium hydr〇x coffee') has a selectivity of 5〇:1 石西si〇2; non-selective f-grinding - an example is the use of two The oxidized 11 abrasive has an acidity test value of <12, such as κ〇Η, which is too low to dissolve Shi Xi. This non-selective Shi CMp process will have less than 5〇:1 Shi Xixi: si〇2 selection rate, and in an exemplary embodiment, the dream: si〇2 selection rate will be in the range of 2:1 to 1:2. In order to avoid grinding into the voids 20, it is desirable that the thickness of the first-deposited deposition is sufficient to bury the voids below the surface.矽 The wavelength of the light is not opaque. If the subsequent lithography process for patterning uses wavelengths of light, the cMp process will not completely flatten the alignment structure using the wiring layer topography or the alignment structure filled with portions of the damascene layer 12. This prevention is not required if the subsequent lithography process uses infrared light or other methods that detect features underneath. Even up to m·, a thin natural oxide (for example, Si〇2) is formed on any surface of the crucible exposed to air or oxygen. This natural oxide is used when the surname is engraved or opened during subsequent processing. There is a hindrance to silver engraving or opening 'or the presence of the native oxide can remain on the wafer as a little monolayer of Si 2 film. In order to avoid this situation, it should be purified by exposing Shi Xi to steam, 24 201213225 plasma or liquid hydrofluoric acid (hydrofluoride acid, or should be performed immediately before deposition of the second layer 22; Without pre-exposure to air or oxygen, the pre-cleaning uses, for example, a biased argon-reducing pre-cleaning. Referring to Figure 5, an insulator material (e.g., oxide) 24 is deposited over layer 18. The oxide deposition can be, for example, In a conventional conformal deposition process, the oxide layer 24 is deposited to a depth approximately the same as the height of the 8 layers. For example, for a layer 13 of thickness 2.3 microns, the oxide layer 24 has a depth of about 2.3 Å. For example, in such a technique It is known that the deposition process may be the use of tetraethoxyx (Tetraeth()xysilane; TE〇s) or μ as the source of the stone and the use of oxygen or ν2〇 as an oxygen source for the deposition of t pEcvD oxide. The thickness of the layer 24 is thinner than the height of the layer 18, and the subsequent oxide (10) process shown in Fig. 8 will over-polishing and planarize the surface of the layer 18. Conversely, if the thickness ratio of the oxide layer 24 is intentionally The height of the layer 18 is thicker. The subsequent oxide (10) process shown in Fig. 8 will cause the surface of the layer 18 to be insufficiently ground and the surface of the layer to be buried under the oxide surface. The two process options may be desirable, = The oxide layer 24 or (4) surface topography from the wiring layer is compared with the importance of 'minimizing the surface of the crucible plus 8 overgrinding. In an embodiment, ... is about Μ micron, the oxide layer is The second a micron' and the optional oxidation back-to-step removal shown in Figure 7 are targeted, ie, > 2 micron. This condition leads to the 'oxide polishing process' step-to-step flat layer 18. In the figure, optional reverse etching is performed in accordance with aspects of the present invention (reverse 25 201213225 to the inlaid process). More specifically, a resist 26 is deposited on the oxide layer 24, and the anti-pattern is patterned. The etchant forms an opening wherein the resist edge 26a overlaps the edge of the lower layer 18. Also, the resist % will slightly mask the lower layer 18. This overlap needs to be greater than 〇, and the overlap can be, for example, 3 microns, and Minimize this overlap to reduce oxides to be flattened during subsequent cMp processes 24. If the overlap is negative, the subsequent RIE # inscribes the silver into the lower portion of the oxide | 24, thereby creating a deep trench adjacent to the layer 18, which may cause subsequent wiring layers, such as from within the deep trench. The problem of residual metal causes a short circuit in the subsequent layers, and this should be avoided. As shown, the opening is the opposite image of the patterned layer 18. As shown in Figure 7, 'Use Conventions The coffee process engraves the oxide material 7 24. In the embodiment, as shown in Fig. 7, the (4) process produces a frame J 30. The frame "3" surrounds the lower layer j 8 . If the oxide material 24 is fully slid down to the surface of layer 18, the oxide in the region away from layer U will be minimized. This may be desirable to minimize over-grinding of layer 18 to reduce the thickness tolerance of the layer; and to eliminate the possibility of residual oxide remaining on the MEMS capacitor or contact area. Alternatively, some oxide may be left over layer 18, as shown in Figure 7. In Fig. 8, the oxide material 24 is planarized, for example, to be flush with the lower layer (e.g., an almost flat or flat surface). In an embodiment: this process will also flatten the lower (four) layer 18, which will advantageously result in a flat cavity structure (e.g., having a flat or flat surface) in the subsequent processing steps. Ping #去』& See the W (10) process. Unexpectedly and in more detail, the oxide (10) can minimize the variability of the 2nd mortar; for example, 'depending on the wiring spacing', the oxide material = the grinding can minimize the depression between the lines 14. (Examples on the interval 14a between the lines.) (d) Figure 25 shows several topographical diagrams of the oxide grinding of the depth of the Shixi depression and the surface of the layer U shown in Figure 8 (also That is, atomic force microscopy data. These figures relate to the grinding of the oxide layer 24 as shown, for example, in Figure 8. In this example, the depressions in layer 18 (see, for example, Figures 3 and 8) ) can be 250 nm (0.25 μΐΏ) high, which is the thickness of line 14. The graph in Figure 25 shows the oxide layer in the case of 〇5 μηη, 〇8 claws and 5$ different wiring compartments 3514a 24 sec, 6 sec. and CMP. These diagrams illustrate the undesired importance of the wiring spacing 14 & of line 14 to minimize the morphological variability of layer i 8. For example 5 , respectively, compared with the depth of the 〇1 〇 nm recess of the CMP of the CMp of the oxide of 6 sec. The groove of 0.5 μm (interval) and the cMp of the oxide of 3 sec. show the depth of the 2 nm recess in the layer. Also, the depth of the depressed portion of the cMp of the oxide of 6 sec and the CMp of the oxide of 90 sec. The 8 nm recess. The depth of the 卩 is compared to the depth of the 30 nm recess of the layer 18 of the μ 8 μηι in the case of the cMp of the oxide of 30 seconds. In addition, the depth of the 40 nm recess of the CMP with 60 seconds respectively Compared with the depth of the 1〇ηιη recess of the CMP of 9 seconds, in the case of the CMp of the oxide of 30 seconds, the groove of the 2012 ΓΠ * 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 It is expected that the increased CMP time of the oxide will optimize the morphology of the layer 18, i.e., the reduction in the depth of the recess. These recesses in layer 18 will replicate beneath the 纟 beam, resulting in the underside of the MEMS beam. In addition, the underside morphology of the MEMS beam, which consists of the deposited oxide and the underlying oxide joint below the recess, may be poorly adhered to the MEMS, and the resulting material is exfoliated during MEMS operation. Peeling can cause catastrophic MEMS capacitor yield or Of downgrading 'due to the presence of a sheet in the MEMS beam is below or above the cavity ⑽ spalling of the oxide.

Thus, the method for reducing the depth of the depressed portion or the variability of the tantalum layer for the MEMS structure includes determining the spacing between the lines formed on the tantalum layer. The method further includes etching the oxide layer for a predetermined amount to minimize variability of the layer. For each interval, (iv) a predetermined amount of time will result in an optimal structure', e.g., reducing any variability in the layer. The recess above layer 18 can be the source of residual oxide under the open or released mems beam, which is formed in the seam of the crucible due to the underlying morphology caused by the interstitial material in layer 14. Above the gap. For example, an oxidized electro-pECVD process can be used and optionally at about 350 ° C or 400. (: Lower oxide layer 24 or oxide layer 34 is deposited, resulting in oxidation of the recess or seam. This oxidized recess or seam CC (as shown in Figure 33) may remain in the MEMs beam after the opening On the lower side, a topography is created beneath the MEMS beam that partially blocks the MEMS beam from contacting the lower capacitor electrode (wire) 14 or collapses or falls during MEMS 28 201213225 beam actuation or operation, Causing damage to the dielectric of the MEMS capacitor. The optional embodiment described in Figure 4b, Figure 4c, and Figure 4d eliminates this problem, where the layer Q ^ _ ^ is ground and covered with a second As the optional step shown in Figure 9a, the oxide material 24 can be deposited to a thickness of about 3.3 μηη compared to 2.3 μΠ1 shown in Figure #. For this embodiment The etched depth is similar to the depth described in the figure, but the etch etch depth will be substantially _i_ deeper and will require exposure to the surface of the underlying layer 18. The recesses may be formed, for example, in I18. Shown above the gap 20 between the lines 14. As shown in the figure, thick oxygen A material 24 is deposited on the side of layer 18, patterned and etched by ❹, and ❹ (10). In Figure 9b, sap layer 32 is deposited, for example, on thick oxide material 24 and layers. 18. As previously mentioned, the natural (or any) oxide should be avoided on the surface of layer 18 before depositing the subsequent fracture layer 32. In Figure 9C, a conventional process is used. (e.g., CMP) to planarize the layer 32 (and a portion of the oxide material 24) that eliminates or minimizes the recess. In an embodiment, the process will advantageously produce a flat cavity in subsequent processing steps. Structure (eg, flat or flat surface). These additional steps (ie, germanium deposition, CMP, deposition (Fig. 4a - Fig. 4C 'Fig. 9a - Fig. 9c) and reverse mosaic oxide CMP Over-grinding (Fig. 6 - Fig. 8) or non-reverse mosaic oxide CMp overgrinding (Figs. 5 and 8) determines the morphology of the microscopic and giant MEMS beams 29 201213225. See below for further discussion in Figure 25 Microscopic MEMS beam topography due to the depression above the void. Undesirable An example of a superficial topography is that the curved 矽 surface i8a and the 矽 surface 18be 第9d shown in the ninth and yth diagrams illustrate the 矽 surface curvature 18a caused by the non-optimized planarization, and is more specific. For example, the figure illustrates an example of an undesired macroscopic morphology. The curvature of the superficial topography i8a or concave surface 18b in the lower cavity material 18 can cause the release of the MEMS beam 'East knot' curvature and poor The MEMS actuation, that is, the MEMS beam can be bent around the sacrificial cavity material 18, resulting in high beam post-release curvature and poor MEMS beam actuation or contact areas. The curvature of the surface of the poem can be determined by the radius of curvature ROC", which is desirable for lem, and the ROC value is greater than 5 cm due to the reduced surface contact area of the Mems capacitor and the comparison between the two MEMS capacitor plates. The large pitch results in a reduction of approximately 〇% of the MEMS capacitor capacitance. In Figure 10a, starting from the structure of Figure 8 or Figure 9c, an optional trench 33 can be formed in the layer 18 above the wiring 14. To ensure uniform etch of germanium, an optional oxide RIE process can be performed on the resist patterned wafer prior to germanium etching. Additionally, in the presence or absence of an optional oxide RIE process, etching is performed. Previously, HF cleaning using a photoresist on the wafer could be performed to passivate the tantalum surface with hydrogen. In an embodiment, the trench 33 is formed into a layer 2 of 20 microns high (eg, sacrificial cavity material 18). The depth is about 3; however, the invention covers other dimensions, depending on design parameters, and more specifically, the height of the layer 18. 30 201213225 The oxide needle core as described in Figure 3a The purpose of these drum oxide nails or grooves 33 Then, an 'I-electric buffer' is placed between the beam and the lower layer μ to prevent arcing caused by the close proximity of the line in the MEMS beam to the line 14 during the 纟mems operation. When the DC (direct) dc voltage is high (i.e., 5_ι〇〇ν) can be applied to, for example, the 赃(10) actuator in line 14. (4) The potential for arc-free, the follow-up of the bottom of the close contact groove 33 can be removed. The beam metal layer is as shown in the (10) and centroid views. The oxide nail 33a causes the subsequent MEMS beam metal layer 38 to be removed from the design, while the oxide nail 33b leaves the metal layer 38 in the design. Subsequent metal layer 38 Used to form a MEMS beam lower electrode, the subsequent metal layer 38 can be patterned to cover the oxide nail 33 or to prevent the oxide nail from being covered. If the oxide nail is not covered, the actuator pole is reduced. The possibility of arc or other dielectric damage between the plates; if the oxide nails are covered (ie, the metal extends down into the oxide nail B), the oxide nail can be reduced to reduce the actuator arc or The effectiveness of electrical damage. If the oxide nail 33 is not Covered by the metal layer %, and there is a step down into the material by the process method of =, there may be a thin metal spacer left along the sidewall of the oxide nail. Since the = spacer spacer contact electrode 38 'Therefore, the metallographic septum is not required. J uses an oxide needle of almost 9 degrees or a round bottom corner. For the reduction, it can be shown on the circle based on the argon-SF6... The rf bias power 'can reduce the argon flow. If 31 201213225, it is desirable to make the pattern of the MEMS beam metal 38 appearing on the bottom of the nail before or after the nail is rounded. The process can be flattened in the reverse cavity, etch J oxide nail 33. If the patterning and _ of the oxide nail 33 are performed after the reverse cavity planarization process, the oxide caliper is controlled only by the (four) depth variability rather than by the reverse cavity oxide CMp planarization step. Degree variability. Alternatively, if the patterning and silver etching of the oxide nail 33 is performed prior to the reverse cavity oxide planarization oxide deposition step, the oxide nail 33 will have an increased component of the high variability caused by the (10)p removal variability. However, the oxide nails 33 will be filled or partially filled with planarizing oxide, which would increase the spacing or spacing between the subsequent metal layer 38 and the actuator metal layer 14 if the oxide nails are covered by metal. In Fig. 11, the upper capacitor dielectric or oxide deposition is performed on the structure of Fig. 10a. More specifically, in this deposition step, oxide material 34 can be deposited to a height of about 8 〇 nm; however, as previously described, the invention encompasses other dimensions. When the MEMS beam is actuated, the ME(10) capacitor dielectric comprises a dielectric layer 16 and a dielectric I 34 that are separated by a coarse radii of the surface of the MEMS capacitor electrode and a small gap caused by the protrusions. A tapered through hole 36 may be formed in the oxide material 24 and the oxide material crucible to the lower layer, the line 14, . The tapered through holes 36 can be formed using conventional lithography, etching, and cleaning processes known to those skilled in the art. It should be noted that the tapered via holes are not excessively oxidized to the underlying TiN, TiAl3, AlCu surface. This excessive oxidation can produce high via resistance. The rear via RIE photoresist stripping 32 201213225 can be performed at a low temperature (i.e., 1 〇〇t) as needed to minimize oxidation. Alternatively, it is known in the art to make inlaid short studs. The use of tapered vias 36 reduces CMP exposure on the surface of the stone, resulting in less 矽18 thickness variability, avoiding the lower likelihood of grinding or damaging the upper MEMS capacitor insulator W and forming deep recesses. Since the thickness of the fracture layer 18 determines the adsorption voltage of the device, it is desirable to minimize the thickness variability of the layer. It should be noted that the tapered through hole 36 should be used in the ice/field from the dream cavity area, because if the tapered through hole is placed in the broken cavity, the oxidation name used to manufacture the tapered through hole is It will be blocked by the layer 18. If the subsequent metal deposition process for line 38 has poor conformality or sidewall coverage, then the aspect ratio of tapered via 36 needs to be 'low', such as 'Q 5:1. For a 2 micron thick insulator Μ and 5' can use a 4 micron wide tapered via 36. Alternatively, a higher aspect ratio may be used for the tapered through-holes 36 if the process is modified (i.e., hot reflow or (10) process). In Fig. 12, the line of the electrode 38 is formed on the oxide material 34 and the line is deposited in the via 36 to contact the underlying line to deposit the electrode 38 in the trench 33; however, 'The electrode is not shown in the groove 33 of the 12th @(Right: in the following figure, 'electrode 38 is shown as being formed in the groove. In the example, Ray 1β γ & It may be, for example, AlCu; however, the invention also encompasses 'in embodiments, for example, in other materials, the electrode 38 may be TiN, TiNst w, or the thickness of the wire (4), the electrode and other electrodes, and the particular design Depending on the parameters. For example, you can use ^". One State One 33 201213225

The Ti/AlCu/Ti/TiN layer, after annealing at 400C, will form TiAl;j under and above A1Cu. To minimize any protrusions, an optional Ti layer may be deposited and/or formed in direct contact with A1 in the embodiments as previously described. In this case, the projections should be restrained from being opposed to the upper surface on the lower surface of the wire (electrode) 38. Alternatively, the electrode 38 may be formed of a metal such as 'gold, or a refractory metal such as w*Ta; or may be formed without a Ti-AlCu interface (e.g., Ti/TiN/A1Cu/TiN). In Figure 13, in the shape of the electrode in the shape of the & 琢 何 何 何 何 何 何 40. In an embodiment, the insulator material 4 is an oxide deposited using any of the above methods, and the deposited oxide is deposited to a height of about 5 to 5 μm, depending on the beam spring constant and the oxide to metal thickness ratio requirement. In an exemplary embodiment, the insulator material is 4 Å PECVD 2 μιη oxide' and the insulator material has residual stress and thickness that are well controlled. In an embodiment, a tapered via 42 is formed in the insulator material to expose portions of the underlying electrode 38 in a manner similar to the previously formed via 36, and a tungsten stub via can be fabricated to degrade The thickness variability of the layer 4 caused by the variable (10) money of the insulator layer 4G is at the expense. The variability of the thickness of the insulator layer 4 or the residual stress produces the spring constant and stress gradient variability of the slab, which can negatively affect the beam curvature and bending. As shown in FIG. 14, 'the upper-pole 44' is formed and patterned on the insulator layer 40 and the upper electrode is deposited in the via hole 42 to contact the lower electrode. In the real (four), the upper electrode 44 is connected to the lower electrode. 38 The same material 34 201213225 is formed; in an exemplary embodiment, the upper electrodes 38 and 44 are composed of Ti/AlCu/Ti/TiN. For tungsten stub vias, the prior art teaches that the highest TiN layer should be left on the via after the via etch. For tapered vias used with such MEMS structures, it is desirable to etch the TiN layer by using ΉΝ RIE chemistry before depositing the electrode 38 and the electrode 44 metal (ie, Ti/A1Cu/Ti/TiN). Argon sputtering is used to sputter a TiN layer or a combination of argon sputtering and TiN RIE chemistry to completely remove the Τι layer to eliminate the potential for via ohms. In an embodiment, the amount of metal of electrode 38 and electrode 44 should be the same or substantially the same 'to balance the total amount and stress of the device so that no excessive stress is placed on the beam of the MEMS structure. The amount of metal is determined by both the metal thickness and the layout. If an equal layout is used for the electrode 38 and the electrode 44, if the electrodes have the same thickness, the electrodes will have the same. The right slotted or perforated layout for the lower electrode 38 will require the upper electrode to be thinned to match the amount of metal. In an embodiment, the thickness of the lower or upper electrode 44 may be increased or decreased to intentionally place a stress gradient into the beam 'this will deflect the beam up or down after release; or change the temperature The resulting beam is bent as described below. It has been previously discussed that 'electrode 38 and electrode 44 are composed of a single, equal metal film. In practice, such as Bu Ling #, +, ^ As mentioned above, the electrode is composed of multiple layers of metal, each layer of metal has a different coefficient of thermal expansion (added 1 expansi〇n (10) called CTE) and other mechanical properties, and if the layout changes Or thickness 'is almost impossible to precisely match the mechanical properties of the multilayer metal. If the A1Cu portion of electrode 38 and electrode 44 is much thicker than refractory and other metals via 35 201213225, then (4) and other mechanical properties can be approximated to the first order by the CTE and other mechanical properties of the A1Cu film. Alternatively, if the layout of the upper electrode 38 and the lower electrode 44 are asymmetrical or different, the thickness of the electrode having a lower pattern factor (i.e., less metal) can be made thicker to balance the amount of metal. An example of the asymmetric upper and lower electrodes is shown in Fig. 28. In this representation, there are diamond-shaped (or other patterned shapes)-like shapes removed from the lower two electrodes 200 that are placed to reduce the likelihood of metal protrusion formation. Since the area of the lower MEMS electrode 200 is smaller than the area of the upper MEMS electrode 21, if the thickness of the metal of the electrode 200 and the electrode 21 is equal, the amount of metal in each electrode will be unbalanced. Balancing the amount of metal between the lower electrode and the upper electrode is important for both the cantilever MEMS beam and the bridge dirty (10) beam because the coefficient of thermal expansion (CTE) of the beam metal (e.g., 'aluminum) is much greater than the coefficient of thermal expansion of the Si〇2.

In an embodiment, the electrodes may be partially balanced with different regions. For example, if the lower MEMS beam electrode is 80% less than the upper electrode, the lower electrode can be thickened by 1 (%) to partially rebalance the amount of metal in the two electrodes. Deliberately making the amount of metal in the two MEMS electrodes unbalanced can cause the MEMS beam to bend after release or opening, which causes the beam to bend up or down to the desired position; or the intentional imbalance between the two of the electrodes The MEMS beam bluster can be minimized at operating operating temperatures (eg, -55 it to US. 0 or any normal range of packaged wafer operating temperatures) as described below. When Με·beam is bent up or down, MEMS is empty The cavity actuation gap is increased or decreased; and the curvature of t MEMS 36 201213225 can vary, ° the curvature of the beam can reduce the contact area when the wafer temperature is expanded or contracted due to the operating temperature and the beam changes with varying temperatures It is desirable to minimize the MEMS beam bending above the capacitance, and the MEMS cavity gap is inversely proportional. When the open MEMS beam moves because of the cover rivet (Ud Ην^ΑΑ or because the cover is bonded to the cover BB (see page 31) Fig.) When bound by the cover, the MEMS beam will not be actuated as desired and will be partially or completely inactive. The back cover oxide is shown in Figure 16 with the largest back-off range in the corner. Less: this = Circumference, as shown in Fig. 32, can reduce the possibility that the cover oxide will pin the MEMS beam in the "milk cavity" and the through hole in the corner of the m-round cavity 48 are rounded or chamfered. The 3〇e diagram illustrates a non-retraction 11 deposition having a tapered sidewall profile of the upper chamber, which may be preferably in situ (i.e., in the same chamber) during deposition of the stone Excessive mode (ie, transfer between the deposition chamber and the etchback chamber) performs multiple PVD11 deposition and rf bias wafer (4) steps to achieve a near C-degree angle of the Shi Xi deposition profile to obtain this guarantee Forming a stone deposition process. Once a 45 degree angle is reached, for example, a net deposition of 〇3 _ on a characteristic of 〇·3 μπι high (Fig. 3) or a net deposition of about ι _ on an extremely deep feature (Fig. 16), after a less frequent etch back step, the 'deposition equilibrium' can be composed of a combination of normal, unbiased or thicker non-biased films, which may be required. Oxidation joints in the rafts caused by the underlying topography. The objectives of these 矽 deposition/eclipse processes Therefore, the receding suspension structure is eliminated and the seam in the deposition crucible caused by the appearance of the shape of the shape 20121325 is reduced or eliminated (Fig. 35a). This case illustrates the corner of the MEMS structure compared with the 35b diagram. Oxide seam ^). This non-retracted PVD矽 deposition process is combined with lower chamber pressure deposition for bottom and sidewall deposition, and the non-retracted pvD矽 deposition process uses germanium chamber pressure etching, in which rf bias is applied to the crystal Round, to maximize the top surface and corners (four) ^ repeat the steps of low pressure deposition and high pressure touchback in sequence until the desired thickness is reached. In an example I. Straining towel, lower pressure deposition (eg, <6 mTorr) and high pressure (for example, > 10 mTorr) etch back step thickness values are approximately deposited 1〇_5〇11111 and eclipse i 5 25 nm, for example, the button 矽 removal is less than the deposited thickness And, as mentioned below, the thickness of the first layer of dreams can be increased to, for example, 50 coffee or (10) to avoid smashing to the characteristic corner towel. In addition, this sequence allows for increased film density on the sidewalls and tapered surfaces. Thereafter, the surface area is minimized to reduce the amount of surface oxidation. Alternatively, a PVD7 deposition and (4) process can be used, where the bias sputtering & is used to extinguish the wafer and the wafer is biased to establish a 45 degree sidewall angle. This is critical for achieving stable opening performance of Si because of any oxidation 1 . After the repeated argon sputtering back to the surname step to obtain the desired 45 angle 'and after obtaining the desired 45 degree angle of the I# ^, the Shi Xi deposition process can be restored to the urgent name, said The normal deposition process of the ., , and helium sputtering steps. The offset 矽 deposition system Miao Tiantian recognizes this process applied to the lower jaw cavity layer 18, gaps and seams. During the initial deposition process, the & 矽 should be noted to avoid sputtering 颂绥駚 + Α 蚀 eroded to the H edge or other material from the corners of the feature. 38 201213225 The corners 4第5 in the 3rd graph can be chamfered by 45 degrees by this in-situ or non-in-situ sputtering method, resulting in redeposition of the oxide layer 46 into the stone's The presence of Si〇2 in the sputum makes it difficult to open the hole. To avoid (4) sputter exposure during the initial accumulation, an initial non-biased layer can be deposited, for example, 50 nm or 100 nm. When the MEMS beam is released or cooled, the release @mems beam will bend upward or downward as the electrode with a larger amount of metal expands or contracts more than the electrode with a smaller amount of metal. Figures 29 and 2 show the beam using the layout shown in Figure 28, and (10) the variation of the bridge beam bending for temperature. As mentioned above, the mems beam is bent because the CTE between the oxide in the beam and the metal does not match. The main metal in the beam (for example, 'Fantasy has 15G_25()<t yield stress temperature. It is known in the art that the yield stress temperature occurs when the residual stress in the aluminum is no longer changing with temperature. Bending at the yield stress temperature Variable flat or more common is reverse (curve B or e in Figure 29). MEMS bridge beams with balanced metal have the least bending with temperature; beams with larger upper electrodes increase with increasing temperature Bending; beams with larger lower electrode turns downward with temperature. It should be noted that if the bend of the MEMS bridge beam is large enough, the beam will be bound by the cover above the MEMS beam or the fixed electrode below the MEMS beam (p. Figure 29 Curve A or F). For the reasons stated above, the most desirable MEMS beam bending with temperature changes to minimize the total bending. The use of the MEMS curved profile is initially bent upwards over the temperature range of interest and then The MEMS beam thickness of the lower bend (ie '29th ® curve' line C) can achieve this; 39 201213225 or vice versa. To achieve such a MEMS beam bending curve may require deliberate lower electrode amount and upper electrode amount In an exemplary embodiment, the ratio of the pattern factor of the lower electrode 38 to the upper electrode 44 is 0.8:1; the beam oxide is 2 μm thick, and the lower electrode has a thickness of 45 μm of unreacted A1Cu containing 45 〇 nm. The total thickness is and the lower electrode has an unreacted AK:U thickness of 370 nm and a total thickness of < μιη. This combination produces an unbalanced amount 8 and an electrode 44, ', Ρ, the ratio of the electrode 38 to the electrode 44 is 〇9 ^ Α; μ. r 1 ' and this combination produces a minimum beam bending change with temperature (in the temperature range of interest C of the curve C).

40 201213225

F 1:0.5 2 μηη Low bending bound by the lower fixed electrode This bending of the MEMS beam after this release can cause two problems, as mentioned above · a · during normal wafer operation 'eg 'from '-5 5 ° C To 12 5 , MEMS beam bending will increase or decrease the actuation gap, resulting in a corresponding change in the actuation voltage; and b. if the released MEMS beam is warmed to a high temperature (eg, > 15 (rc, eg, 400°) C), this condition may be caused by normal processing after opening or removing the sacrificial material. Then the released MEMS beam will be mismatched due to thermal expansion between the upper MEMS beam electrode and the lower MEMS beam electrode and the beam oxide. Bending upwards, downwards or upwards and downwards, and if the bend is large enough, the bend is bound by a cover on the MEMS beam or a fixed electrode under the MEMS beam. Bound MEMS beams during annealing can be reduced, unwanted Curvature, resulting in a curved (ie, uneven) MEMS beam. A curved MEMS beam will have a reduced contact area, resulting in a reduced electric valley. In addition, if the MEMS beam abuts against a fixed electrode or beam below the beam Applied by the top cover If it is too high, the MEMS beam or cover may be broken, thereby causing a catastrophic failure of the MEMS device. In Fig. 15, an insulator material 46 is deposited on the exposed portions of the upper electrode 44 and the insulator material 4A. In an embodiment, The insulator material 46 is deposited to a thickness of about 80 nm; however, the present invention also contemplates that the other ruler 201213225 inches is a balanced MEMS beam, and the insulator material 46 above the MEMS beam should be substantially the same thickness as the insulator material 34 beneath the MEMS beam. This thickness balance with layer 46 should include any additional dielectric deposition on layer 46 that occurs during the subsequent vent dielectric deposition sealing step. Cavity vias 48 are formed by patterning and etching through the insulator. To pass through the insulator materials 34, 40 and 46 to the lower layer 18. In an embodiment, for example, HF acid may be used to clean any undesired oxides on the crucible prior to subsequent niobium deposition, such as by 矽丨8 Exposure to natural oxides formed by air. It is desirable, but not required, that the sidewall angle of the cavity vias 48 be tapered to improve subsequent sidewall deposition and reduce seams in the crucible or In Fig. 16, a layer of germanium 5 is deposited on the structure of Fig. 15. In an embodiment, layer 50 may be deposited to a thickness of about 4 pm; however, other dimensions are also encompassed by the invention. The deposition of the ruthenium layer 5 〇 shows that the morphology of the shi layer 50 varies according to the characteristics of the underlying layer. The fracture layer 5 〇 can form a regressive shape above the via 42 and the via 48, during subsequent oxide deposition. The oxide may fill the retracted structures in a rivet-like manner such that rivet-like oxide nails are present over the vias 42 and vias 48. The rivet-like oxide features in the cover may pin the post-release MEMS beam. In order to avoid this MEMS beam pinning, it is necessary to optimize the hard layer 5〇 deposition process to avoid this shape (Fig. 30e); or to require a sufficiently thick layer of stone layer 5 to pinch or partially pinch the through hole 42 and pass The opening of the aperture 48 (Fig. 3D); a tantalum deposition, CMp and subsequent tantalum deposition similar to that previously described for the tantalum layer 18, or a combination of the above. Further, as shown in Fig. 16, 42 201213225, the layer 10 is passed through the through hole 48 to be in contact with the lower layer 18. In an embodiment, no oxide will be present between the two layers (e.g., layer 18 and layer 5) due to HF acid cleaning. In an optional embodiment, the enamel layer has an initial thickness of 3 micrometers. The ruthenium layer undergoes an i-micron CMp removal, and the ruthenium layer has a second radiant deposition to achieve a thickness of 4 μηη. In the optional embodiment illustrated in Figure 17, the germanium layer 5 can undergo an optional lithography process and RIE process using a reverse mask, similar to that described above. The reverse mask will place the photoresist over the vias 42 and vias 48 such that the fields are etched and cleaned using RIE or wet chemical knurling processes, and subsequent resist stripping and cleaning. The reduction is introduced to the topography of the subsequent CMp step. The reverse mask shape needs to completely cover the vias 42 and vias 48 so that they will not be etched along the sidewalls of the trench, as previously described with respect to Figure 6. Figure 18a illustrates the patterning and etching of a germanium layer 50 using methods similar to those previously described with respect to Figure 3. In Figure 18a, the tantalum layer 50 is subjected to a CMP process to planarize or partially planarize the tantalum surface and thereafter the tantalum layer undergoes cleaning. As previously mentioned, any crucible grinding process can be used, and if a process with low or no selectivity to Si〇2 is used, the possibility of point defects on the crucible surface is eliminated. In this embodiment, the germanium layer 50 is patterned such that the germanium layer 50 remains in the previously formed vias 48 and the trenches 46 formed. In an embodiment, the germanium layer 50 can be planarized using conventional CMp processes with or without reverse mask patterning and etching processes. For CMP only or reverse mask etch back followed by cMp, an optional second germanium deposition may be performed after HF cleaning. Alternatively, 43 201213225 may optimize the deposition of the germanium layer 50 such that the germanium layer deposit fills the vias 42 and vias 48 in a conformal manner; or the germanium layer deposits the pinch-off vias 42 and vias 8 as described above and below. This will ensure that the subsequent cover layer $* will not extend to the rivet-like feature towel formed over the through hole 42 and the through hole 48, and that the rear cover layer only extends into the rivet-like feature to potentially cause frictional resistance. By MEMS beam, as described above. That is, in an embodiment, the process will also advantageously result in a flat or substantially flat cavity structure (e.g., a flat or flat surface) in subsequent processing steps. The optional steps in the figure can help the subsequent etching/planarization of the germanium layer 50. If the wavelength of light is used for subsequent lithography alignment, any other planarization of (10) or (iv) 5G cannot be completely flattened on the wafer. All of the features are: to avoid the complete flattening, the through holes 42 and the through holes can be stacked on the side of the functional integrated circuit, so that even if the flat holes 42 and the through holes 48 are flattened, the The stacked via structures 42 and the vias 48 are planarized. As shown in the 19th & figure, the oxide material 52 can be planarized such that the oxide remains in the layer 5 〇p 士 / & 1 ^ , above (Fig. 19a), or the oxide material 52 yF layer $ layer 5〇平齐' is similar to that previously shown in Figure 8. Whether or not the oxide layer 52 is flattened back to the surface of the layer, it may be desirable to deposit additional dielectric to square the desired oxide cap thickness on the mems cavity, as described below. Alternatively, as shown in Fig. 19b, the oxide layer 52 may be partially planarized; or the oxide layer 52 may not be planarized. As an optional step very similar to that shown in Figure 9a, the oxide material can be deposited to a thickness of about $ _ with a ratio of 2·3 μπ, 44 201213225 wherein the Si layer, for example, is deposited on a thick oxide material . Using a conventional process (eg, CMP) to planarize the Si layer (and a portion of the oxide material for the initial oxide deposition or all of the film, the oxide material 52 deposition process should adequately fill the line layer 44 spacing by, for example, , depositing an initial oxide medium with HDPCVD oxide to fill the gap, depositing 7 button/deposit oxide or PECVD based on the oxide of te〇s, so that the voids of the oxide layer do not cross the CMp to planarize the oxide surface In the case of all such embodiments, the reverse pattern etch back step shown in Figure 18a is optional. If the germanium layer 50 is not fully planarized, as shown in Figure 16, the oxide layer The surface of 52 will be along the surface topography of the crucible layer, as shown in the figure. In the case of the introduction of the topography shown in Fig. 19c, the oxide CMP step is stepped with or without reverse inlay (four). The presence of the via-like vias 48 does not completely planarize the surface of the oxide layer from 5 to 2, resulting in the resulting profile shown in Figure 19d. It should be noted that the surface profile shown in Figure 19d may also be In the 19th picture with the overlap on the shape of the (10) figure Alternatively, if the optional oxide etch back step is etched down to the tantalum layer 5', the oxide above the via 42 and via 48 will extend below the surface of the tantalum layer. The topography above the apertures 42 and vias 48 can create trenches in the surface of the finally segmented wafer, for example, due to, for example, water being collected in the trench during the humidity-1 force stress of the packaged wafer. In order to avoid this problem, the oxide layer W may be deposited to a thickness such that the vias 42 and the openings above the vias 48 are pinched off; 45 201213225 or the planarization of the oxide layer 52, The final surface is flat as shown in Fig. 9a. Alternatively, the reverse pattern (four) mask can be modified so that the mask opening is removed in the area around the through hole 42 and the through hole fill. A top view of the cavity 5, the through hole 42 and the through hole 48. If the reverse pattern is used to return to the silver process together with the barrier through hole 42 and the through hole 48 (Fig. 19f), the through hole 42 and the through hole 48 are used. The oxide will not be left in the (wth figure) and will more easily planarize or substantially planarize the oxide The surface of 52. The optional oxide CMP process for planarizing or partially planarizing the oxide layer μ can scratch the surface. Examples of surface to trace are shown in Figure m. Opening or removing the river After sacrificing the cavity layer 18 and the MEMS sacrificial cavity layer 5G, these surface-to-marks can serve as a crack nucleation point. To eliminate this problem, an optional second dielectric or oxide deposition is performed to deposit the 19h chart. The layer 4 is shown. In Figure 20, the oxide material 54 is shown on the surface, and the oxide material 54 determines the thickness of the cover prior to opening the hole. For example, the oxide material 54 can be opened prior to opening. There is a thickness of about 3 μηη. If the oxide layer 52 over the layer 10 is not removed or completely removed, the total oxide thickness of layer 52 and layer 54 prior to slitting will determine the thickness of the lid. The venting opening 58 is patterned in the embodiment and the venting opening is opened in the oxide cover to expose a portion of the lower layer 10. It should be understood that more than one venting opening 58 may be formed in the oxide material 54. The venting opening 58 can be formed using conventional lithography and etch engraving processes known in the art. All of the patterned features discussed in this disclosure use conventional, for example, stepper or 46 201213225 proximity lithography tools (using a reticle) to: "p[alpha] in such techniques.习Use conventional lithography, including masking ten craftsmanship plus special emblem, W Dan: Β, Ι feature size 'that is line width, and current ',> 舻 mutual a, the characteristics of the imaging and wafer The overlap or overlap between the earlier layer features, 1 wau, * the 4 additional features placed in the split channel between the active wafers. However, the additional features can also be placed in the wafer Or you can use the live ^ ^ ^ B f 曰曰 feature. In order to make the printing, the "active characteristics in the performance", important but not required: 'copy the earlier layer features. For example, for the vent 58, the structure outside the active wafer is used for measurement. If the feature size or overlap, the structure should be stacked on top of the upper ridge cavity and (as needed) above the other lines in the cavity' such that the height and measurement characteristics of the wafer are optical (ie, reflective) and The same is true in the active wafer. This is especially important for venting Μ because the vent has a relatively small width, and depending on the process used to planarize the upper cavity, the upper cavity can extend beyond the surrounding wafer surface 1 If the vent hole resist width is measured outside the cavity, this condition may cause the problem that the vent hole 58 is printed on the cavity. The width of the vent hole 58 and The height determines the amount of material that should be deposited to pinch the vent after the boring. In general, when the vent width is reduced and as the vent ratio increases, it should be deposited to pinch off the vent 58. The amount of material is reduced, and the aspect ratio of the vent is high For the ratio of widths, in an embodiment, a 3 μm thick open-cell front cover will have a 丨 diameter. In the embodiment, 'the HF solution can be used to clean the structure before the opening 且 and specifically the exposed lower layer 矽If the vent hole 58 47 201213225 has the same aspect ratio or if there are too few vent holes, it is difficult to discharge the sacrificial cavity material 18 and the sacrificial cavity material 50. The vent hole may be annular or a few : is circular 'to minimize the need for subsequent material s to pinch the vent. In an exemplary embodiment, the vent is shaped in an octagon, as described above to minimize calculation requirements The right cover is too thin relative to the MEMS cavity area, and after the opening or during any subsequent film deposition, the cover on the evacuated or drained cavity may be bent upward due to yttrium film stress or due to MEMS beam annealing during annealing Crack or knife layer against the cover. For example, 'covered with an i (four) oxide cover (4) multiplied by 500 μm of the cavity after the opening or after the subsequent sealing film deposition, will cover oxide or seal Residual stress of the film or because of annealing The interleaved MEMS beam pushes up against the cover and is prone to cracking or delamination. In an exemplary embodiment, each 1 〇〇〇〇μπι cavity region requires an oxide cap of approximately 1 micron to avoid opening Thereafter, the cover is broken. In Fig. 21a, the ruthenium layer 50 and the ruthenium layer are opened or etched through the vent hole 58. In the embodiment, the XeF2 etchant may be used to perform the detachment through the vent hole 58 ( For example, etching) This etch will strip all of the material (the formation) to form the upper cavity or chamber 6〇a and the lower cavity or chamber 60b, and this etch has a choice for many other materials, including Si〇2. As shown in this representation, the upper cavity 6〇a and the lower cavity 6〇b have flat or nearly flat walls due to previous etching steps of the ruthenium layers 18, 50. Optional HF can be performed before the opening 矽Clean to remove the native oxide and hydrogen passivate the exposed surface. As shown in FIGS. 21b and 21c, the venting holes 58 may be formed at a number of positions at 48 201213225, forming portions of the upper sill layer 50, the lower layer 18, or both the upper sill layer 5 〇 and the lower sill layer 18 ( Exposure part). For example, as shown in the second aspect, the vent hole is formed inside and outside the cavity through hole 48. The venting holes 58 should be round or nearly circular to minimize the amount of insulation required to pinch the vents after opening. An octagonal shape can be used to draw the exhaust through holes to minimize the computational workload required to process the design data, as described above. In this embodiment, the etch rate of the ruthenium layer 5 in the upper portion 59a will be etched faster than the ruthenium layer 18 in the lower portion 59b, thus ensuring that no excessive stress is placed on the lower portion 59b, as shown in the figure (10). . (The upper portion 59a and the lower portion 59b will form a cavity above and below the MEMS structure.) Figures 2 and 21e show a more detailed cross-sectional view of Figs. 21b and 21c. As shown in the 2nd figure, the vent hole 58 is formed to be part of the upper layer 50 and the lower layer 18. In this embodiment, as seen in Figure 2^d, the lower layer 18 will actually support the upper portion 59a since the lower layer is etched at a slower rate. In Fig. 21e, the vent hole 58' may be formed at several positions but mainly formed to the (exposure) layer 18. In this embodiment, the etch rate of layer 18 in lower portion 59b is faster than the 矽 layer in upper portion 59b, thereby creating the potential for additional stress on MEMS beam 00. (For example, MEMS beam 60 may be partially or fully Rip off or tear off). If the venting arrangement is such that the lower cavity 18 is opened faster than the upper cavity 50 (e.g., by placing the venting opening in the through hole (cavity through hole) as shown in Figure 2 ic 48 Outside) 'The lower cavity can be opened before the upper cavity. This can cause stress-related rupture problems, as shown in Figure 2 1 c. When the lower layer 18 of the 2012201213225 is almost completely open but still extends the full height of the cavity and the upper cavity layer 5 is not completely open and does not extend to the full height of the upper cavity, the cover and the beam are bent upwards. The stress can tear the oxide 6 〇 from the lower cavity as shown in Figure 21c. For these reasons, it is desirable to place the venting hole above the upper cavity such that the upper cavity opens in front of the lower cavity. In Fig. 21f, the chamfered lower cavity a and the chamfered upper cavity b are rotated by 4〇5 (see also, for example, Fig. 21b, the chamfering of the cavity is chamfered after the opening of the opening: >, stress, The result is a reduction in the likelihood of dielectric film rupture caused by temperature cycling or other stresses. A 45 degree chamfer 405 is illustrated; however, any chamfer angle is contemplated, including a rounded corner (also indicated by component symbol 405). As mentioned above, in contrast to making the corners round, the chamfering of the corners reduces the computational complexity associated with verifying that the layout does not violate the minimum row and spacing rules. It is also possible to have through holes 42 and through holes in the cavity. Chamfering, as described below. In Figure 21c, the venting opening 58' can be formed at several locations to expose the lower layer 18. In this embodiment, the layer 18 in the lower portion will have a higher engraving rate than the upper portion 59b. In the middle of the stone layer 5 〇 faster, can also make any line | 14, 38, 44 corner chamfer (as shown in Figure 22) to reduce the total stress. As shown in Figure 22, The venting opening 58 is sealed using a material 62 such as a dielectric or metal. If the sealing material 62 is on the beam Depositing a film in the cavity can potentially unbalance the stress of the MEMS beam and also bond the cover to the beam in the area around the via, as described herein and as described by Figure 25 To avoid this, in embodiments where the aperture seal 50 201213225 material is deposited in the cavity, it should be sufficiently far away from the via (eg, greater than 1 micron or, in an exemplary embodiment, More than L micron) Place the venting hole 'so that the released MEMs beam is not bonded to the cover by the opening (4) deposition. Or 'The venting hole can be placed in the cavity area away from the MEMS beam' so that there is no venting hole A sealing material is deposited on the released EMS beam. Next, an optional layer 64 is deposited to provide a hermetic seal. Layer 64 can be, for example, an nmpECVD nitride film or other known film to provide gas on oxide layer 62. In Fig. 23a, the final via 66 is opened in the structure of Fig. 22. In the embodiment, the via 66 exposes the lower electrode 44. In an embodiment, a conventional lithography and etching process is used to form Through hole 66. In a further embodiment, the through hole is formed For example, an optional polyimide (polyimide W 68) may be deposited on the nitride cap layer 64. The problem of forming this final via is that the height of the final via is caused by the planarization of the upper cavity, which is 6 Within the range of -12 μηι. The long dielectric RIE step causes problems with the RIE tool due to chamber overheating or other problems; or simply because the steps have an hourly processing time with a low portion and are expensive 0 Figure 23b And Fig. 23c illustrates an alternative process for forming a via. For example, a portion of the via hole 66a can be formed while forming the vent hole 58. (After forming the vent hole 58 (and subsequent layers 50, 18) After cleaning, the dielectric material 62 and the nitride cap 64 can be used to seal the venting opening 58. In this option, the final via 66 is formed by using two separate patterning and etching steps, which reduces the amount of time required to fabricate the MEMS device and also tapers the angle of the final via. Therefore, the improved error-free (pb_free) bump gap filling is improved. In an embodiment, an optional polyimine or other polymeric coating material 68 known in the art can be deposited on the nitride cap 64. A dielectric material 62, a nitride cap 64, and a polyimide material 68 will also be formed in a portion of the vias. Thereafter, the remaining portion of the via hole can be formed by etching through the dielectric material 62, the nitride cap 64, and optionally the polysilicon: material 68 to the lower electrode 44. The 'partial through hole' indicated in this representation has a larger cross section than the through hole (10). For example, the vias may be about 6 μm span (eg, 'diameter); and the vias 66b have smaller dimensions, such as Η micron and 'total height of vias (formed by vias 66a and vias (10)) ) can be about 9 microns. In an embodiment, 'optionally the polyimine opening is smaller than the oxide opening "column, for example, 48 microns" to cover the corner of the oxide/nitride interface at the corners of the line. Figure 24a - Figure 24f illustrate fabrication in accordance with the present invention Various top views of the structure. 帛24a图_24c illustrates different cross-sectional views of the first structure according to the present invention; and 24d-24f illustrates different cross-sectional views of the second structure according to the present invention In the case of a sweater, the % diagram is a top view of the cantilever beam structure having a lower cavity 200a lower working chamber 200b. The cavity through hole 21 is between the upper cavity 2a and the lower cavity Mob. The cavity through hole is a "u" shaped or Ί 1" shaped through hole in the embodiment, although other shapes are also contemplated by the present invention. The width of the cavity via 210 can be, for example, about 1 micron to 1 micron, and the length of the via is about 1 micron to 1 micron. In an exemplary embodiment 52 201213225, the cavity via 210 is 4 microns wide and 1 〇 τ see Han υ 微 micro water length. As discussed, 'if the cavity via is sufficiently thick (eg, 5μη〇, the narrow cavity via (eg '2叩 wide) will pinch off during deposition of the upper cavity, which reduces the entry of niobium oxide Extension in the through hole. The upper cavity 2〇〇a and the lower cavity 2〇〇b (as previously described herein) may be the same size or different sizes. CMP treatment to form a flat lower cavity (denoted as 200b) A surface curvature may be created on the edge of the cavity. To avoid curvature of the surface of the MEMS beam, the cavity via 48 is placed such that the inner edge of the cavity through hole exceeds the curvature and is on the flat portion of the lower cavity. Figure 24b also illustrates a cavity through hole 21A that extends between the upper cavity 200a and the lower cavity 200b. In addition, Figure 24b shows a parallel first actuator 215 and A second actuator 215. The capacitor head 220 is provided with respect to the first and second actuators 215, which may be a lower fixed capacitor in accordance with aspects of the present invention. These lines (i.e., line 215 and Line 220) is formed from layer 14 as shown in Figure 22. Those skilled in the art will recognize that The first and second actuators (electrodes) 215 can be wires, as described above. The first and second actuators (electrodes) 215 will produce MEMS beams after actuation (ie, application of sufficient dc voltage) Bending, Fig. 24c shows a cavity through hole 210 extending between the upper cavity 200a and the lower cavity 2〇〇b. In addition, '24c illustrates parallel first and second Actuator 215a. Capacitor arm and head 220a are provided with respect to first and second actuators 215a, which may be root 53 201213225. A lower fixed capacitor plate according to aspects of the present invention. Capacitor arm and The head 220a extends between the first actuator 215a and the second actuator "between the edge of the cavity and the capacitor head. The MEMS capacitor is formed in the element 22" (in the Mb diagram) and the element 22a (in Figure 24c). Actuator 215a and capacitor arm and head in Figure 24c are "consisting of line 38 and line 44 in Figure 22, and as shown, the actuator The capacitor arm and the head system are connected by a through hole 228 as described below. In addition, FIG. 24c illustrates the electrical via 228'. The hole system is connected to the lower line and the upper line of the cantilever beam. The electrical through hole 228 can also be connected to the capacitor arm 220a, and the capacitor arm 22〇a extends between the actuators 215a. These through holes are shown in Fig. 22. Shown as 42. An oxide nail 225 is provided below the beam, and the oxide nails can extend to the capacitor arm 220a and the actuator 215a. These oxide nails 225 can also be above the actuator 215 of Figure 21b. Figure 24c also shows oxide nails 225 below the beam. In Figure 22, the oxide nails are element 33. At operation ten, electrode 215a will produce a bend of the MEMS beam after actuation. In normal MEMS operation, an actuation voltage is applied between actuator 2 15 and actuator 2 15 a. For example, actuator 215 can be grounded and 50 V can be applied to actuator 215a; -25 V can be applied to actuator 215 and 25 v can be applied to actuator 215a; 50 V can be applied Applied to the actuator 215 and the actuator 215a can be grounded, and the like. These MEMS layouts have four separate inputs, a lower capacitor input, an upper capacitor output, a lower actuator, and an upper actuator. As is known in the art, the four electrodes can be combined. For example, the upper actuator 54 201213225 215a and capacitor 220a may be comprised of a single connection line; the lower actuator 215 and lower capacitor 220 electrodes may be comprised of a single line; or both. For such simpler two or three input devices, it would be necessary to decouple the parent current (ac) signal and dc, for example by using an inductor wired to ground or the dc voltage on the electrode. Actuated. Figure 24d - Figure 24f illustrate different cross-sectional views of a second structure in accordance with the present invention. More specifically, Fig. 24d illustrates a top view of the cantilever structure. The 5 cantilever beam structure has an upper cavity 3〇〇a and a lower cavity 3〇〇b. The cavity through hole 310 extends between the upper cavity 300a and the lower cavity 300b. In an embodiment, the cavity via 310 includes parallel strips, although other shapes are also contemplated by the present invention. The width of the cavity through hole 31〇 may be, for example, about 〇丨 micrometer to 100 μm, and the length of the through hole is about i micrometer to 1 〇〇〇 micrometer. In one exemplary embodiment, the vias 31 are 4 microns wide and 1 microsecond long. Fig. 24e also shows a cavity through hole 31, which extends between the upper cavity 300a and the lower cavity 300b. In addition, the second map shows the first, second, and third actuators 315. In an embodiment, the first and second actuators are parallel' and the third actuator is a lower actuator. The capacitive tamper 320 can be used to secure the grid electrode plates in accordance with aspects of the present invention in the first actuator and the second actuator and the third (lower) actuation of the gates 320. These lines (i.e., lines 315 and lines) are formed by layers 4 as shown in FIG. Those skilled in the art will recognize that the second and second actuating thieves (electrodes) 315 can be wires, as described in 55 201213225. The first, second and third actuators 315 will produce a bend of the MEMS beam after actuation. The Fig. 24f shows a cavity through hole 310 which extends between the upper cavity 300a and the lower cavity 300b. In addition, Fig. 24f illustrates first, second, and third actuators (electrodes) 315a. The first, first and second actuators (electrodes) 3 1 5a are provided. The capacitor head and arm 32A extend between the first actuator 315a and the second actuator 315a. The actuator 315a and the capacitor arm and head 320a in Fig. 24f are composed of line 38 and line 44 in Fig. 22. In addition, the 24th f diagram illustrates an electrical via 3 2 8, which is connected to the lower and upper lines of the cantilever beam. Electrical vias 3 2 8 may also be connected to capacitor arms 320a. Oxide nails 325 are provided below the beam and the oxide nails can extend to the capacitor arm 32a and the lower actuator 315c. In operation, the first, second, and third actuators (electrodes) will produce a bend in the MEMS beam after actuation. More specifically, the lower actuator will apply a voltage to the actuator (electrode). In both cases, if the MEMS device is a capacitor, the MEMS beam comprises a metal/insulator/metal with an additional thin insulator layer below and above the stack. If the device is a capacitor, an exemplary embodiment would use a metal thickness below 0.5 microns and an upper metal thickness and a 2 micron insulator thickness with an 8 〇 nm insulator layer above and below the beam. In addition, the actuator 215 (Fig. 24a - Fig. 24c) or the actuator 315 (Fig. 24d - Fig. 24f) will be grounded such that when an actuation voltage is applied to the actuator, the MEMS beam will cause Move and bend downwards, as is known in the 56 201213225 technique. Alternatively, an actuation voltage can be applied to the actuation electrodes in Figures 24c and 24f, and the actuators in Figures 24b and 24c are grounded. In another embodiment, the actuator will be connected to the capacitor and I will be required to ground the actuator and the capacitor using a dc ground wire, such as an inductor.

Figure 30a - Figure 30e Figure 1000 y* 〇 This / L circle is not in the upper cavity 矽 50 surface glaze after the non-conformal 矽 deposition step has been performed, open 乂 ' 'The surface topography is not pinched off The electrical through hole 42 and the cavity through hole 48 are known as openings. Unbiased PVD矽 deposition will form a 'bread block, shape,' as shown in Figure 30a, as is known in the art. Figure 30a - 筮因士向_弟 3〇e diagram also shows the oxide nail i6a. The ruthenium layer 50 is retracted by f ^ (ie, having undercuts) to cover the sidewalls of the vias, and when the MEMS cavity f is deposited, such as 'Si02, the cap material will fill the vias 42. And pass 4R ^, the upper back exit, as previously described. If the beam is bent upwards after the opening, the rivet-like feature (250) in the cover is rubbed and/or the rivet-like squirrel-like structure is bonded to the beam (255) (see for example 31))] In Figure 16, the τ τ τ τ τ 石 石 石 石 石 石 石 石 石 石 石 石 τ 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 空腔 τ . In Figs. 31-33 and 篦-solid and Fig. 35, the telluride material 54 is shown on the surface, and the thickness of the cover is determined before the oxide material 54 is cut into the holes. In an embodiment, the venting opening is opened in the oxide cover, thereby exposing

One of the 5 〇 石 石 夕 夕 夕 。 。 。. _ A P knife It should be understood that more than one venting opening 58 may be formed in the oxide material 54. The venting holes can be formed using conventional lithography and etching processes known to those skilled in the art. Vent hole W 57 201213225 曰 在 在 在 在 在 夕 夕 应 夕 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 寺 寺 寺 寺 寺 寺 寺 寺 寺 寺 寺 寺Material 62, such as a dielectric or metal, may be used to seal vent 58 as described above. , 34 ® is a % flow diagram for the design process used in semiconductor design, fabrication, and/or testing. Figure 34 illustrates an exemplary design flow for use in, for example, semiconductor 1C logic design simulation, testing, layout, and fabrication. The design flow 900 includes processes, machines, and/or mechanisms for processing design structures or devices to produce the designs described above and illustrated in Figures 33 and 35 of Figure 1. A logically or functionally equivalent representation of a structure and/or a shock. The design structure processed and/or generated by the design stream 900 can be encoded on a machine readable transport or storage medium to include data and/or instructions for execution or processing of the data and/or instructions on the data processing system. A logical, structural, mechanical, or functional equivalent representation of a hardware component, circuit, device, or system. Machines include, but are not limited to, any machine used in a design process (such as 'design, manufacture, or analog circuits'), components, and devices. For example, a machine may include: a lithography machine, a machine and/or equipment for generating a mask (eg, an electron beam writer), a computer or equipment for simulating a design structure, poetry manufacturing or testing Any device or any device used to design a functionally equivalent representation of the design to any medium (eg, a machine for programming a programmable gate array). The design flow _ can vary, depending on the type of representation being designed. For example, 'for building special application integrated circuits (Appiicati〇n 58 201213225

The Design Process 900 of the Specific Integrated Circuit; ASIC) may be different from the design flow 900 for designing standard components, or may be different from being used to translate a design into a programmable array (eg, by Altera® Inc. or Xilinx®) The design flow 900 of a programmable ram array (PGA) or field programmable gate array (FPGA) provided by Inc. Figure 34 illustrates a plurality of such design structures including input design structure 920. The input design structure is preferably processed by design process 910. Design structure 920 can be a logic analog design structure that is generated and processed by design process 910 to produce a logically equivalent functional representation of the hardware device. Design structure 920 may also or alternatively include data and/or program instructions that, when processed by design process 910, produce a functional representation of the physical structure of the hardware device. Regardless of the functional and/or structural design features, an electronic computer-aided design (ECAD) can be used to generate the design structure 920, such as implemented by a core developer/designer. When encoded on a machine readable data transfer, gate array or storage medium, the design structure 92 can be accessed and processed by one or more hardware and/or software modules within the design process 91 Analog or functional representation of electronic components, circuits, electronic or logic modules, devices, devices or systems such as those shown in Figures 1 - 33 and 35. As such, the design structure 920 can include files or other data structures including Class A and/or machine readable source code, compiled structures, and computer executable code structures, such files or other 59 201213225 The data structure is functionally simulated or represented by other layers of the circuit or hardware logic design when processed by the design or analog data processing system. Such data structures may include hardware description language (HDL) design entities or other data structures such as other lowercase HDL design languages such as Verilog and VHDL and/or higher order designs such as c & c++ The language is consistent and / or compatible. The design process 910 is preferably used and incorporated into a hardware and/or software module for synthesizing, translating or processing the images shown in Figures iii - 33 and 35 The design/analog functional equivalent of a component, circuit, device, or logic structure to create a network connection table, which may include a design structure such as a design structure 92. The network connection table may include, for example, compiling or processing data structures such as compiling or processing data structure tables, recording elements, logic gate control circuits, and input/output (I/O) devices. A list of models, etc. that describe the connections to other components and circuits in the design of the integrated circuit. An iterative process can be used to synthesize the network connection table %〇. During this iteration, the network connection table 98〇 is synthesized one or more times, depending on the design specifications and parameters of the device. As with the other types described in this article, the network connection table 98 can be recorded on the machine readable data storage medium, or the network connection table program can be designed as a programmable inter-array 歹ij . The media can be a non-volatile storage medium such as a disk drive or a CD drive, a programmable gate array, a CF card ((7)(7), fl a s h) or other flash memory. Additionally or alternatively, the media may be a system or cache memory, buffer space or conductive or optically conductive device and material 60 201213225 、, 乂 by internet or other network connection suitable way in the system or cache The memory, the buffer space or the conductive or optically conductive devices and materials are loaded and the intermediate material data is encapsulated. The snippet process 910 can include hardware and software modules ▲ for processing various input data structure types including network connection tables. Such data structure types may be resident, for example, in library component 930' and such data structure types include for a given manufacturing technique (different technology nodes, 32 nm, 45 nm, 9 〇 (10), etc.): The set of commonly used components, circuits and devices 'includes models, layouts and symbolic representations. The data structure type may further include a design specification 94〇, a characterization-bean material 950, a verification data 96〇, a design rule 97〇, and a test data file 985, which may include input test patterns, output test results, and other tests. News. The design process 91 can further include, for example, standard mechanical design processes (such as stress analysis, thermal analysis, mechanical event simulation, process simulations for operations such as townships, tanning, and molding operations, etc.) It will be appreciated by those skilled in the art that possible mechanical design tools and applications can be used in the design process without departing from the scope and spirit of the invention. The design process 91 can also include performing standard circuit design processes. Modules, such standard circuit design processes such as timing analysis, verification, design rule checking, placement and routing operations, etc. Design process 910 uses and incorporates logical and physical design tools (such as HDL compilers and simulation model building tools) ), in conjunction with any additional mechanical design or documentation (if applicable), to process the design structure 92 and some or all of the supporting data structures in the supporting data structure of 201213225 to produce a second design structure 990. 990 Data format for the exchange of information on mechanical devices and structures (eg IGES, DXF, Paras〇Hd χτ , jt, drg stored information, or any other suitable format for storing or rendering such (4) design structures) resident on a storage medium or a programmable closed array. Similar to design structure (4), design structure (4) preferably includes Or a file or other computer-coded material or instruction, s or a broadcast, a material, or other computer-encoded data or instructions resident on a transmission or data storage medium, and when processed by the ecad system The logical or functionally equivalent form of the embodiment of the present invention shown in FIG. 3 and FIG. 35 is shown in FIG. 35. In one embodiment, the design structure 99 〇 can include a compiled, executable ship simulation model that functionally simulates the devices shown in Figures 1 - 33 and 帛 35. The design structure "〇 can also be used Data format and/or symbol data format used to exchange layout data of integrated circuits (for example, GDS2, GL1, 〇ASIS, information stored in the mapping file, or used to store such materials (4) Any of its (four) Design structure "〇 can contain greedy 'for example, symbol data, mapping (four), test transcripts, design content files, manufacturing materials, layout parameters, lines, metal layers, through holes, shapes' for Through the system [through the routing of the manufacturing line and by the manufacturer or other designer/developer to produce the device or structure as described above and 62 201213225: Figures 33 and 35 Anything, he may continue to proceed to stage 995, where, for example, the design structure (four) travels to the outgoing belt (called the call to the manufacturing) is released to the masking industry, sent to another - The designer, is sent back to the consumer, etc. The method described above is used in the manufacture of integrated circuit chips. The resulting integrated circuit die can be dispensed by the manufacturer in the form of bare wafers (i.e., as a single wafer having a plurality of non-packaged wafers), as bare die, or in a package. In the latter case, the wafer is mounted in a single wafer package (such as a plastic carrier having wires attached to a motherboard or other higher order carrier) or a multi-chip package (such as having a surface interconnect or buried interconnect or having The surface interconnect and the buried interconnect are both in the carrier. In any event, thereafter, the wafer is integrated with other wafers, discrete circuit components, and/or other signal processing devices as part of (4) intermediate production (such as 'board) or (b) final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices and central processing units. The terminology used herein is for the purpose of describing particular embodiments and is not intended to The singular forms "a" and "the" are also intended to include the plural unless the The phrase "comprising" and / or "comprising", when used in the specification, is used to specify the features, integers, steps, operations, components and/or components of the description, but does not exclude - or Other features, 63 201213225 The existence, or addition of a group, a procedure, an operation, an element, a component, and/or such other features, a whole, a step, an operation, an element, or a group of components. Where applicable, the corresponding structures, materials, acts, and equivalents of the various functional elements or step functional elements in the scope of the claims are intended to include any structure or material used to perform the function in conjunction with other claim elements such as the claim. Or action. The description of the present invention has been provided for purposes of illustration and description, and is not intended to Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the embodiments of the invention Various modifications of the present invention Although the present invention has been described in terms of the embodiments, those skilled in the art will recognize that the invention can be practiced in the spirit and scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS In the above detailed description, reference is made to the accompanying drawings in the claims Figures 1 - 23 and 26 - Figure 33 illustrate various structures and associated processing steps in accordance with the present invention; Figures 24a - 24f illustrate fabrication using a process according to aspects of the present invention. Top view of the MEMS device; 64 201213225 Figure 25 shows a number of topographical diagrams (ie, 'atomic force microscopy data') on the depth of the depression and oxide polishing; Figure 34 is for semiconductor design and fabrication. And/or a flow chart of the design process in the test; and Figure 35a illustrates the structure and process of reducing or eliminating oxide seams in the deposited crucible caused by the attractive morphology in accordance with aspects of the present invention (and figures) Figure 3b of the oxide seam is compared). [Main component symbol description] 10 12 Substrate interconnection/town interlayer 14 14' Line/wiring layer/lower electrode TiN/TiA13 layer/lower layer line 14a Wiring interval/wiring gap 16 Insulator layer/dielectric layer/spacer 16a Dielectric Nail/Oxide 16A Top Surface Nail 16B Side Surface 16C Bottom Surface 18 Sacrificial Cavity Material / Hair 18a 矽 Surface Α 夕 表面 Surface Curvature / Convex Layer 18b Shi Xi Surface / Concave Surface 19a Element 22 Second Layer 26 Resistance Money Depressor Void / Seam Insulator Material / Oxide Layer Resist Edge 65 201213225 28 Opening 30 "Frame" 32 矽 Layer 33 Trench / Oxide Nails 33a Oxide Nails 33b Oxide Nails 34 MEMS Capacitors 36 Tapered Through Hole Body Layer/Oxide Material/Dielectric Layer 38 Upper MEMS Electrode 40 Insulator Material/Insulator Layer/MEMS Beam Metal Layer 42 Tapered Through Hole/MEMS Space 44 Upper Electrode/Line Layer/Line Cavity 46 Oxidation Shield/Insulator 48 孑L/MEMS Cavity/Trap 50 矽Layer 52 Oxide Material/Oxide Layer 54 Cap Layer/Oxide Material 58 Vent Hole 59a Upper 59b Lower 60 MEMS 60a upper cavity/upper chamber 60b lower cavity/lower chamber 62 oxide layer/material 64 layer/nitride cap 66 through hole 66a partial through hole 66b through hole 68 polythenimine layer 200 lower MEMS electrode 200a upper cavity 200b lower cavity 66 upper MEMS electrode / empty 215 first actuator / second actuator / wire / electrode cavity through hole first actuator / second 220 capacitor head / line / component / lower capacitor / electrode capacitor arm and head / element 225 oxide nail / capacitor electrical through hole 250 rivet-like feature beam 300 step structure upper cavity 300b lower cavity shape configuration 310 cavity through hole first actuator / second 315a First actuator / second actuator / third actuator / third actuator / electrode / wire / electrode lower actuator 320 capacitor head / line capacitor head and arm 325 oxide nail electricity Through Hole 400 Layer Corner 900 Design Flow Design Process 920 Design Structure Library Component 940 Design Specification Characterization Data 960 Validation Data Design Rule 980 Network Connection Table 67 201213225

985 Test Data File 990 995 Stage A A1 Interval/Line Width A2 A3 Slot Interval BC Curve DE Curve F Ή Hole RR 'S' Slot TP Second Design Structure Curve / Chamfer Lower Cavity Slot Curve / Chamfered Upper Cavity Curve Curve surface to trace triple point 68

Claims (1)

201213225 VII. Patent application scope: 1. A method for forming at least one Micro-Electro-Mechanical System (MEMS), the method comprising the steps of: forming a wiring layer on a substrate; from the lower wiring layer Forming a plurality of discrete lines; and forming an electrode beam over the plurality of discrete lines, wherein at least one of the steps of forming the electrode beam and the plurality of discrete lines forms a layout that is minimal in subsequent tantalum deposition Protrusion and triple point. 2. The method of claim 1, wherein at least one of the plurality of discrete lines and the layout of the electrode beams are slotted or perforated. 3. The method of claim 2, wherein the slotted layout and the apertured layout comprise forming a cover at one end of the slotted layout or the apertured layout to avoid the triple point; or wherein The slotted layout has a width to pitch ratio of 1:6; or wherein the slotted layout or the apertured layout has a metal amount of about 20% or less relative to the electrode beam or the plurality of discrete lines, The amount of metal is removed by the holes or the grooves; or wherein for a higher line, the grooved layout or the metal removal of the perforated layout is more short, the shorter The line includes at least one of the electrode beam and the plurality of discrete lines. The method of claim 1, wherein the plurality of discrete lines are formed of aluminum or an aluminum alloy. 5. The method of claim 4, wherein the plurality of discrete lines are formed of the AlCu with Ti in at least one of under and above the AlCu and the method further comprises the step of annealing for a sufficient time, To form TiAl3; or the method further comprises the steps of: annealing the plurality of discrete lines after patterning and etching to reduce metal etching problems caused by TiAl3. 6. The method of claim 5, wherein the Ti reacts with aluminum to form the TiAl3, and a thickness of the AlCu is reduced by approximately a 3:1; or wherein the thickness is greater than 5% of a thickness of the AlCu And forming a thickness of one of Ti in a range smaller than 25% of the thickness of the AlCu. The method of claim 1, wherein the plurality of discrete lines are formed of a pure refractory metal to minimize protrusion formation; or wherein the refractory metal comprises at least one of the following metals: Ti, TiN, TiN, Ta The method of claim 1, wherein the plurality of discrete lines are solid; or wherein the electrode beam is formed by the Aicu with Ti in at least one of under and above the AlCu, And the method further comprises the following step 70 201213225: annealing for a sufficient time to form TiAl3. 9. The method of claim 1, wherein the layout comprises a slot and a hole, the spacing between the vertical end of one of the slots and one of the ends of the line shape being reduced to less than one of the discrete lines Width; or wherein the grooves are orthogonal grooves or angled grooves. 10. A method of forming at least one microelectromechanical system (MEMS), the method comprising the steps of: forming a lower wiring layer on a substrate; patterning the lower wiring layer 'to form a plurality of discrete lines; and wiring the wiring A MEMS beam is formed over the layer, and at least one of the steps of forming the MEMS beam and the plurality of discrete lines forms a layout that minimizes protrusions and triple points in subsequent > 11. The method of claim 1 , wherein: " 玄 complex number of discrete lines formed by Ming or Yiming alloy, the alloy comprising one of the following aluminum alloys: A1Cu, A1Si, and A1CuSi; The method further comprises the steps of: forming Ti under at least one of the underlying and upper portions of the alloy; and annealing the plurality of discrete lines for a sufficient time to form TiAl3, wherein the step of annealing the plurality of discrete lines is The patterning step 71 is provided after 201213225, and etching to reduce the metal etching problem caused by TiAU. 12. The method of claim 10, wherein a Ti thickness is formed in a range greater than 5% of a thickness of one of the aluminum alloys and less than 25% of the thickness of the aluminum alloy; or wherein the plurality of discrete lines Formed from a pure refractory metal to reduce protrusion formation; or wherein the perforated layout and the grooved arrangement comprise forming a cover at one end of the grooved layout or the perforated layout; or wherein one of the following occurs: One of the slotted layouts has a width to pitch ratio of 14, and the apertured layout has a metal amount of about 20% or less that is removed by the holes. 1 3. A structure comprising: a plurality of discrete lines on a substrate, the plurality of discrete lines being formed of AlCu with a Ti above and below to form TiAl3; and at least one a MEMS beam, the at least one MEMS beam being formed by the AlCu with a Ti in at least one of the upper and lower portions of the AlCu and the at least one MEMS beam is formed in a cavity and placed over the plurality of discrete lines, Wherein at least one of the plurality of discrete lines and the at least one MEMS beam is formed with a perforated or slotted layout. 14. The structure of claim 13 wherein an interval between the end of one of the slots 72 201213225 and one of the ends of the line shape is reduced to less than a line width. 15. A method for generating a function of a MEMS in a computer aided design system, the method comprising the steps of: generating a plurality of discretes on a substrate having a perforated or grooved layout One of the functional representations of the line 'The plurality of discrete vias are formed by forming a layer of AlCu above and below to form TiAl3; and producing a functional representation of at least one MEMS beam with a perforated or slotted layout' The at least one MEMS beam is formed in a cavity and placed over the plurality of discrete lines. 73