TW201143174A - Optoelectronic component - Google Patents

Optoelectronic component Download PDF

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Publication number
TW201143174A
TW201143174A TW100110253A TW100110253A TW201143174A TW 201143174 A TW201143174 A TW 201143174A TW 100110253 A TW100110253 A TW 100110253A TW 100110253 A TW100110253 A TW 100110253A TW 201143174 A TW201143174 A TW 201143174A
Authority
TW
Taiwan
Prior art keywords
photovoltaic element
lead frame
protective layer
semiconductor wafer
metal
Prior art date
Application number
TW100110253A
Other languages
English (en)
Inventor
Johann Hochmuth
Simon Jerebic
Original Assignee
Osram Opto Semiconductors Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors Gmbh filed Critical Osram Opto Semiconductors Gmbh
Publication of TW201143174A publication Critical patent/TW201143174A/zh

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52Encapsulations
    • H01L33/56Materials, e.g. epoxy or silicone resin
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58Optical field-shaping elements
    • H01L33/60Reflective elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H01L2224/48996Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/48997Reinforcing structures
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)
  • Photovoltaic Devices (AREA)

Description

201143174 六、發明說明: 【發明所屬之技術領域】 本發明係有關於一種光電元件,尤指一種具有導線架 之光電元件。 【先前技術】 上述光電元件之一範例爲發光二極體,或者光發射之 二極體(LED)。此光電元件具有發射輻射的半導體晶片,其 設於一導線架(lead frame)上。此導線架上設有一鑄體,其 可提供不同功能,如半導體晶片的保護或使半導體晶片發 射的輻射散射或者收束。 導線架提供與半導體晶片的電性連接。其一般具有~ 金屬或者導電良好的金屬,如銅。導線架經由如打線導線 之一導線與半導體晶片電性連接。若導線架遭受如侵蝕的 效果,必須面對問題。若導線架中的金屬受侵蝕,連接處 可能與導線分離,例如經由焊接連結的脫落。因此使電性 連接中斷’導致光電元件的功能缺陷或關閉》 【發明内容】 本發明爲解決上述問題,提供一種光電元件,其電極 連接不易造成其中半導體晶片之導線連接中斷。 此問題可藉由如申請專利範圍第1項所述之光電元件 解決。 光電元件之變化設計與較佳樣態如申請專利範圍中 附屬項所述。 典型實施樣態 201143174 不同實施樣態中的光電元件具有一金屬的導線架。導 線架上設有一半導體晶片。半導體晶片被一鑄體包覆。鑄 體與導線架間設有一保護層’其中保護層之氣體滲透性較 鑄體低。 除了保護半導體晶片’鑄體可作爲半導體晶片發射的 輻射之光學元件。其可表現光學功能,例如發散或收束輻 射。因此其特徵爲所發射輻射範圍之穿透性。 保護層提供導線架之侵蝕保護。爲達此功能,其須盡 可能阻止使導線架受侵蝕的分子之傳輸。侵蝕可由如硫化 氫(Ηβ)、氧(〇2)亦或水蒸氣(h2〇)之氣體造成。較佳者,保 護層比鑄體更能阻止分子傳輸,因保護層的氣體滲透性低 於鑄體的氣體滲透性。 氣體滲透性爲一材料性質,表徵例如玻璃或非晶固體 讓氣體通過的特性。此處氣體滲透性尤指氧(〇2)或者氫(H + ) 的滲透性。氣體滲透性於SI單位系統外以barrer爲單位。 barrer表示氣體分子通過此材料的通過速率乘以其厚度除 以材料面積再除以材料兩側的壓力差。其中lbarrer相當於 大約7.5· 10·18 m4s-iN-i。氣體滲透性爲溫度相關的物理量。 本發明中原則上以標準狀態下之氣體滲透性爲考量。其中 標準狀態尤指溫度300 Kelvin(凱氏溫度),即26.85°C。 本發明之基本原則在於’在結構上將鑄體之光學功能 與導線架之侵蝕保護彼此分開。如此可不顧慮輻射作用選 擇保護層的材料’尤使其具有較低氣體滲透性以達較高保 護效果。因此尤可根據其光學性質選擇鑄體。對於鑄體, •4- 201143174 可較佳地選擇具有適當溫度與輻射穩定性的材料。氣體渗 透性可大體上不考慮或者視爲次要。 本發明整體上提供導線架更有效的侵蝕保護,尤其對 於朝半導體晶片之電極側。因此,導線架的電性電極連接 不易造成與所含半導體晶片的導線連接中斷。 數種實施樣態中,保護層於標準狀態下具有的氣體滲 透性比鑄體至少低兩倍。因此,保護層可產生比鑄體更高 的阻延侵蝕效果。 數種實施樣態中,保護層具有一聚合物。其可爲例如 網狀聚合物。因此,可簡單處理保護層材料,以簡單地形 成保護層。 在數種實施例中,保護層具有環氧樹脂。環氧樹脂在 許多應用中可用於侵餓保護。其易於處理,也較佳地呈透 明狀,使如反射器之光學元件可放置其後。於此,可例如 將導線架設置成反射器。 在數種實施樣態中,保護層具有散佈的散射顆粒。例 如可散佈氧化鈦(Ti〇2-)分子或者Ti02粒子於例如環氧樹 脂之一基材中。當基材硬化時,散射顆粒即散佈凝結其中。 藉散佈的散射顆粒,保護層可同時作爲反射提升層,尤可 減少導線架中的輻射吸收。整體上可增加從光學元件輸出 的輻射產量。 在數種實施樣態中’鑄體具有矽膠。此材料特性爲不 僅在可見光範圍穿透性高,且製作光電半導體元件時處理 方便。此外’矽膠在可見光與鄰近範圍具有抗輻射性,可 201143174 避免例如鑄體的混濁。鑄體亦可具有以矽膠爲基底的合成 物質或者類似的混合物。 在數種實施樣態中’鑄體具有散佈的散射顆粒。散射 顆粒可爲分子或粒子。因此尤可造成光電半導體晶片 產生的輻射之散射。 於一實施樣態中’導線架具有一金屬,其標準電位不 超過一伏特。標準.電位表示導線架中金屬的氧化還原電 位。根據標準電極電位’可根據性質將金屬分成非貴金屬 或者貴金屬。作爲參考點(零點)的是25〇C下在氣體壓力1 b a r時的常態氫電極之電性電位。導線架中數種金屬的標準 電極電位爲: • Ni + Ni2+ : -0.23 Volt; • ' Ni^Ni2+ : -0.23 Volt; • S η S η 2 + : -0.14 Volt; • Pb^Pb2+ : -0.13 Volt; • ' Fe —Fe3+ : -0.04 Volt; • · Cu-> Cu2+ : +0.34 Volt; • · C u C u + '· +0.52 Volt; • ' Ag->Ag+ : +0.8 Volt; • ' Pt^Pt2+ :+1.2 Volt; • · A uA u + : + 1 · 5 V ο 11。 因限制了標準電極電位,導線架尤可具有廉價金屬, 同時尤其避免使用貴金屬,亦即對侵蝕穩定的金屬。提供 保護層即無需使用貴金屬。 201143174 在數種實施樣態中,上述金屬可爲在可見波長範圍呈 高反射性的金屬。此謂,此金屬從波長4 0 0 n m起具有的反 射係數高於〇 · 8 0。因此,可增加導線架對散射輻射的反射 貢獻,且提升光電元件的幅射輸出效率。 在數種實施樣態中,金屬可爲銀,其具有較高抗侵蝕 性與極高反射性。 在數種實施樣態中,上述金屬可設於導線架朝向鑄體 的表面,藉以達成散射輻射特佳之反向散射。導線架中其 餘部分可具有例如易導電材料,如銅(Cu)或合金或者混合 物。 在數種實施樣態中,光電半導體晶片可爲發光二極 體。亦可爲其他光電半導體晶片,例如光感應器。 【實施方式】 第1圖爲光電元件100之一第一實施例。此光電元件 具有一導線架i 02,其上設有光電半導體晶片1 〇4。光電半 導體晶片104被鑄體106包覆。其中鑄體106與導線架間 設有一保護層108。 導線架1 02提供光電半導體晶片1 〇4之電性連接。其 一般具有一金屬,較佳者係依其電性與光學性質選擇。設 於導線架1 02上的半導體晶片i 〇4尤可發射輻射於主要側 面方向’亦即向上與向下。通常,導線架丨〇2因此具有例 如銀的高反射性金屬,其中係以例如一銀層舖設之。銀同 時爲良好電性導體。 半導體晶片1 04所發射的輻射因此尤可經鑄體1 06輸 201143174 出。鑄體106作爲將所發射的輻射收束或發散之光學元 件。其中,鑄體1 06須盡可能抗受所發射的輻射。若所發 射的輻射爲在可見光、紫外光或紅外光範圍的輻射,可考 慮例如矽膠或以矽膠爲基底的材料作爲鑄體。 保護層108側向設於半導體晶片104。它因此在結構 上不位於輻射密度最高的區域。因此可依保護層108的性 質尤以防阻侵蝕層的性質作選擇。其中,保護層可更含散 射顆粒,如Ti02分子或粒子。因此,可使保護層1〇8有高 反射性。因此,導線架102在保護層108覆蓋的部分之反 射性高於導線架1 0 2在無保護層1 0 8處的反射性。因此, 保護層1 08尤亦可滿足提升反射性膜層的功能。 第2圖爲光電元件200之一第二實施例。第二實施例 基本上與第1圖中第一實施例具有相同結構。其因此可依 所述第一實施例之樣態與變化實施。第二實施例主要不同 在於設有主體2 02。主體2 02相當於一載體,承載具有自 我保護外罩的光電元件200之其餘部分。主體202可爲單 件或多件。例如,主體202可藉噴覆合成材料於載體或導 線架102形成。其中,主體202的材料可選自半導體製程 中習知的多種適當材料。可考慮例如光電半導體元件操作 溫度的溫度範圍。可選擇例如具有高反射係數的適當材 料。如此,可例如提升光電元件200之輻射功率。主體2〇2 或主體202的部分亦可藉噴鑄程序形成。 主體202於側面包覆導線架102。導線架102設有— 光電半導體晶片,其經連接層204固定於導線架1〇2上。 201143174 連接層2〇4可爲赶劑,例如導電黏劑。在數種實施樣態 連接層2〇4可爲一焊接連結。經由焊接連結,可於光 導體晶片1 04與導線架} 02間形成電性連接。 半導體晶片104被鑄體106覆蓋。鑄體106亦覆 體202的部分。鑄體1〇6與導線架102間設有保護層 保護層於側面包覆半導體晶片1 〇 4。 此外,主體2 02內可設連接電極206»連接電極 經電極連結2 08連接半導體晶片1〇4朝向鑄體106之 (輻射發射面)。因此,可形成經輻射發射面的電性連 電極連結2 0 8可爲例如一打線導線。 第二實施例中,保護層108亦設於連接電極206 的部分,於其上與電極連結208相連。連接電極206 極連結2 0 8間的連接部分可由例如一焊接處(楔型欠 成’其同樣因連結分開受到抗侵蝕保護。因此,連接 因覆蓋保護層108而受保護避免電性連接斷離,藉此 體上排除造成光電元件200功能障礙的可能原因。 第3圖爲第二實施例去除鑄體後的俯視圖。其中 202具有一凹處,可設入光電半導體晶片1〇4。主體有 個固定元件300,以將光電元件200固定於例如一導 (印刷電路板或P C B )。 半導體晶片1 04於側向被保護層1 08包覆,使俯 中位於半導體晶片104下與保護層108下的導線架 見。導線架即如此於輻射輸出面受到抗受侵蝕保護。 俯視圖中,半導體晶片1 04的輻射輸出面可見一 中, 電半 蓋主 108° 206 上側 接。 上面 與電 P )形 處尤 可大 主體 複數 體板 視圖 不可 典型 201143174 的電流散佈結構。第二實施例中,半導體晶片丨〇4經—所 謂焊墊(bondpad)與例如—焊線之電極連結2〇8連接至連接 電極206。其中亦顯示第二連接電極3〇2,藉此可使導體板 電性連接。 結論 爲具象化本發明思維,以上藉數個實施例描述光電元 件。實施例不限於特定技術特徵組合。若數個特徵與樣態 僅於一特殊實施例的關係中或個別實施例中描述,其亦可 分別與其他實施例中其他特徵組合。若爲一般技術知識所 涵蓋’亦可於實施例中去除個或增加別呈顯的特徵或特殊 樣態。 【圖式簡單說明】 以下依據圖式進一步說明光電元件的不同實施例。圖 式中’元件符號的第一個或前幾個數字指示首次使用此元 件符號的圖式。相同符號將用於所有圖式中的相同或等效 元件。說明如下: 第1圖爲光電元件之第一實施例; 第2圖爲光電元件之第二實施例; 第3圖爲第二實施例去除鑄體之俯視圖。 【主要元件符號說明】 1 00 光電元件 102 導線架 1 04 半導體晶片 106 鑄體 -10- 201143174 1 08 200 202 204 206 208 300 3 02 保護層 光電元件 主體 連接層 連接電極 電極連結 固定元件 第二連接電極

Claims (1)

  1. 201143174 七、申請專利範圍: 1 .一種光電元件(100),其包含: -—金屬的導線架(1 0 2 ); -設於該導線架(102)上之一半導體晶片(104); -包覆該半導體晶片(104)之一鑄體(1〇6),以及 -該鑄體(106)與導線架(102)間所設之一保護層(108) ’ 其中該保護層(108)所具有之氣體滲透性較_體(106) 低。 2 ·如申請專利範圍第i項所述之光電元件(1〇〇)’其中該保 護層(1 08)於標準狀態下具有之氣體滲透性至少比該鑄 體(106)低兩倍。 3 .如申請專利範圍第1或2項所述之光電元件(1 00) ’其中 該保護層(108)含有聚合物。 4·如申請專利範圍第3項所述之光電元件(100),其中該保 護層(108)含有環氧樹脂。 5 .如申請專利範圍第1至4項中任一項所述之光電元件 (1〇〇) ’其中該保護層(108)含有散佈的散射顆粒。 6.如申請專利範圍第1至5項中任一項所述之光電元件 (1〇〇),其中該鑄體(106)含有矽膠。 7 ‘如申請專利範圍第1至6項中任一項所述之光電元件 (1〇〇) ’其中該_體(106)含有散佈的散射顆粒。 8 ·如申請專利範圍第1至7項中任一項所述之光電元件 (100),其中該導線架(102)具有標準電位不超過一伏特 之金屬。 -12- 201143174 9 ·如申請專利範圍第1至8項中任一項所述之光電元件 (1〇〇),其中該金屬爲在可見波長範圍呈高反射性之金 屬。 10.如申請專利範圍第8或9項所述之光電元件(100),其中 該金屬爲銀。 1 1 .如申請專利範圍第8至1 0項中任一項所述之光電元件 (1〇〇),其於該導線架(102)朝向該鑄體(106)的表面設有 金屬。 1 2 ·如申請專利範圍第1至1 1項中任一項所述之光電元件 (100),其中該光電半導體晶片(104)爲一發光二極體。 -13-
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CN105765731B (zh) * 2013-11-21 2018-01-16 欧司朗光电半导体有限公司 用于制造光电子半导体器件的方法和光电子半导体器件
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