TW201133747A - Integrated circuit structure - Google Patents

Integrated circuit structure Download PDF

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Publication number
TW201133747A
TW201133747A TW099132755A TW99132755A TW201133747A TW 201133747 A TW201133747 A TW 201133747A TW 099132755 A TW099132755 A TW 099132755A TW 99132755 A TW99132755 A TW 99132755A TW 201133747 A TW201133747 A TW 201133747A
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TW
Taiwan
Prior art keywords
metal
pseudo
semiconductor wafer
bump
integrated circuit
Prior art date
Application number
TW099132755A
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English (en)
Other versions
TWI449139B (zh
Inventor
Tzuan-Horng Liu
Shang-Yun Hou
Shin-Puu Jeng
Wei-Cheng Wu
Hsiu-Ping Wei
Chih-Hua Chen
Chen-Cheng Kuo
Chen-Shien Chen
Ming-Hung Tseng
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Taiwan Semiconductor Mfg
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Publication of TW201133747A publication Critical patent/TW201133747A/zh
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Publication of TWI449139B publication Critical patent/TWI449139B/zh

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

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201133747 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種積體電路，特別有關於一種用 於封裝結構的偽金屬設計。 【先前技術】 現代的積體電路都在半導體晶片上形成，為了增加 製造生產率以及降低製造成本，積體電路通常在半導體 晶圓上製造。每個半導體晶圓含有許多相同的半導體晶 片，於積體電路製造完成之後，從晶圓分割出半導體晶 片’並且在半導體晶片被使用前進行封裝。 在典型的封裝製程中，首先，半導體晶片（也稱為晶 粒）被貼附至封裝基底上，包含將半導體晶片物理性地牢 固在封裝基底上，以及將半導體晶片上的接合墊（b〇nd =d)與封裝赛底上的接合墊連接，接著使用底部填膠，通 :包括環氧樹脂’使得半導體晶片與封裝基底的接合更 牢固。可使用覆晶接合（fHp_chip b〇nding)或打線接合 (wire bonding)的方式’將半導體晶片與封裝基底接合， 所元成的結構稱為封裝組件。 第1圖顯示傳統的晶片之剖面示意圖，纟包含基底 10、電性連線8、銘墊2、銅柱4以及銲錫區6。銲錫區 用於”封裝基底（未繪出）接合’電性連線8則將銅柱4 與位於基底10表面的積體電路電性連接。 在半導體W接合至封裝基底之後，連結半導體晶 片與封裝基底的鮮錫區常常會裂開，#㈣會裂開是因 〇503-A34842TWF/kelly 201133747 為半導體晶片與封裝基底之間的熱膨脹係數不同所產生 的應力所引起’此外，半導體晶片與封裝基底的不同層 之間的熱膨脹係數差異也會產生應力。隨著封裝基底與 半導體晶片的尺寸增加，其所產生的應力也會隨之增 加’應力增加的結果會使得銲錫裂開的問題變得更嚴 重’並且在半導體晶片的不同層之間會發生脫層現象， 特別疋，在半導體晶片的低介電常數介電層之間更容易 發生脫層現象。 【發明内容】 依據一實施例，積體電路結構包含半導體晶片，金 屬墊在半導體晶片的主要表面上，以及凸塊下金屬層在 金屬墊之上與金屬墊接觸，金屬凸塊形成於凸塊下金屬 層之上與凸塊下金屬層電性連接，偽圖案形成在與金屬 墊相同的水平面上，且由與金屬塾相同的^屬材料形成。 其他實施例也揭示如下。 為了讓本發明之上述目的、特徵、及優點能更明顯 易懂，以下配合所附圖式，作詳細說明如下： 【實施方式】 以下詳述各實施例的製造與使用，然而，可以 的是，這些實施例提供許多可應㈣發明概念，其 在各種不同的特定背景中實施，在此所討論的特定 例僅用於說明’並非用以限定揭露的範圍。 依據-實施例’在半導體晶片中存在新的封裝結 0503-A34842TWF/kelly 4 201133747 構，接著’討論實施例的各種變化。在全部的說明實施 例與各種示意圖中，使用相似的標號來標示相似的元件。 第2A圖顯示半導體晶片100的一部份，其也可以是 晶圓的一部份。晶片1〇〇包含基底20,主動電路24形成 於其上。基底20可以是由常用的半導體材料所形成的半 導體基底’例如矽、矽錄或類似的材料。主動電路24可 包含互補式金氧半導體（CMOS)電晶體、電阻器、電容器 (未繪出）’以及/或類似的電路。内連線結構26在主動電 • 路24之上形成，與部分的主動電路24内連接，並連接 主動電路24與上方的金屬層及銲錫凸塊。内連線結構26 包含複數層金屬層，包括在複數層介電層内的金屬線26a 與導孔26b，這些介電層通常稱為金屬層間介電層 (IMD) ’在内連線結構26内的介電層可以是低介電常數 介電層。 金屬墊30在内連線結構26之上形成，且可經由内 連線結構26與主動電路24電性連接。金屬墊30可包含 • 銘’因此在以下描述中也稱為鋁墊30’雖然金屬墊30也 可包含或由其他金屬材料形成，例如銅、銀、金、鎳、 鎢、則述之合金，以及/或前述組合的多層結構。在一實 施例中’金屬墊30由鋁銅合金(AlCu)形成。 介電層34在内連線結構26之上形成，介電層34也 可稱為鈍化層（passivation layer ; passivation-Ι)，可由介 電材料形成’例如氧化石夕（silicon oxide)、氣化碎（silicon )未推雜的梦玻璃（un-doped silicate glass ; USG)， 以及/或前述纟且八 丑合之多層結構。導孔33在介電層34内形 0503-A34842TWF/kelly 201133747 成，電性連接金屬墊30與内連線結構26。在一實施例中， 介電層34位於金屬墊30下方，在其他實施例中，介電 層34可形成在與金屬墊30相同的水平面上。 額外的介電層35(也稱為passivation-2)可在介電層 34之上形成，凸塊下金屬層（under-bump metallurgies; UBMs)38在介電層35上形成’每個凸塊下金屬層38的 一部份延伸至介電層35内。介電層35可由聚亞醯胺 (polyimide)或其他的介電材料形成，例如氧化矽（silic〇n oxide)、氮化石夕（silicon nitride)，以及前述組合之多層結 構。金屬塾30可與凸塊下金屬層38物理性地接觸。 在一貫施例中，凸塊下金屬層38由複合層形成，包 括欽層以及在鈦層上的銅層。在其他實施例中，凸塊下 金屬層38可包含其他金屬層，例如鎳層或金層。凸塊下 金#層38與其底下各自的金屬墊30之結合稱為凸塊塾 結構（bump pad structure)。 金屬凸塊40在凸塊下金屬層38之上形成，金屬凸 塊40可藉由在凸塊下金屬層38之上形成光阻，將光阻 圖案化（未綠出）’以及電鍍金屬材料至圖案化光阻的開口 内而形成。金屬材料可包括銅，因此所形成的金屬凸塊 40也稱為銅凸塊4〇，雖然金屬凸塊4〇也可以使用其他 金屬製成。接著，可選擇性地將額外的其他層，例如鎳 層（未緣出）以及銲錫層46電鍍在每個銅凸塊40之上。然 後’將光阻移除，並使用濕蝕刻移除未被銅凸塊覆蓋 的凸塊下金屬層38。 晶片100中更包括偽圖案（dummy pattern)5〇形成在 0503-A34842TWF/kelly 6 201133747 與金屬塾30相_水平面上，偽圖案％ 並且可由相同的材料形成，例=在 地沈積金屬層=與二屬製塾：的形成包含全*性 興曰沉俊進仃蝕刻製程，蝕刻製葙可LV β社 用與Bcl3(chlorid_為钱刻劑的乾韻刻。偽圖^ 並且可以不與基底20上的任何主動 1及/或任何金屬凸塊4〇電性連接。
在一實施例中，只有偽圖案50形成，在偽圖宰 底下並沒有形成偽金屬圖案與偽圖案50連接。在其他實 施例中’如第2 Α圖糾- 八 貫 含偽重八2 成額外的偽圖案，其可包 金=/: J 孔(d_y ' 。額外偽圖案的形成可改善偽圖案50與介 八佈及Γ的黏著力’並且可改善在晶㈣0内的應 佈’使得區域應力可以重新分佈至晶片ι〇"的 二二ί。在其他實施例中，可以在偽金屬線/墊54底下 二肉夕的偽圖案55及57,並且延伸至更下方的層間介 電層内。 在其他實施例中’如第2B圖所示 ，取代銅凸塊40,形成或固定在凸塊下金屬層％上鬼 同樣地，在第3A » ΖΙΛ ^ 凸塊40,㈣及4A圖中，銅凸塊4〇也可以被薛錫 第2C圖顯示依據一實施例，在第2A以及/或迚圖 中所不之結構的一部份之上視圖。第2A及2B圖所顯示 的剖面示意圖可由第2C圖中的平面剖面線2_2得到，為 了簡化圖式’銅凸塊4〇與凸塊下金屬層38未綠出。在 0503-A34842TWF/kell· 7 201133747 上視圖中，金屬墊3〇具有八邊形的形狀，然而金屬墊3〇 也可以有其他形狀’例如六邊形正方形、圓形以及其 他類似的形狀。偽圖帛50 #分佈λ抵上遍及整個晶片 100 ’在一實施例中，如第2C圖所示，偽圖案50可以是 偽條（dUmmystrip)的形式，由接近晶片1〇〇的一邊ι〇〇—Α 延伸至接近一相對邊100-B，除非金屬墊30在偽圖案5〇 的通道上形成，在此情況下，偽圖案5〇會斷裂成比較小 的片段。因此，一些偽圖案5〇的長度L1可能大於例如 晶片100的個別長度L2的約5〇百分比或更多。在金屬 墊30與偽圖案50之間的間隙S1可能大於約2"爪，或 甚至大於約3/zm，以避免偽圖案5〇與金屬墊3〇發生短 路。然=，可以理解的是，在說明書中所提及的尺寸僅 作為示範用’並且可以改成其他適合的數值。在一示範 性的實施例中，當偽圖案5〇的寬度w介於約5#111至乃 之間時，平行的偽圖案5〇之間的間隙“可約為⑺ 二及2〇_。因此’在晶片1〇"，包含所有的金屬 墊30與偽圖案50的圖案密度可大於約％百分比，並且 可介於約50百分比至8〇百分比之間。 、 第3A及3B圖分別顯示依據另一實施例，半導體晶 ^ 1〇0的剖面示意圖與上視圖’第3A圖顯示第邛圖:曰 不之結構的-部份之剖面示意圖，其中第从圖所示之 面示意圖是由S 3B圖t的平面剖面線3A_3A得到。二 了偽圖案50具有不同的形狀之外，此實施例與第2a_^ 圖所示之實施例相似。參閱第3B圖，在一實施例 圖案50為正方形（或具有接近的長與寬之矩形广其具有 0503-A34842TWF/keIIy „ 201133747 的長度以及/或寬度介於例如約1μιη至約5μιη之間然 而不同的尺寸也可以使用。在金屬墊30與鄰近的偽圖案 50之間的間隙81可大於約2//m，或甚至大於約3以瓜'。 在一示範性的實施例中，鄰近的偽圖案5〇之間的間隙幻 可約為2/zm及3//m。因此，包含金屬墊3〇與偽圖案 50的圖案密度可介於約2〇百分比至5〇百分比之間。 再參閱第3A圖，偽圖案52及54可以在偽圖案％ 底下形成或不形成。再者，因為層間介電層可用於電性 佈線(electrical routing) ’當一些其他偽圖案（例如偽圖案 50’）可能不具有底下的偽圖案52以及/或54時，一些偽 圖案50可具有底下的偽圖案52以及/或54，其取決於是 否有可利用的空間。 第4A及4B圖分別顯示依據另一實施例，半導體晶 片}〇〇的剖面示意圖與上視圖’第4A圖顯示第4B圖二 示之結構的一部份之剖面示意圖，其中第4A圖所示之剖 面示意圖是由第4B圖中的平面剖面線4A_4A得到。參 閱第4B _，偽_ 50可以是偽圖案保護物（dummy pattern shield)的形式，其圍繞晶片1〇〇中一個以上，以 及可能全部的金屬塾3G。在-實施例中，只有—個連續 的偽圖案50在晶片100内形成’換言之，所有的偽圖案 5〇或者大抵上在晶片_内所有的偽圖案5()互相連接， 形成-個連續的偽圖案。因此，偽圖案5G的面積可大於 晶片100面積的約80百分比。另一方面，金屬墊3〇可 藉由偽圖案50互相分開。在其他實施例中，在晶片1〇〇 内的偽圖案50只包含限定數量（例如小於約1〇)的偽圖案 0503-A34842 丁 WF/kelly Λ 201133747 保護物，這些偽圖案保護物互相分開。 偽圖案50延伸至遍及大抵上整個的晶片刚，偽圖㈣ 中接近晶片100的一邊100_Α的部份5〇—丨可以與偽；案 〇中接近晶>} 100的一相對邊100_Β的部份5〇性 連接。再者，偽圖案50中接近晶片100的一角1〇〇 部份50—3可以與偽圖案5〇中接近晶# ι〇〇的一相 的部份50-4電性連接。此外，在金屬塾3〇鱼鄰 近的。卩分偽圖案50之間的間隙S1可能大於約2以爪，或 =大於約3/zm。在整個晶片1〇〇中，包含金屬墊％ ”偽圖案50的圖案密度可大於約9〇百分比。同樣地， =以在偽圖案（偽圖案保護物例底下形成複數個偽 52 與 54 〇 藉由在與金屬墊30相同的水平面上形成偽圖案，可 以=善晶片/晶圓的可事度，這是因為偽圖案5〇造成應力 重分佈（Stress-redistHbUti〇n)的結果。可進行許多實驗來 評估偽圖案對於個別晶片可靠度的影響，在第_群組與 第二群組的樣品晶圓中，分別依據第2A圖與第4a圖^斤 不之結構製成偽圖案，其中只形成偽圖案5〇，但是沒有 形成偽圖案52與54。可以觀察得到，第一群組與第二群 組的樣品晶圓的失效率都約為2〇百分比。然而，當沒有 形成偽圖案50時，在相同的測試條件下，晶片的失效率 增加至約83百分比，此結果顯示偽圖案5〇對於改 ij . ^ 曰 Θ 片的可靠度具有顯著的效果。 另外’第三群組的樣品晶片是依據第4A圖所示之結 構製成’其具有偽圖案5〇、52及54，可以觀察得到，第 〇503-A34842TWF/kelly ]〇 201133747 三群組的樣品晶片之失效率更降低至〇百分比。 雖然本發明已揭露較佳實施例如上，然其並非用以 限定本發明，在此技術領域中具有通常知識者當可瞭 解，在不脫離本發明之精神和範圍内，當可做些許更動 與潤飾。因此，本發明之保護範圍當視後附之申請專利 範圍所界定為準。
0503-A34842TWF/kelly 11 201133747 【圖式簡單說明】 圖.第1圖係顯示傳殊半導體晶片的一部份之剖面示意 _， 第2A及2B圖係_示依據一實施例，半導體晶片的 剖面示意圖； 第2C圖係顯示^2A以及/或2B圖中所#結構 的上視圖； 第3A至4B圖係顯示依據其他實施例，半導雜a曰片 的剖面示意圖與上視圖。 【主要元件符號說明】 2〜紹塾； 4〜銅柱； 6 ^鲜錫區， 8〜電性連線； 10、20〜基底； 24〜主動電路 2 6〜内連線結構； 26a〜金屬線； 26b、33〜導孔； 34〜介電層； 30〜金屬墊； 35〜額外的介電層（鈍化層） • 9 38〜凸塊下金屬層； 40〜金屬凸塊 40’〜銲錫凸塊； 50、50’〜偽圖案； 46〜銲錫層； 52、54、55、57〜底下的偽圖案； 100〜晶片。 0503-A34842TWF/kelly 12

Claims (1)

  1. 201133747 七、申請專利範圍： 一種積體電路結構，包括： 一半導體晶片； 一金屬墊，設置於該半導體晶片的一主要表面上； 一凸塊下金屬層，設置於該金屬墊之上，與該金 墊接觸； ' ° ' 一金屬凸塊，設置於該凸塊下金屬層之上，與該凸 塊下金屬層電性連接；以及 、〆 一偽圖案，設置在與該金屬墊相同的水平面上，且 由與該金屬墊相同的金屬材料製成。 2.如申請專利範圍第！項所述之積體電路結構，其中 在該半導體晶片内無金屬凸塊在該偽圖案之上形成，且 無金屬凸塊與該偽圖案電性連接，其中該偽圖案 ^金屬凸塊以及該半導體晶片内的主動積體電路電性隔 3·如申請專利範圍第丨項所述之積體電路結構， 該金屬凸塊為銅凸塊或銲錫凸塊。 八 4 圖如中請專利範圍第1項所述之積體電路結構， 至:近屬條，由接近該半導體晶片的-邊延伸 該偽5:案申二圍的第述之積體電路_ 個金屬塾。，料金屬保護物，完全地圍繞複數 6.如申請專利範圍第5項所述 該連續的偽仝属仅m檟體電路結構，其申 偽金屬保護物由該半導體晶片的-邊連續地延 〇5〇3-A34842TWF/kelly ^ 201133747 伸至一相對邊。 伸至一相對角。 千導體曰曰片的-角連續地延 括：8·如申請專利範圍第〗項所述之積體電路結構，更包 ’與該偽圖 案物理性⑶置於該偽圖案底下 顿=金屬特徵，設置於該偽重分佈導孔底下，其中 4金屬雜與該偽重分佈導孔及該偽圖案電性連接。 9.一種積體電路結構，包括： 一半導體晶片； 一鈍化層，設置於該半導體晶片的一主要表面上； 複數個金屬墊，設置於該鈍化層下方； 複數個凸塊下金屬層，每個凸塊下金屬層包括一第 一部份設置於該鈍化層之上，以及―第二部分延伸至該 鈍化層’與每一個金屬塾接觸； 複數個金屬凸塊，每個金屬凸塊設置於該些凸塊下 金屬層之上，與該些凸塊下金屬層中的一個接觸；以及 複數個偽圖案，分佈在整個該半導體晶片中，其中 該些偽圖案為設置在相同水平面上的平行偽金屬條，且 由與該些金屬墊相同的材料製成。 10.如申請專利範圍第9項所述之積體電路結構，其 中在相同的水平面上，且由與該偽金屬保護物相同的材 料形成的全部金屬特徵之圖案密度大於9〇百分比。 〇503-A34842TWF/kelly
TW099132755A 2010-03-30 2010-09-28 積體電路結構 TWI449139B (zh)

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