TW201041041A - Semiconductor structure and method for making the same - Google Patents

Semiconductor structure and method for making the same Download PDF

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TW201041041A
TW201041041A TW098120620A TW98120620A TW201041041A TW 201041041 A TW201041041 A TW 201041041A TW 098120620 A TW098120620 A TW 098120620A TW 98120620 A TW98120620 A TW 98120620A TW 201041041 A TW201041041 A TW 201041041A
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semiconductor structure
metal
layer
conductive pattern
dielectric layer
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TW098120620A
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TWI471938B (zh
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Yi-Jen Lo
Yu-Shan Chiu
Kuo-Hui Su
Chiang-Hung Lin
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Nanya Technology Corp
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    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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Description

201041041 六、發明說明： 【發明所屬之技術領域】 元線結構，以及相關於這種 本發明係有關於半導體技術，牿則β ,哥別疋有關於一種半導體結構，例 如一種垂直通道電晶體的金屬閘極或字 半導體結構的製程方法。 Ο
G 【先前技術】 制薄膜的特性 控財針對麟的均—性及製程 :導體a:上、赫要:目則業界已發展出許多製程技術，其能夠在 ㈣时ΓΛ崎的方式沈積崎料_，並且能財效的控 表面上沈積侧_ =^=2_在歡料趙結構的 ::為繁雜的步驟。選擇性化學氣相沈積優：=:: 、、:而目别的選擇性沈積方法仍有缺點。舉例來說，選擇性沈積 201041041 方法常被絲在接_巾成長齡在進行齡屬的成長或 沈積步驟之則’必須先對接觸洞進行一連串的清洗步驟，以確保石夕 表面的潔淨^若有反應離子钱刻收如細^扯㈣^^所造 成的RIE傷害層存在於接觸洞的底部，就無法在接觸洞中成長鎮金 屬層’因為RIE傷害層會在選擇性沈積過程中扮演類似絕緣層的角 色。因此’ RIE傷害層必須在金屬膜成長前被完全清除。 〇 此外目_選擇性沈積方法似乎健無法在舞基的金屬底層 上形成厚度超薄(小於I5奈米）、具高度膜料一性，同時又能夠在 結構上連續的選擇性沈積薄膜，例‘，鎢金屬薄膜。再者，要能夠 在介電層與金屬底層之間維持足夠高的選擇性，而又要同時沈積出 均厚且超_金屬_，以目前工藝水準而言仍是屬於十分困難的 枯淑。 由此可知，目前業界仍需要-觀良之半導聽構及製造方法， 以配合在㈣顧中需要均厚且超薄的_，且 底層，介電層與該金屬底層之 ，前述形成均厚且超薄的薄膜的方法 還需有經濟、快迷等特性，並具有高產出能力。 【發明内容】 本發明之主要目的在提供—種改良的半導體結構，例如一種垂直 201041041 通道電晶體的金屬祕或字元線結構，以及棚於這種半導體結構 的製程方法’轉決先前技藝關題與缺點。 本毛月提供半導體結構，包括一基材；一介電層，設於該基材 上；-導糊案’設於該介f層上，且該導電_包括—上表面及 侧壁；以及-金屬_ ’僅選擇性的沈積在該導電_的上表面及 侧壁上，而不沈積在該介電層上。 〇 根據本發明另-較佳實施例，提供—種製作半賴結構的方法， 包含有：提供—基材；_紐上形成_介㈣；於齡電層的- 主表面上形成-導電圖案，該導電圖案具有一上表面以及側壁；以 及進行-選擇性原子層沈積製程，選擇性的在該導電圖案的該上表 面及該側壁上沈積-均厚金屬層，但使該介電層的該主表面實質上 無該金屬薄膜形成。 Ο 【實施方式】 第1圖為依據本發明-較佳實施例所繪示的積體電路中的半導 體結構剖面示意圖。如第！圖所示，半導體結構工包含一半導體基 材10 ’例如，石夕基材，-介電層12，設於該半導體基材1〇上，一 導電圖案14，形成在介電層12的主表面12a上，以及一超薄的金 屬薄膜16 ’選擇性的沈積在導電圖案14的上表面⑷及側壁⑽ 上。其中’金屬薄膜16實質上不會直接長在介電層12的主表面以 201041041 上。 根據本發明’半導體結構1可以是一金屬閘極電晶體元件，而介 電層12做為該金屬閘極電晶體元件的閘極介電層或閘極氧化層。本 發明特別適合應用在金屬閘極、垂直通道電晶體元件，這樣的元件 可以被應用在先進的動態隨機存取記憶體(DRAM)技術中，其中， 金屬溥膜16可以用來降低字元線的阻值。此外，在前述技術中，為 0顧及金屬閘極電晶體元件的功函數，通常要求金屬薄膜16具有超薄 厚度(小於15奈米左右），同時需為結構上連續且厚度均一的高品質 材料層。 依據本發明之難實_，介_ 12可吨含有氧化梦、氮化 石夕或氮氧化料。導電_ 14可以包含有欽、氮她、组、氣化如、 紹、銅、金、鶴、雜金屬或上述任意組合或合金。較佳者，導電 G 是由氮化鈦所構成，而域細16是以原子沈積法所形成 的厚度小於丨5奈米的鶴金屬層。此外，較佳者，可以是屬於 =者，-部份的導電圖案14，其厚度_小於Μ奈米, 例如’ 於6到8奈米之間。 第2圖為依據本發明較佳實施例所繪 結構1的方法20流程圖。如第2圖所^第1圖中的+導體 一半導體基材，如第丨财爾示的半導體t驟21 b首先提供 導體基材表面上以熱氧化或熱成長法形成介電層，如第^ 201041041 圖中所繪示的介電層12，其中’該介電層可以包含有氧化矽、氮化 矽或氮氧化石夕等。 在步驟23中’在介電層的主表面上形成金屬囷案，例如第1圖 中所繪示的導電圖案14，其中該金屬圖案可以包含有鈦、氮化鈦、 鈕、氮化鈕、鋁、銅、金、鎢、矽化金屬或上述任意組合或合金。 較佳者，該金屬圖案是由氮化鈦所構成，且該金屬圖案是以濕式蝕 0 刻法所形成者。例如，在例如氮化鈦之金屬層上形成一遮蓋層，例 如多晶矽層，此遮蓋層僅僅蓋住金屬層的上表面，但暴露出金屬層 的側壁’隨後再以濕式触刻法_掉金屬層的側壁，如此形成該金 屬圖案。最後，移除該遮蓋層，暴露出金屬圖案的上表面。 在形成金屬圖案之後，接著進扦遠擇性鎢原子層沈積製程 @leetivetungStenatomielayei·一sitiGnp_ss) ’ 轉性的在前述 金屬圖案上長出超薄且均厚的鶴金屬薄膜，例如第丨圖中所緣示的 金屬触16。根縣發明，祕超薄且均厚⑽ ㈣絲，且具有Μ清觀細ep_喊性旱^ 擇性鶴原子層沈積製程可包括進行複數次原子層沈積循的選 γ，m金屬圖案上所要的鹤金屬薄膜的沈積厚度。為簡化 ^ ®中僅顯不單一次的原子詹沈麵環(步驟24至27)。 含氫=質本ΓΓ較佳實關’纽的原子概_環包括：⑴將 例如石夕甲燒或氣氣，導入反應室中，並維持一預定時間， 7 201041041 使得氫自由基能夠吸附在介電層的主表面上以及金屬圖案的表面上 (步驟24):(2)將反應室抽真空，同時暫停所有氣體供應，選擇性 的將先則吸附在介電層的主表面上的氫自由基去除(步驟25);⑶將 鎢前趨物，例如六氟化鶴(WF6)導入反應室中，並維持在低壓下(低 於5torr)，以及低溫下(低於3⑻。c)，使鎢前趨物與吸附在金屬圖案 表面上的氫自由基反應，如此選擇性的在金屬圖案表面上沈積出鶴 .$屬薄膜(步驟26);以及(4)以惰性氣體，例如，氬氣，進行反應 〇室的吹除’以移除反應副產物(步驟27)。如前所述，為了達到所要 的厚度，上述原子層沈積循環可以重複進行(步驟28)。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所 做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 圖式簡單說明】 〇
圖為依據本發明-紐實施例所繪示的積體電路巾的半導體結 構剖面示意圖。 P 細輪爾州―趙結 【主要元件符號說明】 1半導體結構 201041041 10半導體基材 12介電層 12a主表面 14導電圖案 14a上表面 14b側壁 16金屬薄膜 20方法 21提供基材 22形成介電層 23形成金屬圖案 24導入矽曱烷(或氫氣) 25抽真空 26導入鎢前趨物 27惰性氣體吹除 28重複步驟24-27

Claims (1)

  1. 201041041 七、申請專利範圍： 1. 一種半導體結構，包含有： 一基材； 一介電層’設於該基材上； -導電_，設於該介㈣的—主表面上，且該導電圖案包括一 上表面及側壁；以及 金膜，包覆住該導電圖案，包括該上表面及該侧壁，但該 介電層的該主表面實質上無該金屬薄膜形成。 2. 如申請專利範圍第！項所述之半導體結構，其中該介電層包含氧 化矽、氮化矽或氮氧化矽。 3. 如申請專利範圍第丨項所述之半導體結構，其中該導電圖案包含 鈦、氮化鈦、纽、統姐、銘、銅、金、鶴、魏金屬或上述組合 Q 或合金。 4. 如申請專利範圍帛！項所述之半導體結構，其中該金屬薄膜包含 5.如申請專利範圍第！項所述之半導體結構，其中該導電圖案 化鈦所構成。 6.如申請專利範_5項所述之半導體結構，其中該金屬薄膜是一 201041041 鶴金屬層。 7. 如申請專利範圍第6項所述之半導體結構，其中該鎢金屬層的厚 度小於15奈米。 8. 如申請專利範圍第1項所述之半導體結構，其中該介電層係為一 垂直通道電晶體的閘極介電層。 ° 9.如申請專利範圍第8項所述之半導體結構，其中該導電圖案為一 金屬閘極或一字元線的一部份。 10. 如申請專利範圍第9項所述之半導體結構，其中該導電圖案的厚 度小於15奈米。 11. 如申請專利範圍第9項所述之半導體結構，其中該導電圖案的厚 q 度介於6到8奈米。 12. —種製作半導體結構的方法，包含有： 提供一基材； 於該基材上形成一介電層； 於該介電層的一主表面上形成一導電圖案，該導電圖案具有一上 表面以及側壁；以及 進行一選擇性原子層沈積製程，選擇性的在該導電圖案的該上表 11 201041041 面及該側壁上沈積-均厚金屬層，但使該介電層的該主表面實質上 無該金屬溥膜形成。 13. 如申請專利範圍第12項所述之製作半導體結構的方法，其中該 擇性原子層沈積製程包含以下步驟： ⑴將含氫物質導人反應室中，並維持—預定時間，使得氣自由 .基麟吸附在介f層駐表面上以及導電職的表面上； 〇 (2)將反應室抽真空，_暫停所錢體供應，選擇性的將先前 吸附在介電層的主表面上的氫自由基去除； ⑶將鶴前騎導人反齡巾，鱗縣讎及低溫下，使鶴前 趨物與吸附在導電圖案表面上的氫自由基反應，如此選擇性的在導 電圖案表面上沈積出鎢金屬薄臈；以及 (4)進行反應室的吹除，以移除反應副產物。 14. 如中請專利範圍第13項所述之製作半導體結構的方法，其中該 ^ 含氫物質包含矽曱烷或氫氣。 人 15. 如申請專利範圍第13項所述之製作半導體結構的方法，其中該 鎢前趨物包含六氟化鎢(V/F6)。 16. 如申請專繼_ i3項所述之製作半導義構的方法， 低壓係指壓力低於5torr。 ' 12 201041041 17.如申請專利範圍第13項所述之製作半導體結 低溫係指低於3〇〇。〇。 構的方法 其中該 18. 如申請專利範圍第12項所述之製作半導體結構的 介電層包含氧化矽、氮化矽或氮氧化矽。 / 19. 如申請專利麵第12項所述之製作半導體結構的方法 導電圖案包含鈦、氮化鈦、组、氮化組、銘、銅、金 屬或上述組合或合金。 鶴 其中該 其中該 $夕化金 2〇.如申請專利範圍第12項所述之製作半導體結構 均厚金屬薄臈包含鎢。 的方法， 其中該 其中該 21·如申請翻範圍第12項所述之製作半導體結構的方法 均厚金屬薄膜的厚度小於15奈米。 4 其中該 22.如申請專利翻第12項所述之製作轉體結構的方法 導電圖案的厚度小於15奈米。 、 八、圓式： 13
TW98120620A 2009-05-04 2009-06-19 製作半導體結構的方法 TWI471938B (zh)

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