201027715 六、發明說明： 【發明所屬之技術領域】 本發明係在用於記憶體之記憶體元件（記憶體單元）的領 域中。 【先前技術】 記憶體為積體電路之主要類別。其主要係用作固態獨立 及嵌入式記憶體。最廣泛使用之記憶體技術為DRAM、 SRAM、浮動閘極（Flash)及MRAM。此等現有技術均不能 以高面積密度加以整合且不能同時提供非揮發性及快速操 作。尤其為，Flash對於許多嵌入式應用而言太慢，SRAM 及DRAM在自電源斷開時釋放其記憶體狀態，且SRAM及 MRAM僅可以有限面積密度加以製造。在NROM、 MirrorBit及SONOS快閃記憶體中達到最高密度，其包含電 荷收集層以儲存兩個實體分離電荷封包。Flash之高程式化 電壓使與CMOS電路之整合變複雜。 因此，需要提供一種克服先前技術之記憶體單元之缺陷 的記憶體元件。尤其為，需要提供一種非揮發性且此外使 高面積密度及/或快速操作成為可能之記憶體元件。 【發明内容】 根據本發明之第一態樣的記憶體元件包含源極-汲極-閘 極功能結構，亦即，在中間建立有通道區域之源極電極及 汲極電極，其中依賴於將電信號施加至閘極，電荷載子可 在源極電極與汲極電極之間流動。 較佳地，通道區域可包含半導體或絕緣材料（因此包含 143837.doc 201027715 至多同等少數自由雷％番 . d了載子）或經摻雜為導電；可 不同方式來組態通道區域. 乂許多 的電阻以允許閑極（_方面^地’通道區域提供足夠大 )/、源極電極或波極電極（另— , 面）之間的獨立電壓信號。 万 閘極包含多鐵性材料（因&立θ 士 热夕奸圾、々 以因此為具有至少兩個耦合有序參 數之材料）。多鐵性材料通當 汁常係以一排列位於閘極電極（一 方面）與源極電極及汲極電 铋拟士迕^ ( 方面）之間β記憶體元件 ❹= 成為位元記憶體元件。此係藉由導致多鐵性材料包 響含兩個穩定晶傳而達成， .„ ^ ^ 八肀第—日日疇之切換狀態係藉由 在閘極電極與源極電極之間 以設定，且笛-日磕 冩入」電壓ί吕唬加 ㈣ 第—曰曰傳之切換狀態係藉由在閘極電極與汲極 電極之間施加第二「寫入」電壓信號加 =情，如)藉由其之間的裂縫或嘴壁釘紫結構而實= 刀離或者或此外，在本發明之一於杜奋 較佳實施例巾，其可藉 吏冑入」信號控制始終同時施加第一寫入脈衝及第 ❹ ‘”、人脈衝而發生（即使兩個位元中之僅—者待覆寫）。 因為兩個晶嘴使兩個位元能夠儲存於單一記憶體元件 ，所以與先前技術之記憶體元件相比較，面積密度增 加々雖然與僅具有一個晶田壽之類似記憶體元件相比較，接 、等U占用纟置上之大部分區域）相同，但記憶體密度 被增加2倍，因為藉由根據本發明所提議之簡單量測的記 憶體7L件包含兩個資訊位元。 鐵電性材料擁有穩定且可藉由經施加電場而遲滞地切換 之自發極化。鐵磁性材料擁有穩定且可藉由經施加磁場而 143837.doc 201027715 切換之自發磁化。多鐵性材料擁有同時鐵電性有序化及磁 有序化。此等兩個有序參數經耦合。存在鐵磁性、次鐵磁 性及反鐵磁性多鐵性體（multiferroics)。 因此’多鐵性材料晶疇可藉由跨越其施加第一電壓信號 及第二電壓信號（例如，藉由施加電場脈衝）加以程式化。 歸因於鐵磁性、次鐵磁性或反鐵磁性有序參數至鐵電性有 序參數之耦合，此亦導致程式化此鐵磁性、次鐵磁性或反 鐵磁性有序參數。 對於「讀取」操作，可使用自旋閥效應（spin effect)。自方疋閥效應導致可切換源極電極與没極電極之間 的電阻（對於在至少一方向上在源極電極與汲極電極之間 流動之電流）。為此目的，汲極電極及源極電極兩者均較 佳地係鐵磁性的或至少包含鐵磁性元件。又，多鐵性材料 旎夠影響流至源極電極或汲極電極之電荷載子之磁矩的相 對定向及源極電極或汲極電極之磁化的相對定向。此可以 兩種可能方式中之一者進行： -作為第一替代例，多鐵性材料可導致產生狀態依賴性磁 場，磁場影響流入導電通道之電荷載子之磁矩。因此， 鐵磁性/次鐵磁性/反鐵磁性有序參數之切換導致通道區 域中磁場之切換。此可藉由以下各項進行： 〇間極鐵磁體（或潛在地為閘極次鐵磁體；在本文中， 定義「閘極鐵磁體」、「鐵磁體」、「鐵磁性層」或「鐵 磁性材料」包括相符次鐵磁性材料，熟習此項技術者 知曉鐵磁體之功能亦可藉由次鐵磁體實現）耦合至多 143837.doc 201027715 鐵性材料；接著’閘極鐵磁體與多鐵性材料進行直接 接觸（在中間無任何物的情況下進行直接接觸）， 〇接著，鐵磁性（或次鐵磁性）多鐵性材料自身產生足夠 大的雜散場。 作為第—替代例，第一晶疇及第二晶疇之鐵磁性/次鐵 磁性/反鐵磁性有序參數之切換可分別導致源極電極及 汲極電極之磁化方向之切換，使得自旋閥改變電荷載子 磁矩之較佳定向。為此目的，源極電極直接交換耦合至 多鐵性材料之第—㈣，且沒極電極交換輕合至第二晶 疇此係與用於導致流至源極電極及汲極電極之電荷載 子之磁矩具有預定義較佳$向的構件（例>，固定磁化 (釘紮）閘極鐵磁體，其雜散場在電荷載子流人通道區域 時疋向電荷載子之磁矩）組合。 在任一狀況下，用於第-位元及第二位元之「讀取」過 程分別依靠導致電荷載子流至源極電極及汲極電極之電产 » 之產生。較佳地，此係藉由在源極電極與淚極電極之間施 加「讀取」脈衝而達成。在大多數一般狀況下，上述自旋 闕效應導致電壓-電流特性係極性依賴性的。依賴 取」脈衝之極性，讀取第一位元或第二位元。此亦暗示記 憶體兀件不為完全隨機存取類型，因為可能不同時讀 一位兀及第二位元。然而，可能同時讀取記憶體中不同記 憶體元件之位元。 τ个U。己 記憶體元件係以具有非揮發性之優點為特徵，因為多鎩 性材料之鐵電性有序參數及磁性有序參數係非揮發性的鐵 143837.doc 201027715 歸因於其非揮發性特性，可期望低功率消耗。 又’改變多鐵性元件之鐵電性極化為固有快速過程（5〇 ps-l nS)°因此’根據本發明之記憶體元件與快閃記憶體^ μ8)相比較具有顯著程式化速度優點。 另外’記憶體元件可實施於簡單的小型單位單元（僅具 有6F2之所需空間，在無任何額外電阻器或電容器之ι_電 晶體結構中）中且因此與先前技術之記憶體元件相比㈣ 於以更高面積密度之整合。又，其在用於較小單元時良好 地按比例調整，因為其不包含任何電容器。 記憶體元件之又一優點（尤其與MRAM相比較）為降低之 寫入能量（約10七焦耳/位元，相對於MRAM之1〇…焦耳/位 元）。 …、 記憶體元件之再一優點（尤其與❿化相比較）為較低程式 化電壓（大約1 V，相對於Flasl^15 ν)。 可能鐵磁性多鐵性體包括方蝴石（Ni3B7013I)、詞欽礦⑽ 如，BiMn〇3ATbMn〇3)及硫酸鹽（諸如，cdCr糾。然而， 在此等當前已知材料中，耦合有序參數僅在低溫下係非 零，使得記憶體元件及以其製得之裝置主要適於經冷卻裝 置係可接受之特殊應用。 在一較佳實施射’元件包含冷卻I置。較佳地，藉由 該冷卻裝置所提供的記憶體元件之操作溫度低於_克耳 文（Kelvin) 〇 然而，根據一尤其較佳實施％，多鐵性材料為耗合卜 般藉由交換偏壓耦合）至閘極鐵磁體或汲極電極及源極電 143837.doc 201027715 極且釘紮閘極鐵磁體或汲極電極及源極電極之多鐵性反鐵 磁體。此「鐵磁體釘紮」實施例首先係以已知反鐵磁性多 鐵性體比其鐵磁性對應物更加溫度穩定之優點為特徵。 ，又，存在超順磁極限（亦即，單元中磁性層之磁各向異性 變得與kT相當時之大小，其中k為波耳兹曼（B〇hzmann)常 數且T為絕對溫度，使得磁化在彼極限以下變得不穩定）不 為反鐵磁體中之問題的特殊優點，使得單元可經設計為同 等較小且仍穩定。 ❹ 可用反鐵磁性多鐵性材料之實例為BiFe03。 根據本發明之記憶體元件可用作純記憶體裝置之記憶體 單元及/亦包括可程式化邏輯之邏輯電路中之記憶體單元兩 者。可在歐洲專利申請案EP 08104301 0中發現可併入有根 據本發明之記憶體裝置之該等邏輯電路的實例。因此，歸 因於根據本發明之方法’可在無額外遮蔽步驟的情況下整 合記憶體及邏輯電路，其向該等積體電路提供顯著製造成 ❿本優點。 【實施方式】 在下文中’將參看隨附圖式來描述本發明之實施例。圖 辆係示意性的且未按比例。在圖式中，相同參考數字指 代相同或相應元件。 在諸圖所描繪之元件之鐵磁性材料中，實心箭頭通常指 示固定磁化。固定磁化可為以某一方式加以釘紫之磁化， 其具有高於在正常操作期間作用於其上之有效場之總和的 續頭場’或其經以其他方式影響以不在程式化元件之正常 143837.doc 201027715 操作期間改變磁化方向。空心箭頭指示可藉由程式化電壓 脈衝^號而切換之磁化。在釘紮磁化的狀況下，諸圖中未 展不釘紮層。鐵磁性層之釘紮為熟習磁性記憶體領域者 (例如）自MRAM記憶體所熟知。此處不再進一步論述釘 紮。 圖1所描繪之記憶體元件丨在基板3上包含源極電極12及 ;及極電極13，源極電極12及汲極電極13兩者均為鐵磁性導 電材料，例如，為鈷合金或高導磁合金（FeNic〇合金）。在 源極電極與汲極電極之間（例如）藉由基板中之η型摻雜區域 或以任何其他適當方式而形成導電通道21;但導電通道可 能無需包含與基板3相同之材料。 基板可為任何已知或其他適當基板，諸如，半導電基 板，例如，砷化鎵或矽。所描繪實施例中之基板係由參考 電壓接點（即，地面接點8(或「主體」（bulk)接點）)接觸。 如此項技術中已知，在（例如）源極電極12與地面接點8之間 可存在（未描繪）連接，使得源極電極12始終處於地面電位 (或視情況處於其他參考電位），或作為一替代例，在閘極 電極與地面接點之間可存在連接，如下文進一步所描述。 記憶體元件1進-步包含閘極，閘極包括閘極電極17、 鐵磁性層14(為任何鐵磁性導電材料）及爽於間極電極與鐵 磁性層之間的反鐵磁性多鐵性層15。鐵磁性層係藉由介電 層16而與源極電極12及汲極電極13以及導電通道21絕緣。 多鐵性層！5交換耦合至鐵磁性層。因此，多鐵性層之有 序參數之切換亦導致緊鄰區域中鐵磁性層之有序參數之切 143837.doc •10· 201027715 換（因此導致磁化之切換）。 由多鐵性層15及鐵職層顺叙M合雙層現在係使得 其可包含兩個穩定晶_ : 14.卜15」；14 2、15 2。該圖中 • 之虛線18描繪第一晶疇14.1、15.1與第二晶疇14·2、15 2之 間的電位分離線》 可藉由固定位置處之經有目㈣加結#來分離晶嘴。該 結構起局部地分裂雙層之作用或充當嘴壁釘紫構件。該結 構可(例如)為虛線之位置處之微縫隙，或雜質或類似釘紮 搴 疇壁。 作為經有目的添加結構之替代<列’雙層亦可缺乏用以分 離晶缚之任何經有目的添加結構。則晶嘴可位於非預定義 位置中且可僅分別藉由在汲極電極及源極電極附近導致不 同有序參數方向而發生。 在任何狀況下’雙層必須為各向異性且足夠大的大小以 在已切斷場之後維持兩個晶嘴，亦即，在任何狀況下，兩 籲㈤晶4必須係穩定的’使得記憶體元件係非揮發性的。已 在降至（例如）2〇 nm或甚至更小之極小大小之結構中預測 及觀測到兩個磁性穩定晶_之共存。使晶嘴穩定的雙層之 大小之下限依賴於各向異性，各向異性又依賴於雙層之材 料組合物。 可分別在閘極電極17與源極電極12之間或在閘極電極P 與汲極電極13之間施加用於兩個晶疇之「寫入」電壓信 號。為此目的，使多鐵性層15及介電層16之厚度及導電性 較佳地彼此適應’使得跨越多鐵性層之電壓降對應於閑極 143837.doc 201027715 電極與源極電極或汲極電極之間的電壓之大部分（較佳地 為至少一半）。 ❹ 藉由寫入電壓信號’可在四種狀態（每一晶疇兩種狀態） 之間切換多鐵性材料之自發極化，如參看圖3a至圖6c更詳 細地所解釋。因為材料係多鐵性的，所以自發極化之切換 亦（例如）藉由顛倒多鐵性材料中「向上」及「向下」磁化 層之順序而切換相符反鐵磁性有序參數。鐵磁性層1緊 夕鐵生層1 5)父換耗合至多鐵性層。由此，多鐵性材 料之4 15’ 1 ' 1 5.2中鐵電性自發極化之切換具有亦切換 鐵磁性層晶疇14.卜14·2之磁化方向之效應。 、 圖2之屺憶體TG件！設計不同於圖〗之設計之處在於：多 鐵性層之順序與鐵磁性層14之順序顛倒。多鐵性層⑽ 於鐵磁！·生層14(-侧）與導電通道21以及源極電極及沒極電 :(另-侧)之間。則不再需要介電層16，因為與大部分通 节使用之鐵磁性材料對比，多鐵性材料15係電絕緣的。201027715 VI. Description of the Invention: [Technical Field of the Invention] The present invention is in the field of a memory element (memory unit) for a memory. [Prior Art] Memory is a main category of integrated circuits. It is mainly used as solid state independent and embedded memory. The most widely used memory technologies are DRAM, SRAM, floating gate (Flash) and MRAM. None of these prior art techniques can be integrated at high areal densities and cannot provide both non-volatile and fast operation. In particular, Flash is too slow for many embedded applications. SRAM and DRAM release their memory state when disconnected from the power supply, and SRAM and MRAM can only be fabricated with limited area density. The highest density is achieved in NROM, MirrorBit, and SONOS flash memory, which includes a charge collection layer to store two physically separated charge packets. The high programming voltage of Flash complicates the integration with CMOS circuits. Accordingly, it is desirable to provide a memory component that overcomes the deficiencies of prior art memory cells. In particular, it is desirable to provide a memory component that is non-volatile and that further enables high area density and/or fast operation. SUMMARY OF THE INVENTION A memory device according to a first aspect of the present invention includes a source-drain-gate functional structure, that is, a source electrode and a drain electrode are formed in the middle of the channel region, wherein An electrical signal is applied to the gate, and charge carriers can flow between the source electrode and the drain electrode. Preferably, the channel region may comprise a semiconductor or insulating material (thus containing 143837.doc 201027715 at most equal to a few free radicals. d is a carrier) or doped to be electrically conductive; the channel region can be configured in different ways. The resistor is a separate voltage signal between the source electrode or the wave electrode (other, surface) that allows the idler (the 'channel area is sufficiently large). The thyristor contains a multi-ferric material (due to & the θ 士 士 士 士 士 士 士 士 士 士 士 士 士 士 士 士 士 士 士 士 士 士 士 士 士 士 士 士The multi-ferric material is usually arranged in an arrangement between the gate electrode (on the one hand) and the source electrode and the gate electrode. The β memory element 成为 = becomes a bit memory element . This is achieved by causing the multiferroic material to contain two stable crystals, and the switching state of the 肀 ^ 肀 - day domain is set by the gate electrode and the source electrode. And the flute-day intrusion voltage ί吕唬加(4) The switching state of the first-曰曰 transmission is based on the application of a second "write" voltage signal between the gate electrode and the drain electrode, such as) By the crack or the wall of the mouth, the purple structure is slashed away or or in addition, in one of the present inventions, the preferred embodiment of the towel can be used to control the signal at the same time. Write pulse and ❹ '", human pulse occurs (even if only two of the bits are to be overwritten). Because the two horns enable two bits to be stored in a single memory element, Compared with the memory components of the technology, the area density is increased, although the memory density is increased by 2, compared with the similar memory elements having only one Jingtian Shou, the majority of the areas occupied by the U and the U are the same. Times because of the simple measurement by the proposed in accordance with the present invention The body 7L contains two information bits. The ferroelectric material has a spontaneous polarization that is stable and can be switched hysterically by the application of an electric field. The ferromagnetic material is stable and can be applied by applying a magnetic field. 201027715 Spontaneous magnetization of switching. Multiferroic materials possess simultaneous ferroelectric ordering and magnetic ordering. These two ordered parameters are coupled. There are ferromagnetic, subferromagnetic and antiferromagnetic multiferrosomes ( Multiferroics) Therefore, a multiferroic material domain can be programmed by applying a first voltage signal and a second voltage signal across it (eg, by applying an electric field pulse). Due to ferromagnetism, subferromagnetic or anti- The coupling of ferromagnetic ordered parameters to ferroelectric ordered parameters, which also leads to the stylization of the ferromagnetic, subferromagnetic or antiferromagnetic ordering parameters. For the "read" operation, the spin valve effect can be used (spin Effect). The self-twisting valve effect causes a resistance between the switchable source electrode and the electrodeless electrode (for a current flowing between the source electrode and the drain electrode in at least one direction). For this purpose, both the drain electrode and the source electrode are preferably ferromagnetic or comprise at least a ferromagnetic element. Further, the multiferroic material has a sufficient influence on the relative orientation of the magnetic moment of the charge carriers flowing to the source electrode or the drain electrode and the relative orientation of the magnetization of the source electrode or the drain electrode. This can be done in one of two possible ways: - As a first alternative, a multiferroic material can result in a state-dependent magnetic field that affects the magnetic moment of the charge carriers flowing into the conductive channel. Therefore, switching of the ferromagnetic/subferromagnetic/antiferromagnetic ordering parameters results in switching of the magnetic field in the channel region. This can be done by: a dipole ferromagnetic (or potentially a gated ferromagnet; in this context, a definition of "gate ferromagnetic", "ferromagnetic", "ferromagnetic" or "iron" The magnetic material includes a secondary ferromagnetic material, and those skilled in the art know that the function of the ferromagnetic body can also be coupled to the 143837.doc 201027715 iron material by means of a secondary ferromagnetic material; then the 'gate ferromagnetic and multiferroic material Direct contact is made (direct contact without any matter in between), and then the ferromagnetic (or subferromagnetic) multiferroic material itself produces a sufficiently large stray field. As a first alternative, the switching of the ferromagnetic/subferromagnetic/antiferromagnetic ordering parameters of the first domain and the second domain may respectively cause the magnetization directions of the source electrode and the drain electrode to switch, thereby causing spin The valve changes the preferred orientation of the charge sub-magnetic moment. For this purpose, the source electrode is directly exchange coupled to the fourth (-) of the multiferroic material, and the electrodeless electrode is exchanged to the second domain and the charge carriers for causing the flow to the source and drain electrodes The magnetic moment has a pre-defined better $-directed component (for example, a fixed magnetization (pinning) gate ferromagnetic body, and the stray field is combined with the magnetic moment of the charge carrier when the charge sub-flow is in the human channel region) . In either case, the "read" process for the first and second bits depends on the generation of the electrical product that causes the charge carriers to flow to the source and drain electrodes, respectively. Preferably, this is achieved by applying a "read" pulse between the source electrode and the tear electrode. In most general cases, the above-described spin 阙 effect results in a voltage-current characteristic that is polarity dependent. Depending on the polarity of the pulse, the first bit or the second bit is read. This also implies that the memory element is not of the full random access type because one bit and the second bit may not be read at the same time. However, it is possible to simultaneously read the bits of different memory elements in the memory. τ U. The memory element is characterized by its non-volatile nature, because the ferroelectric ordering parameters and magnetic ordering parameters of the multi-tanning material are non-volatile iron 143837.doc 201027715 due to its non-volatile characteristics Low power consumption can be expected. In addition, 'the ferroelectric polarization of the multiferroic element is changed to an intrinsic fast process (5 〇 ps-l nS). Therefore, the memory element according to the present invention has a significant stylized speed compared with the flash memory ^μ8). advantage. In addition, the 'memory element can be implemented in a simple small unit cell (only having the required space of 6F2, in the absence of any additional resistors or capacitors) and thus compared to prior art memory elements (iv) Integration at a higher area density. Again, it is well scaled when used for smaller units because it does not contain any capacitors. Yet another advantage of the memory component (especially compared to MRAM) is the reduced write energy (about 10 joules per bit, relative to the MRAM 1 joule per joule per bit). ..., another advantage of the memory component (especially compared to deuteration) is a lower programmed voltage (approximately 1 V vs. Flasl^15 ν). Possibly ferromagnetic polyferric bodies include cristobalite (Ni3B7013I), vocal ore (10), such as BiMn〇3ATbMn〇3), and sulfates (such as cdCr). However, in these currently known materials, coupled ordering The parameters are only non-zero at low temperatures, such that the memory components and devices made therefrom are primarily suitable for particular applications that are acceptable to the cooling device. In a preferred embodiment, the components comprise a cooling I. Preferably, The operating temperature of the memory element provided by the cooling device is lower than Kelvin. However, according to a particularly preferred embodiment, the multiferroic material is coupled by exchange bias. To the gate ferromagnetic or drain electrode and source 143837.doc 201027715 extremely pinned gate ferromagnetic or multi-ferrite antiferromagnetics of the drain electrode and source electrode. This "ferromagnetic pinning" embodiment is first characterized by the advantage that the known antiferromagnetic multiferroic body is more temperature stable than its ferromagnetic counterpart. Further, there is a superparamagnetic limit (that is, a magnitude at which the magnetic anisotropy of the magnetic layer in the cell becomes equivalent to kT, where k is a Boschmann constant and T is an absolute temperature, The magnetization becomes unstable below the limit. It is not a special advantage of the problem in antiferromagnetics, so that the unit can be designed to be equally small and still stable.实例 An example of an antiferromagnetic multiferroic material may be BiFe03. The memory device according to the present invention can be used as both a memory unit of a pure memory device and/or a memory unit in a logic circuit of a programmable logic. Examples of such logic circuits incorporating memory devices in accordance with the present invention are found in European Patent Application EP 08104301. Thus, due to the method according to the present invention, memory and logic circuits can be integrated without additional masking steps, which provide significant advantages to the integrated circuits. [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The figures are schematic and not to scale. In the drawings, the same reference numerals are used to refer to the In the ferromagnetic material of the elements depicted in the figures, solid arrows generally indicate a fixed magnetization. The fixed magnetization may be a magnetization of the nail violet in a manner that has a more continuous field than the sum of the effective fields acting on it during normal operation or otherwise otherwise affected to be in the normal state of the stylized component. 143837.doc 201027715 Change the magnetization direction during operation. The open arrows indicate the magnetization that can be switched by stylizing the voltage pulse. In the case of pinning magnetization, no pinned layers are shown in the figures. The pinning of the ferromagnetic layer is well known to those skilled in the art of magnetic memory (for example) from MRAM memory. Pinning is not discussed further here. The memory device 描绘 depicted in FIG. 1 includes a source electrode 12 and a base electrode 13 on the substrate 3; and the electrode electrode 13 and the drain electrode 13 are both ferromagnetic conductive materials, for example, cobalt alloy or high. Magnetically conductive alloy (FeNic〇 alloy). The conductive via 21 is formed between the source electrode and the drain electrode, for example, by an n-type doped region in the substrate or in any other suitable manner; however, the conductive via may not need to comprise the same material as the substrate 3. The substrate can be any known or other suitable substrate, such as a semiconducting substrate, such as gallium arsenide or germanium. The substrate in the depicted embodiment is in contact with a reference voltage contact (i.e., ground contact 8 (or "bulk contact"). As is known in the art, there may be (not depicted) a connection between, for example, the source electrode 12 and the ground contact 8 such that the source electrode 12 is always at ground potential (or optionally at other reference potentials), or As an alternative, there may be a connection between the gate electrode and the ground contact, as described further below. The memory element 1 further includes a gate, the gate includes a gate electrode 17, a ferromagnetic layer 14 (which is any ferromagnetic conductive material), and an antiferromagnetic multiferroic property between the interpole electrode and the ferromagnetic layer. Layer 15. The ferromagnetic layer is insulated from the source electrode 12 and the drain electrode 13 and the conductive path 21 by the dielectric layer 16. Multi-iron layer! 5 exchange coupling to the ferromagnetic layer. Therefore, the switching of the order parameters of the multiferroic layer also results in the cutting of the ordered parameters of the ferromagnetic layer in the immediate vicinity (therefore, the switching of magnetization is caused). From the multiferroic layer 15 and the iron layer, the M double layer is now made such that it can contain two stable crystals _: 14.Bu 15"; 14 2, 15 2 . The dashed line 18 in the figure depicts the potential separation line between the first domain 14.1, 15.1 and the second domain 14·2, 15 2 . The crystal can be separated by the objective (four) addition junction # at a fixed position. mouth. The structure acts to locally split the double layer or act as a nail wall member. The structure can be, for example, a micro slit at the location of the dashed line, or an impurity or similar pinned domain wall. As an alternative to the purpose-added structure, the <column' bilayer may also lack any purpose-added structure for separating the crystals. The crystal nozzles can then be located in non-predefined locations and can occur only by causing different ordered parameter orientations in the vicinity of the drain and source electrodes, respectively. In any case, the 'double layer must be anisotropic and large enough to maintain two crystal nozzles after the field has been cut, that is, in any case, the two (five) crystals 4 must be stable' to make the memory Body components are non-volatile. The coexistence of two magnetically stable crystals has been predicted and observed in structures that fall to, for example, 2 〇 nm or even smaller. The lower limit of the size of the double layer that stabilizes the nozzle depends on the anisotropy, which in turn depends on the bilayer material composition. A "write" voltage signal for the two domains can be applied between the gate electrode 17 and the source electrode 12 or between the gate electrode P and the drain electrode 13, respectively. For this purpose, the thickness and conductivity of the multiferroic layer 15 and the dielectric layer 16 are preferably adapted to each other 'so that the voltage drop across the multiferroic layer corresponds to the idle pole 143837.doc 201027715 electrode and source electrode or germanium Most of the voltage between the pole electrodes (preferably at least half).自 The spontaneous polarization of the multiferroic material can be switched between four states (two states per crystal domain) by writing the voltage signal ', as explained in more detail with reference to Figures 3a to 6c. Since the material is more ferrous, the switching of spontaneous polarization also switches the antiferromagnetic ordering parameters (for example) by reversing the order of the "up" and "down" magnetization layers in the multiferroic material. The ferromagnetic layer 1 is tightly bonded to the iron layer. Thus, the switching of ferroelectric spontaneous polarization in 4 15' 1 ' 1 5.2 of the multiferroic material has the effect of also switching the magnetization direction of the ferromagnetic layer domain 14. 14.2. , Figure 2 屺 体 体 TG! The design differs from the design in that the order of the multiferroic layer and the order of the ferromagnetic layer 14 are reversed. Multi-iron layer (10) on ferromagnetic! • The green layer 14 (-side) is electrically connected to the conductive channel 21 and the source electrode and is not electrically connected: (other side). The dielectric layer 16 is no longer needed because the multiferroic material 15 is electrically insulated as compared to most of the ferromagnetic materials used in the general section.
:::獨閘極電極層17係任選的且圖式中未展示因為 鐵磁性層14自身可視情況充當閘極電極。 亦在圖2之組態中，可太pq & € ^ 2 Θ極電極（鐵磁性層14)與源 :極2或没極電極13之間施加寫入電壓信號。與圖丨之 態對比，幾乎整個電壓降將 ,, , L ^ 纖性層’使得與圖1 、且態相比較，所需寫入電壓 係較佳的。 彳低因此，圖2之組態通 之 藉由圖3a至圖6c，參看圖 記憶體元件之工作原理， 2之實施例來解釋根據本發明 因此解釋記憶體元件之「寫 143837.doc -12- 201027715 入」操作及「讀取」操作。 圖3a、圖4a、圖5a及圖以表示用於由兩位元元件所採取 之四種不同狀態之「寫入」過程。在每一「寫入」過程 - 令，在閘極電極14( 一方面）與源極電極12及汲極電極13(另 • —方面）之間同時施加「寫入」電屡信號（亦在顛倒兩個位 兀中之僅一者（因此顛倒兩個晶疇中之僅一者）的情況下）。 舉例而σ 了在母一「寫入」過程期間使閘極電極1 4保持::: The single gate electrode layer 17 is optional and is not shown in the drawings because the ferromagnetic layer 14 itself can function as a gate electrode. Also in the configuration of Fig. 2, a write voltage signal can be applied between the too pq & €^2 drain electrode (ferromagnetic layer 14) and the source: pole 2 or the electrodeless electrode 13. In contrast to the state of the figure, almost the entire voltage drop will be , , , L ^ fibrous layer 'to make the desired write voltage better than the state of Figure 1. Therefore, the configuration of FIG. 2 is explained by referring to FIG. 3a to FIG. 6c, referring to the working principle of the memory element, and the embodiment of FIG. 2 explains the explanation of the memory element according to the present invention. "Write 143837.doc -12 - 201027715 "In" operation and "Read" operation. Figures 3a, 4a, 5a and 3D illustrate the "write" process for the four different states taken by the two-element element. In each "write" process, a "write" electrical signal is simultaneously applied between the gate electrode 14 (on the one hand) and the source electrode 12 and the drain electrode 13 (other side) (also in Reversing only one of the two positions (and thus reversing only one of the two domains). For example, σ keeps the gate electrode 14 during the mother-to-write process.
m 於〇 V電位，而向源極電極及汲極電極均獨立地供應丨V 或-IV「寫入」脈衝。 圖3a對應於（例如）藉由向源極電極及汲極電極兩者施 加-「】v脈衝而獲得之「向上_向上」（up_up)狀態。圖儿表 示「向上-向下」（up_down)狀態（-1 V施加至源極電極， + 1 V施加至汲極電極），圖氕表示「向下向上」（d〇wn up) 狀態（+1 v/-i V)，且圖3d表示「向下_向下」（d〇wn_d〇wn) 狀態（+1 V/+1 v)。 • 當然，在本文中，經施加電壓之量及其絕對極性為純粹 實例。 根據本發明之記憶體元件不為完全隨機存取記憶體元 件。不能同時讀取每一記憶體元件之第一資訊位元及第二 資訊位元。圖3b、圖4b、圖5b及圖6b分別展示用於「向 上-向上」狀態、「向上-向下」狀態、「向下-向上」狀態及 「向下_向下」狀態之第一資訊位元之「讀取」過程，且 圖3c、圖4c、圖5c及圖6c展示用於其第二資訊位元之「讀 取」過程。 143837.doc -13- 201027715 「讀取」過程係基於自旋閥效應。對於「讀取」操作， 依賴於是讀取[位元或是讀取第二位元，在源極電極與 汲極電極之間施加所要極性之小「讀取」電壓脈衝。此導 致電荷載子（依賴於導電㈣型而為n型電荷載子或p型電 荷載子）流入源極電極與汲極電極之間的通道區域。電荷 =係藉由該等圖中通道區域21内之箭頭象徵，箭頭表^ 電荷載子之磁矩〇纽#頭說明其流動方向。當經過通道 區域21時’電荷載子經受藉由鐵磁性層叫產生之磁場。 此磁場在電荷載子經受磁場的情況下確定電荷載子之磁矩 因此，當電荷載子進人鐵磁性源極電極或㈣電極後， 載子所流至之電極(在用於第—位元之「讀取」過 極電極，且在用㈣二位元之「讀取」過程中為 極電極）料之晶心科Μ荷載子之定向。 行情形。若大多數電荷載子之磁矩經定向成平 f 源極電極歧極電極之磁化，則具有經維 =矩之電荷載子可容易地進入電極。與此對比，、若電荷 經疋向成反平行於其所流至之電極， 材料時遭遇能量障壁(例 電極 此能量障錢應㈣料「自㈣料次㈣其磁矩）。 造成「巨磁電阻」或「H間」效應）本質上類似於亦 文獻卜 1料磁電阻」之效應且因而描述於 量障壁(各別第—或第二位元為之「：取」組態中遭遇低能 位兀為向上」或「1」）。在圖 143837.doc 201027715 4c、圖5b、圖6b及圖6c中感測高能量障壁（各別第一或第 一位元為「向下」或「〇」）。m is at the V potential, and the 丨V or -IV "write" pulse is supplied independently to the source electrode and the drain electrode. Fig. 3a corresponds to, for example, an "up_up" state obtained by applying a -" v pulse to both the source electrode and the drain electrode. The figure shows the "up_down" state (-1 V applied to the source electrode, + 1 V applied to the drain electrode), and the figure indicates the "down to up" state (+ 1 v/-i V), and Figure 3d shows the "down_down" (d〇wn_d〇wn) state (+1 V/+1 v). • Of course, in this paper, the amount of applied voltage and its absolute polarity are pure examples. The memory component in accordance with the present invention is not a fully random access memory component. The first information bit and the second information bit of each memory element cannot be read simultaneously. Figures 3b, 4b, 5b, and 6b show the first information for the "up-up" state, the "up-down" state, the "down-up" state, and the "down-down" state, respectively. The "read" process of the bit, and Figures 3c, 4c, 5c and 6c show the "read" process for its second information bit. 143837.doc -13- 201027715 The "read" process is based on the spin valve effect. For the "read" operation, it is dependent on reading the [bit or reading the second bit, applying a small "read" voltage pulse of the desired polarity between the source electrode and the drain electrode. This conducts a charge carrier (an n-type charge carrier or a p-type charge carrier depending on the conductive (four) type) into the channel region between the source electrode and the drain electrode. The charge = is represented by the arrow in the channel region 21 in the figures, and the magnetic moment 〇 # # head of the arrow table indicates the flow direction. When passing through the channel region 21, the charge carriers are subjected to a magnetic field generated by a ferromagnetic layer. The magnetic field determines the magnetic moment of the charge carrier when the charge carrier is subjected to a magnetic field. Therefore, when the charge carrier enters the ferromagnetic source electrode or the (four) electrode, the electrode to which the carrier flows (in the first position) Yuan "reads" the electrode of the pole, and in the "four" two-bit "read" process is the orientation of the centroid charge carrier of the electrode. Line situation. If the magnetic moment of most charge carriers is oriented to the magnetization of the flat f source electrode, the charge carriers with the dimension = moment can easily enter the electrode. In contrast, if the charge is antiparallel to the electrode to which it flows, the material encounters an energy barrier (such as the electrode, the energy barrier should be (four) material "from (four) material (four) its magnetic moment). The magnetoresistance or "inter-H" effect is essentially similar to the effect of the magnetic resistance of the material and is thus described in the volume barrier (the individual - or second bit is encountered in the ":" configuration The low energy level is up or "1"). High energy barriers are sensed in Figures 143837.doc 201027715 4c, 5b, 6b, and 6c (the first or first element is "down" or "〇").
因此，源極電極12(用於第一位元）及汲極電極13(用於第 二位元）充當用於其鄰近中晶疇之定向之鐵磁性偵測器。 鐵磁性層14之雜散場在電荷載子流入各別電極之前影響電 荷載子。（極性依賴性）電流-電壓特性係幾乎獨立於另一晶 疇（亦即，更遠離偵測電極之晶疇）之鐵磁性晶疇定向。此 係藉由圖4b、圖4c、圖5b及圖5c_之小箭頭說明。舉例而 言，在圖4b之組態中，來自汲極電極13之電荷载子之磁矩 最初經極化成平行於汲極電極之磁化，因為汲極電極係鐵 磁性的。在第二晶疇之影響下，磁矩在電荷載子進入電荷 載子受第一晶疇之磁場影響之區域（其導致磁矩翻轉）之前 部分地或完全地倒轉。 作為備註，依賴於源極電極及汲極電極鐵磁性材料之電 子結構，在一些狀況下，自旋閥效應可以相反方式工作： 亦即，具有平行磁矩之電荷載子與反平行磁矩電荷載子相 比較可接著遭遇更高能量障壁。此可（例如）為汲極電極材 料包含在大多數能帶中不存在電荷載子之自由狀態之所謂 的「強」鐵磁體時的狀況。然而，為了達成本發明之目 的’效應保持相同：僅重要的係在電荷載子具有平行於其 所流至之電極之磁化之磁矩的情形與電荷载子具有反平行 於其所流至之電極之磁化之磁矩的情形之間的電流_電壓 特性中存在某種差異。換言之，極性依賴性電壓-電流特 性（例如，針對特定經施加「讀取」電壓或為達成特定 143837.doc 201027715 「讀取電流」所需要之電壓而發生的電流)對於電荷載子 磁矩與電荷載子所流至之電極之磁化之兩個不同相對定向 不相同。 圖7說明一替代實施例，其中閘極鐵磁性層34具有固定 磁化，且源極電極12及汲極電極13之磁化交換耦合至多鐵 性層15且可藉由倒轉多鐵性層15之有序參數加以倒轉。在 此組態中，源極電極及汲極電極需要與多鐵性層進行直接 實體接觸。然而，不需要多鐵性材料15與釘紮閘極鐵磁體 34之間的直接接觸。實情為，在釘紮閘極鐵磁體34與多鐵 性材料15之間可存在一種其他材料/多種其他材料之一個 層或若干層（未展示），例如，用於防止閘極鐵磁體34與多 鐵性材料15之間的交換麵合的金屬非磁性層。 圖8a至圖11 c展示用於如圖7所示之實施例之寫入過程及 讀取過程。其表示類似於圖3a至圖6c之表示。 類似於圖1及圖2之實施例，在「寫入」過程中，可藉由 閘極電極34與源極電極12及汲極電極13之間的「寫入」電 壓信號來分別設定多鐵性材料之第一晶疇15.丨及第二晶禱 15_2之定向’如圖8a、圖9a、圖l〇a及圖11a所說明。歸因 於交換耦合，以此方式，亦設定（程式化）源極電極及汲極 電極之磁化，此類似於圖1及圖2之實施例中晶_ 14.1、 14.2之程式化。 在「讀取」過程中，當注入至通道區域21中時的電荷載 子磁矩根據供以注入其之電極之極化而極化，但在經過通 道區域21之後始終根據閘極電極之磁場（在所描繪組態中 143837.doc •16- 201027715 向上）而極化。因此，圖7之實施例在讀取過程中產生如下 電荷載子：電荷载子在流至源極電極12或汲極電極13時具 有預定義磁矩定向。因此，歸因於如上文所描述之自旋闕 效應，電#载子流充當用於伯測源極電極或沒極電極之磁 化定向之偵測構件。 曰最後’圖描繪又一實施例。在此實施例中，具有兩個 晶疇35.1、35.2之多鐵性層35為多鐵性鐵磁體。因此，其 直接產生磁場，且無需額外鐵磁性層14。其工作原理以其 他方式相同於圖2之實施例之工作原理。 本發明之另外變體係可能的。舉例而t，在具有可切換 源極電極及沒極電極磁化之實施財，界定流至源極電極 及汲極電極之電荷载子之磁矩定向的磁場無需屬於間極。 實清為’亦可替代地使用產生用於複數個記憶體元件之所 要均磁場的「全域」磁場源，例如，普通鐵磁性塗料， 或外部鐵磁體、電磁體等等。 【圖式簡單說明】 圖1展示根據本發明之記憶體元件之第一實施例的橫截 面； 圖描繪根據本發明之記憶體元件 仟之第一替代實施例的 橫截面； 圖3a至圖6c展示由圖2之裝置所趑你+ . 直所鉍取之四個邏輯狀態的 冩入」步驟及「讀取」步驟； :描綠根據本發明之記憶體元件之又一替代 的 橫截面； 143837.doc •17· 201027715 圖8a至圖lie展示由圖7之裝置所採取之四個邏輯狀態的 「寫入」步驟及「讀取」步驟；及 圖12展示根據本發明之記憶體元件之再一實施例。 【主要元件符號說明】 1 記憶體元件 3 基板 8 地面接點 12 源極電極 13 汲極電極 14 鐵磁性層 14.1 穩定晶嘴/第一晶嘴 14.2 穩定晶鳴/第二晶_ 15 反鐵磁性多鐵性層/多鐵性材料/多鐵性反鐵磁體 15.1 穩定晶脅/第一晶嘴 15.2 穩定晶嘴/第二晶_ 16 介電層 17 閘極電極 18 電位分離線 21 導電通道 34 閘極鐵磁性層/釘紮閘極鐵磁體/閘極電極 35 多鐵性層/多鐵性材料/多鐵性鐵磁體 35.1 第一穩定晶 35.2 第二穩定晶疇 143837.doc -18-Thus, source electrode 12 (for the first bit) and drain electrode 13 (for the second bit) act as ferromagnetic detectors for the orientation of their adjacent mid-domains. The stray field of the ferromagnetic layer 14 affects the charge carriers before the charge carriers flow into the respective electrodes. The (polarity dependent) current-voltage characteristic is oriented almost independently of the ferromagnetic domain of another domain (i.e., the domain further away from the detecting electrode). This is illustrated by the small arrows of Figures 4b, 4c, 5b and 5c_. For example, in the configuration of Figure 4b, the magnetic moment of the charge carriers from the drain electrode 13 is initially polarized to be parallel to the magnetization of the drain electrode because the drain electrode is ferromagnetic. Under the influence of the second domain, the magnetic moment is partially or completely inverted before the charge carriers enter the region where the charge carriers are affected by the magnetic field of the first domain, which causes the magnetic moment to flip. As a remark, depending on the electronic structure of the source electrode and the gate electrode ferromagnetic material, in some cases, the spin valve effect can work in the opposite way: that is, the charge carriers and antiparallel magnetic moment charges with parallel magnetic moments The carrier can then encounter a higher energy barrier. This may, for example, be the case when the drain electrode material contains a so-called "strong" ferromagnet in a free state in which most of the energy carriers are free of charge carriers. However, for the purposes of the present invention, the effect remains the same: only important is the case where the charge carrier has a magnetic moment parallel to the magnetization of the electrode to which it flows and the charge carrier has an antiparallel to it. There is some difference in the current-voltage characteristics between the cases of the magnetic moment of the magnetization of the electrodes. In other words, the polarity-dependent voltage-current characteristic (for example, the current that occurs when a specific "read" voltage is applied or the voltage required to achieve a specific "read current" of 143837.doc 201027715) is applied to the charge carrier magnetic moment. The two different relative orientations of the magnetization of the electrode to which the charge carriers flow are different. Figure 7 illustrates an alternate embodiment in which the gate ferromagnetic layer 34 has a fixed magnetization and the magnetization exchange of the source electrode 12 and the drain electrode 13 is coupled to the multiferroic layer 15 and can be reversed by reversing the multiferroic layer 15 The sequence parameters are reversed. In this configuration, the source and drain electrodes require direct physical contact with the multiferroic layer. However, direct contact between the multiferroic material 15 and the pinned gate ferromagnetic body 34 is not required. In fact, one or more layers (not shown) of other materials/multiple materials may be present between the pinned gate ferromagnet 34 and the multiferroic material 15, for example, to prevent the gate ferromagnetic body 34 from A metal non-magnetic layer that is exchanged between the multiferroic materials 15. Figures 8a through 11c show the write process and the read process for the embodiment shown in Figure 7. It represents a representation similar to that of Figures 3a to 6c. Similar to the embodiment of FIG. 1 and FIG. 2, in the "writing" process, the multi-iron can be separately set by the "write" voltage signal between the gate electrode 34 and the source electrode 12 and the drain electrode 13. The orientation of the first domain 15.. and the second pray 15_2 of the material is as illustrated in Figures 8a, 9a, 1a and 11a. Due to the exchange coupling, in this way, the magnetization of the source and drain electrodes is also set (programmed), which is similar to the stylization of the crystals _ 14.1, 14.2 in the embodiment of Figures 1 and 2. In the "reading" process, the charge carrier magnetic moment when injected into the channel region 21 is polarized according to the polarization of the electrode to be injected therein, but is always based on the magnetic field of the gate electrode after passing through the channel region 21. Polarized (in the depicted configuration 143837.doc •16- 201027715 up). Thus, the embodiment of Figure 7 produces charge carriers during reading: the charge carriers have a predefined magnetic moment orientation when flowing to source electrode 12 or drain electrode 13. Therefore, due to the spin 阙 effect as described above, the electric # carrier stream acts as a detecting member for the magnetic orientation of the source electrode or the electrodeless electrode. The final 'figure' depicts yet another embodiment. In this embodiment, the multiferroic layer 35 having two domains 35.1, 35.2 is a multiferromagnetic ferromagnet. Therefore, it directly generates a magnetic field and does not require an additional ferromagnetic layer 14. Its working principle is the same as that of the embodiment of Fig. 2 in other ways. Additional variations of the invention are possible. For example, t, in the implementation of the switchable source electrode and the electrodeless magnetization, the magnetic field that defines the magnetic moment of the charge carriers flowing to the source electrode and the drain electrode need not belong to the interpole. It is also possible to alternatively use a "global" magnetic field source that produces a desired magnetic field for a plurality of memory elements, such as a common ferromagnetic coating, or an external ferromagnetic, electromagnet or the like. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a cross section of a first embodiment of a memory element in accordance with the present invention; a cross-section of a first alternative embodiment of a memory element according to the present invention; Figure 3a to Figure 6c Shows the steps of the "intrusion" of the four logical states taken by the device of Figure 2 and the "read" step; a further cross section of the memory element according to the invention; 143837.doc •17· 201027715 Figures 8a to lie show the “write” and “read” steps of the four logic states taken by the device of Figure 7; and Figure 12 shows the memory component in accordance with the present invention. Yet another embodiment. [Main component symbol description] 1 Memory component 3 Substrate 8 Ground contact 12 Source electrode 13 Dip electrode 14 Ferromagnetic layer 14.1 Stable crystal nozzle / First crystal nozzle 14.2 Stable crystal / Second crystal _ 15 Antiferromagnetic Multiferroic/multiferroic material/multiferromagnetic antiferromagnetic 15.1 Stabilizing crystal threat/first crystal nozzle 15.2 Stabilizing crystal nozzle/second crystal _ 16 Dielectric layer 17 Gate electrode 18 Potential separation line 21 Conductive channel 34 Gate ferromagnetic layer / pinned gate ferromagnet / gate electrode 35 multiferroic layer / multiferroic material / multiferromagnetic ferromagnetic 35.1 first stable crystal 35.2 second stable crystal domain 143837.doc -18-