GB2560936A - Spin electronic device - Google Patents

Spin electronic device Download PDF

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Publication number
GB2560936A
GB2560936A GB1704985.9A GB201704985A GB2560936A GB 2560936 A GB2560936 A GB 2560936A GB 201704985 A GB201704985 A GB 201704985A GB 2560936 A GB2560936 A GB 2560936A
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source
drain
gate
spin
bias
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GB201704985D0 (en
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Myronov Maksym
Morrison Chris
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University of Warwick
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University of Warwick
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66984Devices using spin polarized carriers
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • G11C11/1673Reading or sensing circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225Auxiliary circuits
    • G11C11/2275Writing or programming circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5657Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using ferroelectric storage elements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/22Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using galvano-magnetic effects, e.g. Hall effects; using similar magnetic field effects
    • H01L27/222Magnetic non-volatile memory structures, e.g. MRAM
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/22Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using galvano-magnetic effects, e.g. Hall effects; using similar magnetic field effects
    • H01L27/222Magnetic non-volatile memory structures, e.g. MRAM
    • H01L27/226Magnetic non-volatile memory structures, e.g. MRAM comprising multi-terminal components, e.g. transistors
    • H01L27/228Magnetic non-volatile memory structures, e.g. MRAM comprising multi-terminal components, e.g. transistors of the field-effect transistor type
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

Abstract

A spin electronic transistor device 1 (spintronic) (1) comprising source and drain electrodes (2, 3), a semiconductor channel (5) running between the source and drain electrodes and a gate electrode structure (6) interposed between the source and drain electrodes comprising a gate electrode (7) and a gate dielectric (8). The source and drain electrodes are multiferroic such that each electrode has a respective magnetization and polarization which are magnetoelectrically coupled. Changing the direction of the electrical polarization also results in a change in direction of the magnetization, hence programming of the magnetization direction results from an application of electrode electrical bias. Suitable multiferroic materials are Bismuth Manganese Oxide BiMnO3 and Cobalt Chromium Oxide CoCr2O4 or synthetic constructions thereof. Seed layers comprising of monolayers of MgO or Al2O3 may be used underneath. The transistor channel preferably comprises of strained germanium forming a quantum well semiconductor channel. The channel may sit on a SiGe buffer layer 10 and a base silicon substrate 12. The gate is preferably not multiferroic. Programming the electrical polarization and magnetic polarization of each of the drain electrode involves applying either a positive (0 bit) or negative (1 figures 5a/b) bias on both the gate and source or drain terminals leaving the drain or source electrode (respectively) floating. Reading the memory / spintronic device involves applying appropriate bias voltages (or current) on the source and drain terminals and detecting the current to determine the resistance of the spin electronic device. The resistance depends on the GMR Giant Magnetoresistance effect. The spin current through the channel of the spin device is determined by the relative bias voltages and relative magnetization directions of the source and drain regions. In addition application of a gate bias invokes operation of a spin transistor. Other embodiments are seen in figure 8 and 14 whereby the gate material overlaps the drain region (figure 8) or where a dielectric and separate gate electrode (22, figure 14) are provided.

Description

Spin electronic device

Field of the invention

The present invention relates to a spin electronic device, in particular, to a multiferroic-based spin electronic device.

Background

Spin-based electronic devices (commonly referred to as “spintronic devices”) offer the possibility of not only implementing logic circuits which consume less power, but also to provide non-volatile storage. Examples of spin-based transistors are described in US US6753562 Bi and WO 2015/129865 Ai.

Summary

According to a first aspect of the present invention there is provided a spin electronic device. The spin electronic device comprise source and drain electrodes, a semiconductor channel running between the source and drain electrodes and a gate electrode structure interposed between the source and drain electrodes comprising a gate electrode and a gate dielectric. The source and drain electrodes are multiferroic such that each electrode has a respective magnetization and polarization which are magnetoelectrically coupled.

Thus, the gate can be used to control orientation of the magnetization of the source and/or drain electrodes, as well as modulate spin transport between in the channel.

The source and/or drain electrode(s) may comprise a multiferroic material. The multiferroic material may be bismuth manganese oxide or cobalt chromium oxide.

The source and/or drain electrode(s) may comprise a synthetic multiferroic, for example, comprising a stack of layers which behave as a multiferroic material.

The device may further comprise a seed layer interposed between the semiconductor channel and a source or drain electrode. The seed layer may comprise an oxide.

The semiconductor channel may comprise a group IV elemental semiconductor material or a group IV-based compound semiconductor material. The semiconductor channel may comprise germanium. The semiconductor channel may comprise a quantum well. The semiconductor channel may be under strain.

The device may comprise a substrate and a buffer layer structure interposed between the substrate and the semiconductor channel.

The gate electrode and/or gate dielectric may not be magnetically polarisable. The gate electrode and/or gate dielectric may not be electrically polarisable. The gate electrode and/or gate dielectric may not be multiferroic.

According to a second aspect of the present invention there is provided a spin device and a set of bias sources arranged to controllably apply a respective bias to the source, drain and gate electrodes.

In a first bias configuration, the bias sources may apply biases such that an electric field is applied to the source or drain electrode so as to orientate polarization in the source or drain electrode in a first predetermined direction. In a second bias configuration, the bias sources may apply biases such that an electric field is applied to the source or drain electrode so as to orientate polarization in the source or drain electrode in a second predetermined direction, which is different from the first predetermined direction.

The apparatus may further comprise a current meter and, in a third bias configuration, the bias sources may apply biases such that a current is driven between the source and drain contacts and wherein the current meter is arranged to measure the current.

In a fourth bias configuration, the bias sources may apply biases such that a spin current is driven between the source and drain contacts and a first gate bias does not substantially modulate spin in the spin current.

In a fifth bias configuration, the bias sources may apply biases such that a spin current is driven between the source and drain contacts and a second gate bias substantially modulates spin in the spin current.

Brief Description of the Drawings

Certain embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:

Figure l is a schematic side view of a first field-effect transistor comprising multiferroic contact electrodes, a gate electrode and a semiconductor channel;

Figure 2 illustrates a buffer layer structure on which the semiconductor channel shown in Figure 1 may be disposed;

Figure 3 is a schematic plan view of the field-effect transistor shown in Figure 1 illustrating polarizations and magnetizations of the multiferroic contact electrodes; Figure 4 illustrates voltage biases which can be applied to the contact and gate electrodes of the field-effect transistor shown in Figure 1;

Figure 5a and 5b illustrates programming the field-effect transistor shown in Figure 1; Figure 6a and 6b illustrate reading the field-effect transistor shown in Figure 1;

Figures 7a and 7b illustrate modulating spin transport in the field-effect transistor shown in Figure 1;

Figure 8 is a schematic side view of a second field-effect transistor comprising multiferroic contact electrodes, a gate electrode and a semiconductor channel;

Figure 9 is a schematic plan view of the second field-effect transistor shown in Figure 8 illustrating polarizations and magnetizations of the multiferroic contact electrodes; Figure 10 illustrates voltage biases which can be applied to the contact and gate electrodes of the second field-effect transistor shown in Figure 8;

Figure 11a and 11b illustrates programming the second field-effect transistor shown in Figure 8;

Figure 12a and 12b illustrate reading the second field-effect transistor shown in Figure 8;

Figures 13a and 13b illustrate modulating spin transport in the field-effect transistor shown in Figure 8;

Figure 14 is a schematic side view of a third field-effect transistor comprising multiferroic contact electrodes, a gate electrode and a semiconductor channel;

Figure 15 is a schematic plan view of the third field-effect transistor shown in Figure 14 illustrating polarizations and magnetizations of the multiferroic contact electrodes; Figure 16 illustrates voltage biases which can be applied to the contact and gate electrodes of the third field-effect transistor shown in Figure 14;

Figure 17a and 17b illustrates programming the third field-effect transistor shown in Figure 14;

Figure 18a and 18b illustrate reading the third field-effect transistor shown in Figure 14;

Figures 19a and 19b illustrate modulating spin transport in the third field-effect transistor shown in Figure 14; and

Figure 20 is a process flow diagram of a method of fabricating a field-effect transistor.

Detailed Description of Certain Embodiments

In the following description, like parts are denoted by like reference numerals.

First spin electronic device 1, ii structure

Referring to Figure 1, a first multiferroic-based spin electronic device 1, ii is shown which is capable of operating as a spin transistor and as non-volatile memory.

The multiferroic-based spin electronic device 1, ii takes the form of a field-effect transistor. The transistor 1, ii includes multiferroic source and drain electrodes 2, 3 (herein also referred to as “contacts”) supported on an upper surface 4 of a semiconductor channel 5. A gate structure 6 comprising a gate electrode 7 and a gate dielectric 8 is also disposed on the upper surface 4 of the channel 5. The channel 5 is supported on an upper surface 9 of a buffer 10 which is formed on a principle surface 11 of a substrate 12, for example, in the form of (ooi)-orientated silicon.

The multiferroic source and drain electrodes 2,3 comprise cobalt chromium oxide (CoCr2O4), bismuth manganese oxide (BiMnO3) or another suitable multiferroic material exhibiting ferromagnetism and ferroelectricity and coupling between magnetic and charge orders, i.e. magnetoelectric coupling. The source and drain electrodes 2, 3 each have a thickness, ti, of, for example, between 10 and 20 nm. The source and drain electrodes 2,3 may be provided with a protective capping layer (not shown) comprising, for example, aluminium or gold. The multiferroic source and drain electrodes 2, 3 may be deposited by molecular beam epitaxy (MBE), by sputtering or other suitable deposition process. Ultra-thin seed layers (not shown) which are only one or two monolayers-thick may be deposited prior to depositing the multiferroic material. The seed layers may comprise, for example, magnesium oxide (MgO) or aluminium oxide (Al2O3).

The semiconductor channel 5 preferably comprises germanium (Ge) and is formed by patterning an epitaxial layer which is sufficiently thin to form a quantum well. The epitaxial layer has a thickness, t2, of, for example, between 10 and 20 nm. The majority carriers in the semiconductor channel 5 are holes.

The gate electrode 7, which is neither magnetic (e.g. not ferromagnetic), nor ferroelectric and, thus, is not multiferroic, comprises a suitable conductive material, such a non-multiferroic metal or metal alloy, such as aluminium or gold, or highly-doped semiconductor material, such as silicon or germanium. The gate electrode 7 may be deposited, for example, by sputtering or by chemical vapour deposition (CVD).

The gate dielectric 8 comprises a suitable dielectric material, such as silicon dioxide (Si02) or germanium oxide (Ge02). The gate dielectric 8 maybe deposited, for example, by sputtering or by chemical vapour deposition (CVD).

Referring also to Figure 2, the channel 5 may be placed under biaxial compressive strain using a suitable buffer 7. In this case, the buffer 7 comprises a compositionally-graded upper layer 13 of silicon-germanium (Sii-xGex) having a thickness, t3, of between, for example, 2 to 10 pm where, for example, x varies from 0.4 to 0.8, from the bottom to the top of the layer, and a lower layer 14 of germanium having a thickness, t4, of between, for example, 1 to 100 nm.

Referring still to Figure 1, the gate length, 1, is smaller than the spin-relaxation length of spin carriers, which in this case are holes, in the channel 5. For strained germanium, the spin-relaxation length is of the order of 1 pm or less.

Multiferroic source and drain contacts 2.2

Referring to Figure 3, the multiferroic source and drain contacts 2, 3 have respective magnetizations 15,16 and respective polarizations 17,18. In each contacts 2,3, the magnetization 15,16 and polarization 17,18 are coupled via magnetoelectric coupling (not shown).

The magnetization 15,16 of a contact 2, 3, for example the drain contact 3, may be switched between two opposite orientations by switching the polarization 17,18 of the contact 2,3. This is achieved by applying suitable voltages Vs, VG, VD to the contact 2,3 and the gate 7 which result in a (net) electric field 19 (Figures 5a & 5b) which can be used to orientate the polarization 17,18.

In the first multiferroic-based spin device l, ii, the contacts 2,3 and gate electrode 7 are arranged to generate in-plane (or “lateral”) electric fields, in particular, along the x-axis. Thus, polarization 17,18 of the multiferroic source and drain contacts 2, 3 can be orientated parallel or anti-parallel along the x-axis. Magnetization 15,16 of the multiferroic source and drain contacts 2,3 can be orientated parallel or anti-parallel along a suitable easy axis (not shown) which, in this case, is orthogonal and is orientated along the y-axis.

The source and drain contacts 2,3 are electrically conductive and if a source-drain potential Vsd of suitable polarity and sufficient magnitude is applied, then spin polarised carriers 20 (Figure 6a & 6b) flow from one contact (herein referred to as the “injector”), in this case the source 2, towards the other contact (herein referred to as the “detector”), in this case the drain 3, with a spin direction determined by the magnetisation 15,16 of the injector. The resistance of the device depends upon the relative orientation of the source and drain contact magnetisations 15,16, for example parallel or anti-parallel.

Electrical control of the spin electronic device 1

Referring to Figure 4, first, second and third voltage bias sources (not shown) can apply respective biases to the source 2, drain 3 and gate 7, and be used to operate the device 1, ii as a memory device or as a logic transistor.

Operation of spin electronic device 1 as memory

Programming

Referring to Figures 5a and 5b, orientation of the magnetization 18 of the drain 3 is used to define the state of the device. Orientation of the magnetization 18 along the positive y-direction is defined to be ‘0’ and orientation of the magnetization 18 along the negative y-direction is defined to be Τ’.

Referring in particular to Figure 5a, a ‘0’ bit is encoded by applying a more positive bias to the gate 7 relative to the drain. For example, this may be achieved by applying a positive bias to the gate 7 and leaving the drain 3 to float, grounding the drain 3 (i.e. applying oV) or by applying a negative bias to the drain 3. This results in a net electric field 19 to be orientated pointing from the gate 7 and drain 2. This causes polarization 16 of the drain 2 to be orientated in the same direction. Via magnetoelectric coupling, the magnetisation 18 is orientated along the positive y-direction. While biases are applied to the gate 7 and drain 2, the source 2 may be set to the same bias as the gate 7 thereby resulting in no net electric field.

Referring in particular to Figure 5b, a Τ’ bit is encoded by applying a more negative bias to the gate 7 relative to the drain. For example, this may be achieved by applying a negative bias to the gate 7 and leaving the drain 3 to float, grounding the drain 3 (i.e. applying oV) or by applying a positive bias to the drain 3. This results in a net electric field 19 to be orientated pointing from drain 2 to the gate 7. This causes polarization 16 of the drain 2 to be orientated in the same direction. Via magnetoelectric coupling, the magnetisation 18 is orientated along the negative y-direction. While biases are applied to the gate 7 and drain 2, the source 2 may be set to the same bias as the gate 7 thereby resulting in no net electric field.

Reading

The state of the device 1 can be read using the giant magnetoresistance (GMR) effect.

Referring to Figures 6a and 6b, the magnetization 15 of the source 2 is fixed (in this case orientated along the negative y-axis).

Referring in particular to Figure 6a, when the magnetizations 15,16 of the source and drain contacts 2, 3 are antiparallel, then the device is in a high resistance state resulting from in a low current when a fixed source-drain voltage is applied. Thus, the device can be read as being in a ‘0’ state.

Referring in particular to Figure 6a, when the magnetizations 15,16 of the source and drain contacts 2, 3 are parallel, then the device is in a low resistance state resulting from in a high current when the same fixed source-drain voltage is applied. Thus, the device can be read as being in a T state.

Thus, the state of device 1, ix can be read by applying a voltage between the source and drain contacts 2,3 and measuring the resistance.

The device 1, ix can operate as a memory device capable of storing data. Thus, the device 1, lx can serve as a memory element in a memory cell (not shown) of an array of memory cells which can be addressed using bit and word lines (not shown).

Operation of the spin device ι, ιΊ as a spin-transistor

As well as being able to operate as a memory device, the device l, ii is operable as a spin transistor.

Referring to Figures 7a and 7b, the magnetization 15 of the source 2 is fixed (in this case orientated along the negative y-axis) and can be used to inject a spin-polarized current into the channel 5 of the transistor 1, ii. The magnetization 16 of the drain 2 is set in a predetermined orientation, for example, parallel. A bias is applied between the source and drain 2, 3 so as to cause the flow of spin-polarised charge carriers 20 to flow from the source 2 to the drain 3, under the gate 7. The spin of the charge carriers 20 is parallel with the magnetization 15 of the source 2.

Referring in particular to Figure 7a, if no bias is applied to the gate 7, then the charge carriers 20 pass freely, without affecting spin polarisation of the current, to the drain contact. The current will be high indicating that the device is in a low-resistance state.

Referring in particular to Figure 7b, if a suitable bias is applied to the gate 7, then spin polarised carriers flowing from the source to the drain experience a 1800 rotation in spin polarisation due to the effective magnetic field induced by the Rashba spin-orbit interaction in the channel. These carriers experience spin scattering as they pass through the drain contact and so the device will be in a high-resistance state.

Suitable values of gate bias and pulse times can be found by routine experiment.

Second spin electronic device 1.1? structure

Referring to Figure 8, a second multiferroic-based spin device 1, i2 is shown which is capable of operating as a spin transistor and as non-volatile memory.

The second multiferroic-based spin device 1, i2 is the same as the first spin device 1, ii shown in Figure 1 except that an extended gate electrode 7’ and an extended gate dielectric 8’ are used. The gate electrode 7’ and gate dielectric 8’ run over the source 3. A first portion 6’ of the gate electrode 7’ and gate dielectric 8’ which lies over the channel 5 but not the drain 3 provides a gate structure. A second portion 21’ of the gate electrode 7’ and gate dielectric 8’ which lies over the drain 3 provides a drain polarization structure. Thus, in the second multiferroic-based spin device i2, the drain contact 3 and gate electrode 7’ are arranged to generate an out-of-plane (or “vertical”) electric fields, in particular, along the z-axis.

The gate electrode 7’ and gate dielectric 8’ may also be extended to run over the source 2.

Referring to Figure 9,10,11a, 11b, 12a, 12b, 13a and 13b, the second device 1, i2 can be configured and operated in substantially the same way as the first device 1, ii.

Third spin electronic device 1, i? structure

Referring to Figure 14, a third multiferroic-based spin device 1, i3 is shown which is capable of operating as a spin transistor and as non-volatile memory.

The third multiferroic-based spin device 1, i3 is the same as the first spin device 1, h shown in Figure 1 except that the device includes a dedicated drain polarization structure 21 comprising a gate electrode 22 and a gate dielectric 23 disposed on an upper surface of the drain 3.

Thus, in the third multiferroic-based spin device 1, l3, the polarization structure 21 is arranged to generate an out-of-plane (or “vertical”) electric fields, in particular, along the z-axis. A dedicated source polarization structure (not shown) may also be provided on the source 2.

Referring to Figure 15,16,17a, 17b, 18a, 18b, 19a and 19b, the third device 1, i3 can be configured and operated in substantially the same way as the first device 1, ii.

Fabrication of the spin device

Referring to Figure 20, a method of fabricating a multiferroic-based spin device 1 (Figure 1, 8 & 14) is shown.

Referring also to Figures 1 and 2, buffer layer(s) 11 are deposited, for example using MBE, on a substrate 12 (step Si). A semiconductor layer (not shown) is deposited, for example using MBE, on the uppermost buffer layer 13 (step S2). The semiconductor layer is patterned, for example by defining an etch mask using lithography and etching unwanted regions of the semiconductor layer using a dry etch, to define the channel 5 (step S3). A suitable seed layer (not shown) is deposited, for example using ALD (step S4). A layer of multiferroic material is deposited, for example using MBE or ALD, on the seed layer (step S5). The multiferroic layer is patterned, for example by defining an etch mask using lithography and etching unwanted regions of the multiferroic layer using a dry etch, to define the source and drain contacts 2, 3 (step S6). A dielectric layer (not shown) is deposited, for example using CVD (step S7). A layer of conductive material (such as polysilicon) is deposited, for example using CVD, on the dielectric layer (step S8). The conductive layer and the dielectric layer are patterned, for example by defining an etch mask using lithography and etching unwanted regions of the layers using suitable wet or dry etches, to define the gate structures and/or polarizations structures (step S9).

Modifications

It will be appreciated that many modifications may be made to the embodiments hereinbefore described.

For example, the channel need not be formed from germanium but maybe formed from a group IV elemental semiconductor materials, such as silicon or carbon (in the form of diamond), a two-dimensional group IV elemental material, such as graphene, germanene and silicene, or group IV-based compound semiconductor materials, such as silicon germanium (SiGe), silicon carbon (SixCi-x), silicon carbide (SiC), germanium carbide (GeC), silicon germanium carbide (SiGeC), germanium tin (GeSn) or germanium tin silicide (GeSnSi) or group III-V based semiconductor materials such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), gallium antimonide (GaSb), indium antimonide (InSb), indium arsenide (InAs), indium phosphide (InP), gallium phosphide (GaP) and other compound semiconductors comprising elements from groups III and V of the periodic table, or group II-VI based semiconductor materials such as mercury selenide (HgSe), mercury telluride (HgTe), cadmium selenide (CdSe) and cadmium telluride (CdTe).

The majority carriers in the channel maybe electrons.

Claims (19)

  1. Claims
    1. A spin electronic device comprising: source and drain electrodes; a semiconductor channel running between the source and drain electrodes; and a gate electrode structure interposed between the source and drain electrodes comprising a gate electrode and a gate dielectric; wherein the source and drain electrodes are multiferroic such that each electrode has a respective magnetization and polarization which are magnetoelectrically coupled.
  2. 2. A device according to claim 1, wherein the source and/or drain electrode(s) comprise a multiferroic material.
  3. 3. A device according to claim 1 or 2, wherein the multiferroic material is bismuth manganese oxide.
  4. 4. A device according to claim 1 or 2, wherein the multiferroic material is cobalt chromium oxide.
  5. 5. A device according to any preceding claim, wherein the source and/or drain electrode(s) comprise a synthetic multiferroic.
  6. 6. A device according to any preceding claim further comprising: a seed layer interposed between the semiconductor channel and a source or drain electrode.
  7. 7. A device according to claim 6, wherein the seed layer comprises an oxide.
  8. 8. A device according to claim any preceding claim, wherein the semiconductor channel comprises a group IV elemental semiconductor material or a group IV-based compound semiconductor material.
  9. 9. A device according to claim 8, wherein the semiconductor channel comprises germanium. io. A device according to any preceding claim, wherein the semiconductor channel comprises a quantum well. n. A device according to any preceding claim, wherein the semiconductor channel is under strain.
  10. 12. A device according to any preceding claim, wherein the device comprises: a substrate; and a buffer layer structure interposed between the substrate and the semiconductor channel.
  11. 13. A device according to any preceding claim, wherein the gate electrode and/or gate dielectric are not magnetically polarisable.
  12. 14. A device according to any preceding claim, wherein the gate electrode and/or gate dielectric are not electrically polarisable.
  13. 15. A device according to any preceding claim, wherein the gate electrode and/or gate dielectric are not multiferroic.
  14. 16. Apparatus comprising: a spin device according to any preceding claim; and a set of bias sources arranged to controllably apply a respective bias to the source, drain and gate electrodes.
  15. 17. Apparatus according to claim 16, wherein, in a first bias configuration, the bias sources apply biases such that an electric field is applied to the source or drain electrode so as to orientate polarization in the source or drain electrode in a first predetermined direction.
  16. 18. Apparatus according to claim 16 or 17, wherein, in a second bias configuration, the bias sources apply biases such that an electric field is applied to the source or drain electrode so as to orientate polarization in the source or drain electrode in a second predetermined direction, which is different from the first predetermined direction.
  17. 19. Apparatus according to any one of claims 16 to 18, further comprising: a current meter wherein, in a third bias configuration, the bias sources apply biases such that a current is driven between the source and drain contact and wherein the current meter is arranged to measure the current.
  18. 20. Apparatus according to any one of claims 16 to 19, wherein, in a fourth bias configuration, the bias sources apply biases such that a spin current is driven between the source and drain contact and a first gate bias does not substantially modulate spin in the spin current.
  19. 21. Apparatus according to any one of claims 16 to 20, wherein, in a fifth bias configuration, the bias sources apply biases such that a spin current is driven between the source and drain contact and a second gate bias substantially modulates spin in the spin current.
GB1704985.9A 2017-03-29 2017-03-29 Spin electronic device Pending GB2560936A (en)

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