WO2010073211A1

WO2010073211A1 - Multibit multiferroic memory element

Info

Publication number: WO2010073211A1
Application number: PCT/IB2009/055875
Authority: WO
Inventors: Siegfried F. Karg; Gerhard Ingmar Meijer
Original assignee: International Business Machines Corporation
Priority date: 2008-12-23
Filing date: 2009-12-21
Publication date: 2010-07-01
Also published as: CN102246237A; EP2374132A1; TW201027715A; CN102246237B

Abstract

A memory element (1) comprises a source electrode (12), a drain electrode (13) and a gate, wherein a memory state of the memory element is switchable by application of a voltage signal to the gate, and is readable by measuring a current-voltage characteristic between the source electrode and the drain electrode across a channel region (21). The gate comprises a multiferroic material (15). A magnetic field may be generated in the channel region (21). According to the invention, the multiferroic material (15) comprises a first and a second stable domain (15.1; 15.2), wherein a switching state of the first domain is set by application of a first write voltage signal between a gate electrode and the source electrode, and a switching state of the second domain is set by application of a second write voltage signal between the gate electrode and the drain electrode, whereby the memory element is a 2-bit memory element.

Description

MULTIBIT MULTIFERROIC MEMORY ELEMENT

FIELD OF THE INVENTION

The invention is in the field of memory elements (memory cells) for memories.

BACKGROUND OF THE INVENTION

Memories are major classes of integrated circuits. They are mainly used as solid-state stand-alone and embedded memories. The most widely used memory technologies are DRAM, SRAM, Floating gate (Flash), and MRAM. None of these existing technologies can be integrated with high areal density and provide at the same time non- volatile and fast operation. Especially, Flash is too slow for many embedded applications, SRAM and DRAM loose their memory state when disconnected from the power supply, and SRAM and MRAM can only be manufactured with a limited areal density. Highest densities are achieved in NROM, MirrorBit, and SONOS flash memories, which comprise a charge trapping layer to store two physically separated charge packets. The high programming voltage of Flash complicates integration with CMOS circuitry. Accordingly, it is desired to provide a memory element overcoming the drawbacks of prior art memory cells. Especially, it is desired to provide a memory element that is non- volatile, and in addition makes a high areal density and/or fast operation possible.

SUMMARY OF THE INVENTION

The memory element according to a first aspect of the present invention comprises a source-drain-gate functional structure i.e. a source electrode and a drain electrode between which a channel region is established, where charge carriers can flow between the source and the drain electrode, dependent on the application of an electrical signal to the gate.

Preferably, the channel region may comprise a semiconductor or insulating material (thus comprise at most comparably few free charge carriers) or be doped to be conducting; the channel region may be configured in many different ways; preferably, the channel region provides an electrical resistance large enough for allowing for independent voltage signals between the gate on the one hand and the source or the drain electrode on the other hand.

The gate comprises a multiferroic material, thus a material with at least two coupled order parameters. The multiferroic material generally is in an arrangement between a gate electrode on the one hand and the source and the drain electrode on the other hand. The memory element is formed as a 2-bit memory element. This is achieved by the multiferroic material being caused to comprise two stable domains wherein a switching state of the first domain is set by application of a first "write" voltage signal between the gate electrode and the source electrode, and a switching state of the second domain is set by application of a second "write" voltage signal between the gate electrode and the drain electrode. The domains may optionally be physically separated, for example by a fissure or a domain wall pinning structure between them. Alternatively or in addition, in a preferred embodiment of the invention, they may arise by the "write" signal control being such as to always apply the first and second write pulses simultaneously, even if only one of the two bits is to be overwritten.

Because the two domains enable that two bits are stored in a single memory element, the areal density is increased compared to prior art memory elements. While compared to a similar memory element with only one domain, the contacts etc., which use up the better part of the area on the device, are equal, the memory density is increased by a factor 2, because the memory element by the simple measure proposed in accordance with the invention comprises two information bits.

Ferroelectric materials possess a spontaneous polarization that is stable and can be switched hysteretically by an applied electric field. Ferromagnetic materials possess a spontaneous magnetization that is stable and can be switched by an applied magnetic field. Multiferroic materials possess simultaneous ferroelectric and magnetic ordering. These two order parameters are coupled. There exist ferromagnetic, ferrimagnetic, and antiferromagnetic multiferroics.

The multiferroic material domains are therefore programmable by application a first and second voltage signal, for example by the application of an electric field pulse, across it. Due to the coupling of the ferromagnetic, ferrimagnetic or antiferromagnetic order parameter to the ferroelectric order parameter, this causes this ferromagnetic, ferrimagnetic or antiferromagnetic order parameter to be programmed, too. For the "read" operation, a spin valve effect may be used. The spin valve effect causes an electrical resistance between the source electrode and the drain electrode (for an electrical current flowing in at least one direction between the source and drain electrode) to be switchable. To this end, both, the drain electrode and the source electrode preferably are ferromagnetic or at least comprise a ferromagnetic element. Also, the multiferroic material is capable of influencing the relative orientation of the magnetic moments of charge carriers flowing to the source or drain electrode and of a magnetization of the source or drain electrode. This can be done in one of two possible ways:

- As a first alternative, the multiferroic material can cause a state dependent magnetic field to be produced, the magnetic field influencing the magnetic moments of the charge carrier flowing in the conducting channel. A switching of the ferromagnetic/ferrimagnetic/antiferromagnetic order parameter thus causes the switching of a magnetic field in the channel region. This can be done by:

o A gate ferromagnet (or potentially gate ferrimagnet; in this text the definition "gate ferromagnet", "ferromagnet", "ferromagnetic layer" or "ferromagnetic material" include according ferrimagnetic material, the skilled person knowing that the function of the ferromagnet can also be fulfilled by a ferrimagnet) being coupled to the multiferroic material; the gate ferromagnet is then in immediate contact (direct contact with nothing in between) with the multiferroic material,

o The then ferromagnetic (or ferrimagnetic) multiferroic material itself producing a large enough stray field. As a second alternative, a switching of the ferromagnetic/ferrimagnetic/antiferromagnetic order parameter of the first and second domains may cause the switching of the magnetization direction of the source and drain electrode, respectively, so that the spin valve changes the preferred orientation for charge carrier magnetic moments. To this end, the source electrode is directly exchange coupled to the first domain of the multiferroic material, and the drain electrode is exchange coupled to the second domain. This is combined with a means for causing the magnetic moments of the charge carriers flowing to the source and drain electrodes to have a pre-defined preferred orientation, for example a fixed magnetization (pinned) gate ferromagnet, the stray field of which orients the magnetic moments of the charge carriers when they flow in the channel region.

In either case, the "read" process for the first and second bit relies on the generation of a current causing charge carriers to flow to the source electrode and to the drain electrode, respectively. Preferably, this is achieved by a "read" pulse applied between the source and the drain electrode. In the most general case, the above- mentioned spin valve effect causes the voltage-current characteristics to be polarity dependent. Depending on the polarity of the "read" pulse, the first or the second bit is read. This also implies that the memory element is not of a fully random access type, because the first and second bits may not be read simultaneously. However, bits of different memory elements in a memory may be read simultaneously.

The memory element features the advantage of being non- volatile, because the ferroelectric and magnetic order parameters of the multiferroic material are nonvolatile. Due to its non-volatile character, low power consumption can be expected. Also, changing the ferroelectric polarization of a multiferroic element is an inherently fast process (50 ps-1 ns). The memory element according to the invention therefore has a significant programming speed advantage compared to flash memory (1 μs).

Further, the memory element can be implemented in a simple, small unit cell (having a required space of 6F² only, in a 1 -Transistor structure without any additional resistors or capacitors) and thus is suitable for integration with higher areal density than prior art memory elements. Also, it scales well when going to smaller cells, because it does not comprise any capacitors.

Yet a further advantage of the memory element - especially compared to MRAM - is a reduced write energy of about 10^"15 J/bit versus 10^"11 J/bit for MRAM.

An even further advantage of the memory element - especially compared to Flash - is a lower programming voltage of around 1 V versus 15 V for Flash.

Possible ferromagnetic multiferroics include Boracite (N13B7O13I), Perovskites like BiMnO₃ and TbMnO₃, and Sulfates such as CdCr₂S₄. In these currently known materials, however, the coupled order parameters are non-zero at low temperatures only, so that the memory element and devices made therewith are primarily suited for special applications where cooled devices are acceptable.

In a preferred embodiment, the element comprises a cooling device. Preferably, the operating temperature for the memory element provided by such cooling device is below 100 Kelvin. According to an especially preferred embodiment, however, the multiferroic material is a multiferroic antiferromagnet coupled (in general by exchange bias coupling) to either a gate ferromagnet or to the drain and the source electrode and pinning the same. This 'ferromagnet pinning' embodiment firstly features the advantage that known antiferromagnetic multiferroics are more temperature stable than their ferromagnetic counterparts. Also, there is the special advantage that the superparamagnetic limit (i.e. the size at which the magnetic anisotropy of a magnetic layer in a cell becomes comparable to kT, where k is Boltzmann's constant and T is the absolute temperature, so that the magnetization becomes unstable below that limit) is not an issue in antiferromagnets, so that the cell may be designed to be comparably smaller and still be stable.

An example of a useable antiferromagnetic multiferroic material is BiFeO₃

The memory element according to the invention can be used both, as memory cell of a pure memory device and as memory cell in a logic circuit also including programmable logics. Examples of such logic circuits into which a memory device according to the invention can be incorporated can be found in the European patent application EP 08104301.0. Due to the approach according to the invention, therefore, memory and logic circuits can be integrated without additional mask steps, which provides a considerable manufacturing cost advantage for such integrated circuits.

BRIEF DESCRIPTION OF THE DRAWINGS In the following, embodiments of the invention will be described referring to accompanying drawings. The drawings are all schematic and not to scale. In the drawings, same reference numerals refer to same or corresponding elements.

Fig. 1 shows a cross section through a first embodiment of a memory element according to the invention;

Fig. 2 depicts a cross section through a second, alternative embodiment of a memory element according to the invention;

Figs 3a through 6c show "write" and "read" steps of the four logic states assumed by a device of Fig. 2,

Fig. 7 depicts a cross section through yet another, alternative embodiment of a memory element according to the invention;

Figs 8a through l ie show "write" and "read" steps of the four logic states assumed by a device of Fig. 7; and

Fig. 12 shows an even further embodiment of a memory element according to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the ferromagnetic materials of depicted elements in the figures, filled arrows generally indicate fixed magnetizations. Fixed magnetizations may be magnetizations that are pinned in some way, that have coercive field that is higher than the sum of effective fields enacting on them during normal operation or that are otherwise influenced not to change a magnetization direction during normal operation of the programming element. Open arrows indicate magnetizations that are switchable by the programming voltage pulse signals. In the case of pinned magnetizations, the pinning layer is not shown in the figures. Pinning of ferromagnetic layers is well-known to the person skilled in the field of magnetic memories, for example from MRAM memories. Pinning is not further discussed here.

The memory element 1 depicted in Figure 1 comprises, on a substrate 3, a source electrode 12 and a drain electrode 13, both of a ferromagnetic electrically conducting material, for example of a Cobalt alloy or Permalloy (an FeNiCo alloy). Between the source and drain electrodes, a conducting channel 21 is formed, for example by a n- doped region in the substrate or in any other suitable manner; the conducting channel may but need not comprise the same material as the substrate 3.

The substrate may be any known or other suitable substrate, such as a semiconducting substrate, for example Gallium Arsenide or Silicon. The substrate in the depicted embodiment is contacted by a reference voltage contact, namely a ground contact 8 (or "bulk" contact). As is known in the art, there may be a (not depicted) connection between for example the source electrode 12 and the ground contact 8, so that the former is always on ground potential (or an other reference potential as the case may be), or, as an alternative, a connection between the gate electrode and the ground contact, as discussed further below. The memory element 1 further comprises a gate that includes a gate electrode 17, a ferromagnetic layer 14 - of any ferromagnetic electrically conducting material - , and an antiferromagnetic multiferroic layer 15 sandwiched between the gate electrode and the ferromagnetic layer. The ferromagnetic layer is insulated by a dielectric layer 16 from the source and drain electrodes 12, 13 and from the conducting channel 21.

The multiferroic layer 15 is exchange coupled to the ferromagnetic layer. Because of this, a switching of the order parameter of the multiferroic layer also causes a switching of the order parameter (thus of the magnetization) of the ferromagnetic layer in immediate vicinity.

The coupled bilayer consisting of the multiferroic layer 15 and the ferromagnetic layer 14 is now such that it can comprise two stable domains 14.1, 15.1; 14.2, 15.2. The dashed line 18 in the figure depicts a potential separation line between the first domainl4.1, 15.1 and the second domain 14.2, 15.2.

The domains can be separated by a purposefully added structure at a fixed position. Such structure acts to locally split the bilayer or that acts as a domain wall pinning means. The structure may for example be a microslit at the position of the dashed line, or an impurity or similar pinning a domain wall.

As an alternative to the purposefully added structure, the bilayer may also lack any purposefully added structure to separate the domains. The domains then may be in a not pre-defined position and may simply arise by different order parameter directions being caused in vicinity to the drain and the source electrodes, respectively. In any case the bilayer has to be an anisotropy and a size large enough to maintain two domains after fields have been switched off, i.e. the two domains in any case have to be stable so that the memory element is non- volatile. The coexistence of two magnetically stable domains has been predicted and observed in structures down to a very small size of for example 20 nm or even less. The lower limit for the size of the bilayer for the domains to be stable depends on the anisotropy which in turn depends on the material composition of the bilayer.

A "write" voltage signal for the two domains may be applied between the gate electrode 17 and the source electrode 12 or the drain electrode 13, respectively. To this end, the thicknesses and conductivities of the multiferroic layer 15 and the dielectric layer 16 are preferably adapted to each other so that the voltage drop across the multiferroic layer corresponds to a large portion (preferably at least half) of the voltage between the gate electrode and the source or drain electrode.

By the write voltage signal, the spontaneous polarization of the multiferroic material may be switched between four states, two states for each domain, as is explained in more detail referring to Figures 3a-6c. Because the material is multiferroic, the switching of the spontaneous polarization also switches the according antiferromagnetic order parameter, for example by reversing the sequence of "up" and "down" magnetized layers in the multiferroic material. The ferromagnetic layer 14 - being immediately adjacent to the multiferroic layer 15 - is exchange coupled to the multiferroic layer. Due to this, the switching of the ferroelectric spontaneous polarization in the domains 15.1, 15.2 of the multiferroic material has the effect of also switching the magnetization direction of the ferromagnetic layer domains 14.1, 14.2. The memory element 1 design of Figure 2 is different from the one of Figure 1 in that the sequence of the multiferroic layer 15 and of the ferromagnetic layer 14 is reversed. The multiferroic layer 15 is sandwiched between the ferromagnetic layer 14 on one side and the conducting channel 21 and the source and drain electrodes on the other side. The dielectric layer 16 then is not necessary any more, because the multiferroic material 15, in contrast to most of the commonly used ferromagnetic materials, is electrically insulating.

Also, a separate gate electrode layer 17 is optional and not shown in the drawings, since the ferromagnetic layer 14 itself can optionally serve as the gate electrode.

Also the configuration of Figure 2, the write voltage signal may be applied between the gate electrode (ferromagnetic layer 14) and the source electrode 12 or the drain electrode 13. In contrast to the configuration of Figure 1, almost the entire voltage drop will be across the multiferroic layer, so that the required write voltage is reduced compared to the latter. Thus, the configuration of Fig. 2 is generally preferred.

By means of Figures 3a-6c, the working principle, thus the "write" and "read" operations, of the memory element according to the invention is explained, referring to the embodiment of Fig. 2.

Figures 3a, 4a, 5a, and 6a represent the "write" process for the four different states assumed by the two-bit element. In each "write" process, "write voltage signals are applied simultaneously between the gate electrode 14 on the one hand and the source electrode 12 and the drain electrode 13 on the other hand- also if only one of the two bits (thus only one of the two domains) is reversed. For example, the gate electrode 14 may be kept at OV potential during each "write" process, whereas the source and drain electrodes are both independently supplied with 1 V or -IV "write" pulses.

Fig. 3a corresponds to the "up-up" state, for example attained by applying -IV pulses to both, the source electrode and the drain electrode. Fig. 3b represents the "up- down" state (-1V applied to the source electrode, +1V to the drain electrode), Fig 3c to the "down-up" state (+1V/-1V), and Fig. 3d to the "down-down" state (+1V/+1V).

Of course, in this the quantities of the applied voltages and their absolute polarities are mere examples.

The memory element according to the invention is not fully random access. The first and second information bit of each memory element can not be read simultaneously. Figures 3b, 4b, 5b, and 6b show the "read" process for the first information bit of the "up-up", "up-down", "down-up", and "down-down"-states, respectively, and Figures 3c, 4c, 5c, and 6c show the "read" process for the second information bit thereof.

The "read" process is based on a spin valve effect. For a "read" operation, a small "read" voltage pulse of desired polarity, depending on whether the first or the second bit is read, is applied between the source and drain electrodes. This causes charge carriers (n-type charge carriers or p-type charge carriers, depending on the conductivity type) to flow in the channel region between the source and drain electrodes. The charge carriers are symbolized by arrows within the channel region 21 in the figures, the arrows representing the charge carriers' magnetic moments.

The block arrows illustrate the direction of their flow. When transiting the channel region 21, the charge carriers are subject to a magnetic field generated by the ferromagnetic layer 14. This magnetic field determines the orientation of the charge carriers' magnetic moments if they are subject to the magnetic field.

The domain in vicinity of the electrode the charge carriers flow to (the source electrode in the "read" process for the first bit, and the drain electrode in the "read" process for the second bit) therefore defines the orientation of the charge carriers when upon their entry into the ferromagnetic source or drain electrode, respectively.

Two situations are to be distinguished. If the magnetic moments of the majority of the charge carriers is oriented parallel to the magnetization of the source or drain electrode they flow to, the charge carriers with the maintained magnetic moment can easily enter the electrode electrode. In contrast thereto if the charge carriers are oriented to be antiparallel to the electrode the flow to, they encounter an energy barrier (for example for having to again flip their magnetic moment) when entering the electrode material. This energy barrier effect - called 'spin valve' effect - is in nature similar to the effect that is also responsible for 'giant magnetoresistance' or 'tunneling magnetoresistance' and is as such described in literature.

A low energy barrier (the respective first or second bit is "up" or "1") is encountered in the "read" configurations of Figs. 3b, 3c, 4b, and 5c. In Figures 4c, 5b, 6b, and 6c a high energy barrier (the respective first or second bit is "down" or "0") is sensed.

The source electrode 12 (for the first bit) and the drain electrode 13 (for the second bit), therefore, act as ferromagnetic detectors for the orientation of the domain in their proximity. The stray field of the ferromagnetic layer 14 influences the charge carriers before they flow into the respective electrode. The (polarity dependent) current- voltage characteristic is almost independent of the ferromagnetic domain orientation of the other domain, i.e. of the domain that is more remote from the detecting electrode. This is illustrated by the small arrows in Figures 4b, 4c, 5b, and 5c. For example, in the configuration of Fig. 4b, the magnetic moments of the charge carriers coming from the drain electrode 13 are initially polarized parallel to the drain electrode's magnetization, because the drain electrode is ferromagnetic. Under the influence of the second domain, they partly or completely flip before they enter the region where they are influenced by the first domain's magnetic field, that causes the magnetic moments to flip back.

As a remark, depending on the electronic structure of the source and drain electrode ferromagnetic materials, the spin valve effect in some cases may work the other way round: i.e. charge carriers with magnetic moments parallel may then encounter a higher energy barrier then the antiparallel magnetic moment charge carriers. This may for example be the case if the drain electrode material comprises a so-called 'strong' ferromagnet where there are no free states for charge carriers in the majority band. For the purpose of the invention, however, the effect remains the same: it is only important that there is some difference in the current-voltage characteristic between the situation with charge carriers with magnetic moments parallel to the magnetization of the electrode they flow to, and with charge carriers with magnetic moments antiparallel thereto. In other words, the polarity dependent voltage-current characteristics (for example the current arising for a certain applied "read" voltage or the voltage required to achieve a certain "read current") is not equal for the two different relative orientations of the charge carrier magnetic moments and the magnetization of the electrode they flow to.

Figure 7 illustrates an alternative embodiment, where the gate ferromagnetic layer 34 has a fixed magnetization, and magnetization of the source and drain electrodes

12, 13 is exchange coupled to the multiferroic layer 15 and can be flipped by flipping the latter's order parameter. In this configuration, the source and drain electrodes need to be in direct physical contact with the multiferroic layer. The direct contact between the multiferroic material 15 and the pinned gate ferromagnet 34, however, is not a requirement. Rather, a layer or several layers of an other material/of other materials (not shown) may be present between the pinned gate ferromagnet 34 and the multiferroic material 15, for example a metallic, non-magnetic layer for preventing an exchange coupling between the gate ferromagnet 34 and the multiferroic material 15.

Figures 8a-llc show the write process and the read process for an embodiment as shown in Fig. 7. The representation is analogous to the one of Figs. 3a-6c.

Similarly to the embodiments of Figures 1 and 2, in the "write" process, the orientations of the first and second domains 15.1, 15.2 of the multiferroic material may be set by "write" voltage signals between the gate electrode 34 and the source and drain electrode 12, 13, respectively, as illustrated in Figures 8a, 9a, 10a, and 11a. Due to the exchange coupling, in this way the magnetizations of the source and drain electrode are set (programmed) too, similarly to the programming of the domains 14.1, 14.2 in the embodiment of Figs. 1 and 2.

In the "read" process, the charge carrier magnetic moments when injected into the channel region 21 are polarized in accordance with the polarization of the electrode they are injected from, but after transition through the channel region 21 are always polarized in accordance with the magnetic field of the gate electrode (upwards in the depicted configuration). Thus, the embodiment of Fig. 7 in the read process produces charge carriers that have a pre-defined magnetic moment orientation when they flow to the source or drain electrode 12, 13. Due to the spin valve effect described above, therefore, the charge carrier flow serves as detecting means for detecting the magnetization orientation of the source or drain electrode. Figure 12, finally, depicts yet another embodiment. In this embodiment, the multiferroic layer 35 with the two domains 35.1, 35.2 is a multiferroic ferromagnet. It therefore directly produces a magnetic field, and the additional ferromagnetic layer 14 is not necessary. The working principle is otherwise identical to the one of the embodiment of Fig. 2.

Further variants of the invention are possible. For example in embodiments with switchable source and drain electrode magnetizations, the magnetic field defining the magnetic moment orientation of charge carriers flowing to the source and drain electrodes need not belong to the gate. Rather, instead also a "global" magnetic field source generating the desired uniform magnetic field for a plurality of memory elements may be used, for example a common ferromagnetic coating, or an external ferromagnet, an electromagnet etc.

Claims

WHAT IS CLAIMED IS:

1. A memory element comprising a source electrode (12), a drain electrode (13) and a gate, wherein a memory state of the memory element is switchable by application of a voltage signal to the gate, and is readable by measuring a current-voltage characteristic between the source electrode and the drain electrode across a channel region (21), wherein the gate comprises a multiferroic material (15, 35), and wherein the memory element comprises means for generating a magnetic field in the channel region (21), characterized in that the multiferroic material (15, 35) comprises a first and a second stable domain (15.1, 35.1; 15.2, 35.2), wherein a switching state of the first domain is set by application of a first write voltage signal between a gate electrode and the source electrode, and a switching state of the second domain is set by application of a second write voltage signal between the gate electrode and the drain electrode, whereby the memory element is a 2-bit memory element.

2. The memory element according to claim 1, wherein the source electrode (12) and the drain electrode (13) are ferromagnetic, the memory element further comprising read means configured to sense spin valve energy barriers for charge carriers flowing to the source electrode and for charge carriers flowing to the drain electrode.

3. The memory element according to claim 2, wherein the read means are configured to apply a read voltage signal of a first polarity between the source electrode and the drain electrode to read a first data bit, and to apply a read voltage signal of a second, opposite polarity between the source electrode and the drain electrode to read a second data bit.

4. The memory element according to any one of the previous claims, wherein the multiferroic material is a multiferroic antiferromagnet.

The memory element according to claim 4, wherein the gate further comprises a gate ferromagnet (14) or ferrimagnet capable of causing a magnetic field to be present in the channel region, the gate ferromagnet or ferrimagnet being coupled to the multiferroic antiferromagnet, a magnetization direction of a first and a second domain of the gate ferromagnet or ferrimagnet being switchable by the coupling to the multiferroic antiferromagnet due to the application of the first and second write voltage signals.

6. The memory element according to claim 5, wherein the multiferroic antiferromagnet (15) is arranged between the gate ferromagnet (14) or ferrimagnet and the channel region (21).

7. The memory element according to claim 6, wherein the multiferroic antiferromagnet (15) is arranged immediately adjacent to the channel region (21).

8. The memory element according to claim 4, wherein magnetizations of the drain electrode and of the source electrode are coupled to the and first and second domain, respectively and are switchable by the coupling to the multiferroic material due to the application of the first and second write voltage signals, respectively.

9. The memory element according to any one of claims 1-3, wherein the multiferroic material is a multiferroic ferromagnet (35) or ferrimagnet capable of causing a magnetic field to be present in the channel region (21).

10. A memory device comprising a plurality of memory elements (1) according to any one of the preceding claims serving as memory cells, and further comprising contacts for applying electrical signals individually to the gates of the memory elements and contacts for reading out by determining a current- voltage characteristic between the source and the drain electrode of an individually addressed memory element in a polarity dependent manner.