JP4415146B2 - Field effect transistor using ferromagnetic semiconductor and nonvolatile memory using the same - Google Patents

Description

  The present invention relates to a novel metal-insulator-semiconductor field effect transistor using a ferromagnetic semiconductor in a channel region, and high performance of a large capacity nonvolatile memory using the same.

  In recent years, the development of a highly information-oriented society, also called the IT revolution, continues to make further progress through “mobile devices”. It is recognized that this large demand for “mobile devices” can be the key to the future semiconductor industry. To meet this demand, conventional methods such as higher speed, lower power consumption, and higher capacity of semiconductor integrated circuits have been proposed. In addition to the improvement in performance, it is necessary to meet new requirements such as information non-volatility. In response to such a demand, a new memory device that combines a ferromagnetic storage technology excellent in nonvolatile high-density recording and a semiconductor integrated electronics technology has attracted attention.

  This device is called a magnetic random access memory (hereinafter referred to as “MRAM”), and has a structure in which a thin insulating tunnel barrier is sandwiched between ferromagnetic electrodes (magnetic tunnel junction; (Hereinafter referred to as “MTJ”) is used as the memory element (see, for example, Non-Patent Document 1).

  The MTJ has a tunneling magnetoresistance (hereinafter referred to as “TMR”) effect in which the tunnel resistance varies depending on the relative magnetization direction between the ferromagnetic electrodes. It becomes possible to electrically detect the magnetization state. Therefore, the presence of MTJ makes it possible to ideally incorporate information storage technology using ferromagnetic material into semiconductor integrated electronics.

  Hereinafter, a general memory cell using the MTJ will be described with reference to FIG. As shown in FIG. 7, a general MRAM memory cell includes a 1-bit memory cell including one MTJ 101 and one MOS transistor 103. The MTJ 101 is a tunnel junction that includes a first ferromagnetic material 105, a second ferromagnetic material 107, and a tunnel barrier 111 that is provided between the first ferromagnetic material 105 and the second ferromagnetic material 107.

  The source (S) 103 a of the MOS transistor 103 is grounded (GND), and the drain (D) 103 b is connected to one ferromagnetic electrode 107 of the MTJ 101. The other ferromagnetic electrode 105 of the MTJ 101 is connected to the bit line (BL), and the rewrite word line (WL (P)) is electrically connected to the MTJ 101 and other wirings and an insulating film directly above or immediately below the MTJ. It is arranged so as to cross the bit line (BL) in a state of being electrically insulated. The read word line WL (R) is connected to the gate electrode (G) 103 c of the MOS transistor 103.

  In ferromagnetic materials, the magnetization direction can be kept non-volatile, so in MTJ101, binary information can be made non-volatile by setting the relative magnetization state between the ferromagnetic electrodes to parallel magnetization or anti-parallel magnetization. Can be remembered. In MTJ 101, the tunnel resistance differs depending on the relative magnetization state between the two ferromagnetic electrodes 105 and 107 due to the TMR effect. Therefore, if a tunnel resistance corresponding to a magnetization state such as parallel magnetization or antiparallel magnetization is used, the magnetization state in the MTJ 101 can be electrically detected.

  Information is rewritten by changing the coercive force of the two ferromagnetic electrodes in the MTJ 101 or by fixing the magnetization direction of one of the ferromagnetic electrodes 105 or 107 and reducing the coercive force. Alternatively, it is performed by reversing the magnetization of a ferromagnetic electrode whose magnetization direction is not fixed. Hereinafter, a ferromagnetic electrode that performs magnetization reversal is referred to as a free layer, and a ferromagnetic electrode that does not perform magnetization reversal is referred to as a pinned layer. More specifically, a current is supplied to each of the bit line (BL) and the rewrite word line (WL (P)) intersecting on the selected cell, and the selected magnetic field is selected by a synthesized magnetic field induced by these currents. Only the magnetization state of the MTJ 101 in the memory cell is changed to parallel magnetization or antiparallel magnetization. At this time, in order to prevent magnetization reversal of unselected cells having the same bit line or rewrite word line as the selected cell, and to prevent magnetization reversal of the MTJ 101 of the unselected cell by a magnetic field from only one wiring, Set the current value to flow through the wiring.

  To read information, a voltage is applied to the read word line connected to the selected cell to turn on the MOS transistor 103, and then a read drive current is passed to the MTJ 101 via the bit line (BL). In MTJ101, the tunnel resistance in the magnetization state of parallel magnetization or antiparallel magnetization differs depending on the TMR effect, and therefore the magnetization state can be determined by detecting a voltage drop in MTJ101 due to the read drive current (see Non-Patent Document 1). ).

K. Inomata, "Present and future of magnetic RAM technology", IEICE Trans. Electron. Vol.E84-C, pp740-746, 2001.

The memory cell using the MTJ has a problem to be solved which will be described below.
1) Issues related to writing In the MRAM, information is rewritten by changing the magnetization state of the MTJ by using a magnetic field induced by the current of the bit line and the word line. Even in MRAM, high density integration and high performance can be realized by miniaturization of devices as in the case of normal semiconductor integrated memory. However, if MTJ is miniaturized, the demagnetizing field of the ferromagnetic electrode increases and magnetization reversal is achieved. The required magnetic field strength is increased. Therefore, the current required for rewriting increases. This increase in current is quite large, and as the wiring is miniaturized, even if the aspect ratio is increased, the reliability of the wiring cannot be secured. When the coercive force of the ferromagnetic material is reduced, the strength of the magnetic field necessary for rewriting decreases, but a fatal problem such as erroneous writing occurs. Therefore, there is a need for a new method that can easily rewrite magnetization information with a magnetic field generated at a low current value without reducing the coercivity of the ferromagnetic material.

2) Problems related to reading The MTJ takes a binary resistance value corresponding to whether the magnetization state of the ferromagnetic electrodes facing each other through the tunnel barrier is parallel magnetization or anti-parallel magnetization. In order to detect this binary information with high sensitivity, it is necessary to increase the ratio of the output signal between the two magnetization states. A large drive current is required to read information at a high speed, but the TMR ratio in the MTJ depends strongly on the bias voltage applied to the MTJ, and decreases rapidly with the bias voltage. Therefore, when a large current is used for reading, the voltage drop at the MTJ increases and the TMR ratio decreases. Therefore, the TMR ratio has a trade-off relationship with high-speed operation. Therefore, it is necessary to devise a technique that does not reduce the TMR ratio even if a large voltage drop occurs in the MTJ.

3) Issues related to integration density The memory cell of the MRAM has a simple structure, and the ferromagnetic material used in the MTJ can be miniaturized to a nanoscale size, so that it is a memory suitable for high-density integration. In order to achieve a high degree of integration of several gigabits or more, the channel length of the MOS transistor is expected to be smaller than about 0.1 μm. However, even if the MTJ is miniaturized in accordance with such a fine transistor, the arrangement of multilayer wiring such as a word line for rewriting rules the reduction of the cell area, and it is difficult to achieve high density integration. Therefore, a memory cell having a simpler structure is required.

  It is an object of the present invention to reduce the voltage for writing and reading in a memory and increase the degree of integration when integrated.

  In the present invention, the above-described problems are solved by using a metal-ferromagnetic-semiconductor field effect transistor (MISFET) in which a channel region is made of a ferromagnetic semiconductor.

1) Writing In a ferromagnetic semiconductor, if the number of carriers in the ferromagnetic semiconductor layer is decreased by applying an electric field, it is possible to change the magnetism from ferromagnetic to paramagnetic (referred to as field effect magnetic control). ). In the memory cell using the MISFET of the present invention, a voltage is applied to the source and drain to change the ferromagnetic semiconductor layer in the channel region from ferromagnetic to paramagnetic (or a state having a sufficiently small coercive force), and this state is changed. Magnetization reversal is carried out while keeping it. Therefore, writing can be performed with a magnetic field sufficiently smaller than the coercive force in the ferromagnetic state.

2) Reading In the MISFET of the present invention, the TMR (magnetic field) between the ferromagnetic channel and the ferromagnetic source (or the ferromagnetic channel and the ferromagnetic drain, or the ferromagnetic channel and the ferromagnetic source, and the ferromagnetic channel and the ferromagnetic drain). The magnetization state is read by the resistance effect. The bias applied between the source and the drain is divided at the source junction and the drain junction. Therefore, in the device according to the present invention, the ratio of the output signal (drain current) between the parallel magnetization and the antiparallel magnetization has a bias dependency weaker than that of a normal MTJ. In this device, it is possible to apply a bias for reading larger than MTJ. In particular, when the source is made of a ferromagnetic material, this bias dependency is remarkably weakened.

3) High-density integration In the MISFET of the present invention, one MISFET constitutes a 1-bit memory cell. Therefore, a very simple configuration can be achieved for the wiring. Since the memory cell can be configured by the simplest one transistor and three wirings, a layout suitable for miniaturization can be easily configured.

  In addition, the conventional MRAM memory cell has a structure of 1MTJ, 1 transistor, 4 wirings (see FIG. 7), and the cell area is shared by adjacent cells due to the presence of the MTJ and the word line for writing. However, in the memory cell of the present invention, a cell structure in which adjacent cells share a source is also possible.

  According to the MISFET of the present invention, the transistor has characteristics as a transistor capable of controlling the drain current by the gate voltage, and has the transfer conductance of the ferromagnetic channel and the ferromagnetic source (or both the ferromagnetic drain or the ferromagnetic source and the ferromagnetic drain). It also has a characteristic characteristic that it can be controlled by the relative magnetization direction. Therefore, binary information can be stored according to the relative magnetization direction, and the relative magnetization direction can be electrically detected. In addition, if the magnetic control based on the electric field effect of a channel made of a ferromagnetic semiconductor is used, the current required for rewriting information can be greatly reduced. Therefore, the MISFET can constitute a high-performance nonvolatile memory cell suitable for high-density integration.

  Hereinafter, a MISFET and a nonvolatile memory using the same according to a first embodiment of the present invention will be described with reference to the drawings. First, a configuration example of the MISFET according to the present embodiment will be described.

  FIG. 1A is a cross-sectional structure diagram of a MISFET according to the present embodiment, which uses a ferromagnetic semiconductor for a channel. The MISFET 1 according to the present embodiment uses a MIS structure having a stacked structure of a gate electrode 15, a gate insulating film 11, and a ferromagnetic semiconductor 5 as a gate structure. The source 7a or drain 7b (or both of the source 7a / drain 7b) made of a ferromagnetic material and the ferromagnetic semiconductor 5 are configured to form a Schottky junction.

  When a Schottky junction between a ferromagnetic material and a ferromagnetic semiconductor is used only on one side, a normal Schottky junction with a nonmagnetic metal is used on the other side. Further, impurities are appropriately introduced into the junction interfaces 5a and 5b (FIG. 1 (a)) between the channel region (5) and the ferromagnetic source 7a or the ferromagnetic drain 7b (or both are ferromagnetic). Or an intrinsic semiconductor may be inserted.

The ferromagnetic semiconductor 5 of the channel is formed on the semiconductor substrate 3 (or on the semiconductor layer thereon) or by introducing magnetic atoms into the semiconductor by a thermal diffusion method or an ion implantation method. Can do. The ferromagnetic material used for the source 7a or the drain 7b (or both 7a and 7b) can be an ordinary ferromagnetic metal (Fe, Ni, Co, permalloy, etc.), but a magnetic element is metallic (high concentration). Doped (added) ferromagnetic semiconductors (Ga _1-x M _x As, Si _1-x M _x , Ge _1-x M _x (M is a magnetic element)) and half-metal ferromagnets (CrO ₂ , Fe ₃ O ₄ , Heusler alloy, etc.) can also be used. Such a ferromagnetic source 7a and drain 7b may be grown or deposited on the ferromagnetic semiconductor layer 5, but are formed by introducing magnetic atoms into the semiconductor by thermal diffusion or ion implantation. Also good. As the MIS structure, a MOS structure in which the surface of the ferromagnetic semiconductor layer 5 is oxidized can be used, or an insulator layer can be grown or deposited on the ferromagnetic semiconductor layer 5 to form a MIS structure. As the substrate 3, a normal semiconductor substrate or SOI substrate can be used.

  The MISFET 1 according to the present embodiment operates in a storage channel type in which carriers of the same conductivity type as the ferromagnetic semiconductor 5 in the channel region are carriers. Although both electrons and holes can be used as carriers, an explanation will be given below with reference to a band structure by taking an n-channel device as an example. A p-channel device can be similarly configured and operated.

FIG. 1B is a diagram showing a band structure in the vicinity of the channel region of the n-channel device. FIG. 1B illustrates the case where a conductive ferromagnetic material is used for the source, but as described above, a structure using a ferromagnetic material for the drain or both of the source and the drain may be used. It indicated dotted line and the solid line and the n-type ferromagnetic semiconductor layer 5 shown in the source 7a and the drain 7b, represents the Fermi energy E _F. E _G represents the band gap of the ferromagnetic semiconductor. E _C and E _V represent the bottom of the conduction band and the top of the valence band of the ferromagnetic semiconductor 5, respectively. Although the ferromagnetic semiconductor layer 5 in the channel region in FIG. 1B is not degenerated, a magnetic element may be doped to such an extent that it degenerates. By the Schottky junction of the source 7a and the drain 7b, a Schottky barrier whose barrier height is φ _S and φ _D respectively is generated on the conduction band side.

  The arrows 4a and 4b shown on the Fermi energy of the channel made of the ferromagnetic material source 7a and the ferromagnetic semiconductor 5 indicate the direction of the majority spins in the respective regions, and the direction of the arrow is upward. If it is, it is up spin, and if it is downward, it is down spin. Also, the display of minority spins is omitted. Further, the nonmagnetic conductor (7b) is expressed by simultaneously indicating upward and downward arrows. Hereinafter, the source 7a (or drain) made of a ferromagnetic material may be referred to as a ferromagnetic source 7a (or ferromagnetic drain). Similarly, a channel region made of a ferromagnetic semiconductor may be simply referred to as a ferromagnetic channel.

  Next, the operation principle of the MISFET according to this embodiment will be described with reference to the drawings. The channel region 5 of the MISFET according to the present embodiment is made of a ferromagnetic semiconductor. Regarding the source 7a and the drain 7b, as described above, when (i) only the source is ferromagnetic, (ii) drain When only the ferromagnet is used, (iii) when both the source and the drain are ferromagnets, there are three combinations. Hereinafter, the principle of operation of an n-channel device having a ferromagnetic source will be described, but the above-described other configurations and p-channel devices also operate in the same manner.

  Further, the case where the relative magnetization direction of the ferromagnetic channel with respect to the ferromagnetic source is the same direction is referred to as parallel magnetization, and the case where these relative magnetization directions are opposite to each other is referred to as anti-parallel magnetization. The channel length of the MISFET is sufficiently shorter than the spin relaxation distance, and the rush bar effect induced by the gate voltage is ignored.

FIG. 2A shows a band structure when the gate-source bias V _{GS is set} to V _GS = 0 and the bias V _DS (> 0) is applied between the drain and the source. By applying V _DS , a potential shape as shown in FIG. 2A is formed. The Schottky junction of the drain 7b is forward biased, and the Schottky junction of the ferromagnetic source 7a is reverse biased. At this time, the width d of the depletion layer due to the Schottky junction of the ferromagnetic source 7a is sufficiently thick, and almost no injection of electrons from the ferromagnetic source 7a toward the channel region 5 occurs due to the tunnel effect (d is the ferromagnetic source 7a). This is the distance until the Fermi level of 7a intersects the band edge of the Schottky barrier on the source side).

Further, since the Schottky junction on the source side is reverse-biased, the current is about the reverse saturation current of the Schottky junction derived from the thermal conduction of the conduction carrier of the ferromagnetic source 7a over the barrier of height φ _S. However, this current can be made sufficiently small by selecting φ _S appropriately. Accordingly, in the state where V _GS = 0, the MISFET is cut off (off). This blocking state does not depend on the relative magnetization direction between the ferromagnetic source 7a and the ferromagnetic channel 5.

When a bias V _GS (> 0) is applied to the gate electrode 15, the electric field near the Schottky barrier φ _S on the ferromagnetic source 7a side is strengthened by the lines of electric force from the gate electrode 15 toward the ferromagnetic source 7a. As shown in b), the barrier width of the Schottky barrier decreases (d ′ in the figure). Accordingly, electrons in the ferromagnetic source 7a are transmitted through the potential barrier φ _S by the tunnel effect and injected into the channel 5 immediately below the gate insulating film 11. The injected electrons are attracted to the insulator / semiconductor interface by V _{GS and} are transported to the drain 7b by V _DS to form a drain current. At this time, the transmission (mutual) conductance and drain current of the MISFET 1 according to the present embodiment depend on the relative magnetization directions of the ferromagnetic source 7 a and the ferromagnetic channel 5.

In the tunnel from the ferromagnetic source 7a to the ferromagnetic channel 5 via the electron Schottky barrier φ _S , an effect similar to the tunnel magnetoresistance (TMR) effect works. This will be referred to as the TMR effect). Therefore, the tunnel resistance is small when the ferromagnetic source 7a and the ferromagnetic channel 5 are in parallel magnetization, and the tunnel resistance is large in the case of antiparallel magnetization. Even when the influence of the TMR effect is small, electrons having a spin polarization depending on the spin polarizability of the source ferromagnet can be injected from the ferromagnetic source 7a. For this reason, electrons cause spin-dependent scattering in the ferromagnetic channel 5 due to the relative magnetization state of the ferromagnetic channel 5 and the ferromagnetic source 7a. Therefore, due to the TMR effect at the time of tunnel injection and spin-dependent scattering in the ferromagnetic channel 5, the relative magnetization directions of the ferromagnetic source 7a and the ferromagnetic channel 5 change, and the transfer conductance changes.

  As shown in FIG. 2B, if the ferromagnetic source 7a and the ferromagnetic channel 5 are in parallel magnetization, the transfer conductance increases and the drain current also increases. However, as shown in FIG. If the magnetic source 7a and the ferromagnetic channel 5 are antiparallel, the transfer conductance is small and the drain current is small.

As described above, in the MISFET according to the present embodiment, the transfer conductance can be controlled by the relative magnetization directions of the ferromagnetic source 7a and the ferromagnetic channel 5 even under the same bias. Further, in the MISFET according to the present embodiment, since the number of conductive carriers injected into the channel can be controlled by V _GS , the drain current can be controlled by V _GS . Therefore, the MISFET according to the present embodiment has a property as a normal transistor capable of controlling the drain current by the gate voltage, and can control the transfer conductance by the relative magnetization directions of the ferromagnetic source and the ferromagnetic channel.

  Next, the nonvolatile memory using the MISFET according to the present embodiment will be described. The MISFET according to the present embodiment stores binary information by setting the relative magnetization of the ferromagnetic source and the ferromagnetic channel to parallel magnetization or antiparallel magnetization, and outputs (drain) corresponding to these magnetization states. A nonvolatile memory that detects the magnetization state from the current) can be realized. Since only one MISFET according to this embodiment can be used to form a 1-bit memory cell, high-density integration is possible. In addition, the magnetic control by the field effect of the ferromagnetic semiconductor used for the channel is positively utilized, and the rewriting current, which is a big problem in the conventional MRAM, can be reduced.

  Hereinafter, the operation principle of this memory will be described using an n-channel MISFET having a ferromagnetic source, but the MISFET and the p-channel device having other configurations described above operate in the same manner. Here, the ferromagnetic source is a pinned layer with a fixed magnetization direction, and the ferromagnetic channel is a free layer that changes the magnetization direction.

  FIG. 3 is a diagram showing a cell configuration of the nonvolatile memory according to the embodiment of the present invention. As shown in FIG. 3, the memory cell according to the present embodiment includes a memory cell 21 including one MISFET according to the above-described embodiment, a word line (WL) 23, a bit line (BL) 25, and a ground line (GND) 27. And have. In the rewrite operation of the nonvolatile memory cell, a relatively large bias is applied to the bit line 25 and the ground line 27 connected to the selected cell 21 (to the substrate potential or the gate electrode), and the ferromagnetism in the channel region disappears. Then, the number of carriers is reduced or depleted until it becomes paramagnetic (or a state in which the coercive force is sufficiently small). As shown in FIG. 3, if the bit line 25 and the ground line 27 are arranged so as to be orthogonal to each other, a bias is applied to the source and drain only in the selected cell 21 and connected to the bit line 25 or the ground line 27. In other unselected cells, only the drain or source is biased. Therefore, if the bias is set to such an extent that ferromagnetism cannot be annihilated over the entire channel with only one bias (for example, only the region not reaching the center from the source, or the region not reaching the center from the drain). Only so that the magnetization information of the unselected cells is not lost.

  In this state, a relatively small current is applied to the word line 23, a magnetic field is induced to change the magnetization direction of the paramagnetic channel, and then the bias between the bit line 25 and the ground line 27 is turned off. Rewrite the information by returning the channel to the ferromagnetic state.

FIG. 4 is a diagram showing an example of the rewriting operation on the magnetization curve. First, it is assumed that the channel magnetization is at point A on the magnetization curve. Consider rewriting from this state to point E in FIG. First, a bias is applied to the bit line and the ground line from the state of point A to change the ferromagnetism of the selected cell to paramagnetism. At this time, the magnetization of the channel becomes the B point. Next, if a current is passed through the word line connected to the gate electrode directly above the channel, even if the strength of the magnetic field induced by this current is equal to or less than the coercive force H _C of the channel region in the ferromagnetic state, as shown in FIG. Magnetization can be reversed like point C. Next, the channel region returns to the ferromagnetic state if the source and drain biases are turned off while a current is applied to the gate electrode. At this time, the magnetization direction in the paramagnetic state is preserved as indicated by point D in FIG. When the current of the word line is cut from this state, the rewriting is completed (point E in FIG. 4).

In the memory cell according to the present embodiment, since the magnetization can be reversed by a magnetic field smaller than the coercive force H _C of the channel region in the ferromagnetic state, the current required for the magnetization reversal can be greatly reduced. In the information read operation, a bias necessary for normal transistor operation is applied to the selected cell, and the relative magnetization state of the ferromagnetic source and the ferromagnetic channel is detected based on the magnitude of the drain current. Since the word lines and the bit lines are arranged orthogonally, the stored contents can be read only for the selected cell. In the read operation, a necessary bias may be applied by precharging.

  Next, a non-volatile memory according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a diagram showing a cell configuration example of a nonvolatile memory that is a nonvolatile memory according to the present embodiment and can collectively erase / rewrite a plurality of memory cells. Similar to the cell configuration example shown in FIG. 3, the memory cell according to the present embodiment has a MISFET 31, a word line (WL) 33, a bit line (BL) 35, and a ground line (GND) 37. ing. However, the bit line 35 and the ground line 37 are arranged in parallel to each other. In this cell structure, the magnetization information of all the MISFETs 31 connected to the selected bit line 35 can be simultaneously erased and rewritten.

  In the rewriting operation, a bias is applied to the selected bit line 35 and the ground line 37 connected to the MISFET 31 connected thereto, and the channels of all the MISFETs 31 connected to the bit line 35 and the ground line 37 are made ferromagnetic. To paramagnetism (or a state in which the coercive force is sufficiently small). Next, a current in a direction corresponding to the rewrite content is supplied to each word line 33 connected to the gates of these MISFETs 31 to change the magnetization direction of the paramagnetic channel. Finally, by turning off the bias of the bit line 35 and the ground line 37, the channels of the respective MISFETs 31 are returned to ferromagnetic and information is rewritten. In the memory cell according to the present embodiment, by using the small current required for rewriting each memory cell, a rewrite current is simultaneously applied to a large number of word lines. It is possible to rewrite the magnetization information of the MISFET at the same time. Therefore, the rewriting speed can be increased. In the above cell configuration, since the word line and the bit line are arranged orthogonally, if a normal transistor bias is applied to the selected cell, the magnetization of the selected cell is based on the drain current corresponding to the magnetization state. The state can be detected. In addition, even with the cell configuration shown in FIG. 5, reading by precharge is possible.

  Next, a memory cell according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 6 shows a memory cell structure according to the present embodiment, which is a composite structure of a gate electrode and a word line using a yoke structure. FIG. 6 is a cross-sectional view of the MISFET as viewed from the source side. As shown in FIG. 6, the memory cell structure according to the present embodiment includes a stacked structure having a channel region 41, a gate oxide film 43, a gate electrode 45, and a word line 47, and a stacked structure of the stacked structure. Among them, a yoke 51 that covers at least the word line 47 and the gate 45 from the outside is provided.

  The yoke 51 is made of a material having high magnetic permeability. If the structure shown in FIG. 6 is used, the magnetic field by the current of the word line 47 can be effectively applied to the ferromagnetic channel 41. Therefore, the write current can be further reduced. The structure shown in FIG. 6 can be applied to the cell configuration shown in FIGS.

  As mentioned above, although it demonstrated along embodiment of this invention, this invention is not restrict | limited to these. It will be apparent to those skilled in the art that other various modifications, improvements, and combinations are possible.

  The present invention can achieve high integration and low power consumption in a nonvolatile memory device, and can be applied as a nonvolatile memory device for various electronic devices, particularly portable electronic devices.

FIG. 1A is a cross-sectional structure diagram of a MISFET according to the first embodiment of the present invention, which uses a channel region made of a ferromagnetic semiconductor and a source made of a ferromagnetic material. FIG. 1B is a diagram showing a band structure in the vicinity of the channel region of the n-channel device. FIGS. 2A to 2C are energy band diagrams showing the operation principle of the MISFET according to the present embodiment. It is a figure which shows the cell structure of the non-volatile memory by embodiment of this invention. It is the figure which showed on the magnetization curve the example of rewriting operation | movement of the non-volatile memory by embodiment of this invention. It is a figure which shows the cell structure of the non-volatile memory by the 2nd Embodiment of this invention. FIG. 10 is a diagram showing a composite structure of a gate electrode and a word line using a yoke structure, which is a memory cell structure according to a third embodiment of the present invention. It is sectional drawing which shows the structural example of the memory cell of a general MRAM.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... MISFET, 5 ... Ferromagnetic semiconductor, 7a ... Source, 7b ... Drain, 11 ... Gate insulating film, 15 ... Gate electrode.

Claims (40)

A source for injecting carriers,
A drain for receiving injected carriers;
A channel provided between the source and the drain and having a Schottky barrier at each junction interface between the source and the drain;
A transistor comprising a gate electrode provided with an insulator layer interposed in the channel,
By forming the channel with a ferromagnetic semiconductor and at least one of the source and the drain with a ferromagnetic material, at least one Schottky barrier in each junction interface between the channel and the source and the drain Is constituted by a junction interface between a ferromagnetic semiconductor and a ferromagnetic material,
The ferromagnetic semiconductor of the channel is ferromagnetic when no voltage is applied to the gate electrode, and becomes paramagnetic when a voltage is applied to the gate electrode or has a holding power as compared to when no voltage is applied to the gate electrode. Low ferromagnetism,
The Schottky barrier due to the bonding interface of the ferromagnetic semiconductor and the ferromagnet, by ferromagnetic semiconductor of the magnetization direction of the channel Waru strange, transistors, characterized in that the barrier height is changed.   2. The transistor according to claim 1, wherein the channel made of a ferromagnetic semiconductor is formed by a ferromagnetic semiconductor layer in which a magnetic element is added to a semiconductor.   3. The transistor according to claim 1, wherein the ferromagnetic material constituting the source or the drain is either a ferromagnetic metal or a half metal ferromagnetic material. 3. The transistor according to claim 1, wherein the ferromagnetic material constituting the source or the drain includes a ferromagnetic semiconductor obtained by adding a magnetic element to a semiconductor. The ferromagnetic material constituting the source or the drain is a ferromagnetic metal or a ferromagnetic semiconductor obtained by adding a magnetic element to a semiconductor, and the junction interface between the source or drain and the channel made of the ferromagnetic semiconductor is 3. The transistor according to claim 1, wherein the energy barrier due to the band discontinuity forms a Schottky barrier.   The metal spin band of the half metal ferromagnet forms a Schottky barrier at the junction interface when the source or drain ferromagnet is a half metal ferromagnet. 4. The transistor according to 3.   When only one of the source and the drain is a ferromagnetic material, the junction between the other of the source and the drain, which is a non-magnetic material, and the channel made of a ferromagnetic semiconductor is 2. The transistor according to claim 1, wherein the transistor is a Schottky junction.   8. The transistor according to claim 1, further comprising a semiconductor layer at a junction interface between the channel made of a ferromagnetic semiconductor and the source or the drain made of a ferromagnetic material.   9. The transistor according to claim 8, wherein the semiconductor layer at the junction interface is formed of a semiconductor layer to which an impurity is added or an intrinsic semiconductor layer.   The insulator layer interposed between the channel and the gate electrode is provided on a ferromagnetic semiconductor layer constituting the channel, according to any one of claims 1 to 9. Transistor.   The transistor according to claim 10, wherein the insulator layer includes a surface oxide layer formed by oxidizing the surface of the ferromagnetic semiconductor layer.   The transistor according to claim 11, wherein the insulator layer is an insulator layer grown or deposited on the ferromagnetic semiconductor layer.   13. The transistor according to claim 1, wherein the transistor is formed on a semiconductor substrate or an SOI (Silicon on Insulator) substrate.   The source or the drain made of a ferromagnetic material is formed by growing or depositing a ferromagnetic material on a ferromagnetic semiconductor layer, semiconductor layer, or semiconductor substrate, or by introducing a magnetic element into the semiconductor layer or semiconductor substrate. The transistor according to claim 1, wherein the transistor is a transistor.   15. The channel according to claim 1, wherein the channel made of a ferromagnetic semiconductor layer is formed by growth or deposition on the semiconductor layer, or introduction of a magnetic element into the semiconductor layer. Transistor. The Schottky barrier due to the bonding interface of the ferromagnetic semiconductor and the ferromagnet, the magnetization direction of the channel of a ferromagnetic semiconductor, by applying a bias between the drain and the source, the source or the drain made of a ferromagnetic material The magnetization direction can be controlled to parallel magnetization or anti-parallel magnetization according to the magnetic field generated by the current flowing through the wiring connected to the gate electrode, and cannot be controlled only by bias application between the drain and gate. The transistor according to claim 1. 2. The channel made of a ferromagnetic semiconductor is a free layer that changes the direction of magnetization, and the source or the drain made of a ferromagnetic material is a pinned layer having a fixed direction of magnetization. Transistor. In the case wherein the carrier is an electron, the Schottky barrier is generated in the conduction band side, if the carrier is the hole is up to 17 the preceding claims, characterized in that said Schottky barrier is generated in the valence band side The transistor according to any one of the above items. In a state where no voltage is applied between said gate electrode source, from the source by the Schottky barrier to 18 claim 1, wherein the injection of carriers by tunneling to the channel is suppressed The transistor according to any one of the above items. The carrier reaches the channel by tunneling the Schottky barrier at a junction between the source and the channel by applying a voltage between the gate electrode and the source. Item 19. The transistor according to any one of Items 1 to 18 . In the case where the drain is a ferromagnetic body, the drain that is a ferromagnetic body is compared with the case where the relative magnetization state of the drain that is a ferromagnetic body and the channel that is a ferromagnetic semiconductor is a parallel magnetization. and when the relative magnetization configuration between the channel which is a ferromagnetic semiconductor is antiparallel magnetization, claim 1, characterized in that the drain current decreases according to any one of up to 20 Transistor. In the case where the source is a ferromagnetic material, the source that is a ferromagnetic material is compared with the case where the relative magnetization state of the source that is a ferromagnetic material and the channel that is a ferromagnetic semiconductor is a parallel magnetization. and when the relative magnetization configuration between the channel which is a ferromagnetic semiconductor is antiparallel magnetization, claim 1, characterized in that the drain current decreases according to any one of up to 20 Transistor. The transfer conductance can be controlled by the relative magnetization direction of the source or drain as a ferromagnetic material and the channel as a ferromagnetic semiconductor under the same drain-gate bias. 23. The transistor according to any one of 1 to 22 . When the source or drain that is a ferromagnetic material and the channel that is a ferromagnetic semiconductor have parallel magnetization, the voltage is determined between the source and the drain by a voltage applied to the gate electrode. 24. A transistor according to any one of claims 1 to 23 , having a threshold defined as a gate voltage that causes a current. Using one transistor according to any one of claims 1 to 24, information on the relative magnetization direction between the channel which is the source or the drain and the ferromagnetic semiconductor is ferromagnetic Store and detect information stored in the transistor based on the transfer conductance of the transistor depending on the relative magnetization orientation of the source or drain as a ferromagnetic material and the channel as a ferromagnetic semiconductor A transistor characterized by: A bias is applied between the drain and the source so that the ferromagnetic semiconductor is in a paramagnetic state or a ferromagnetic state with a sufficiently small coercive force, and the paramagnetic state or coercive force is reduced. by applying a magnetic field current flowing through the wiring connected to the gate electrode to the ferromagnetic semiconductor of the previous SL channel state that is sufficiently small ferromagnetic state occurs, becomes paramagnetic state the ferromagnetic the magnetization direction of the semiconductor layer after changing depending on the orientation of the magnetic field, in a state of applying the magnetic field, by a switching Turkey the application of a bias between the drain and the source, the ferromagnetic semiconductor coercivity 26. The transistor according to claim 25 , wherein information is rewritten by returning to a large ferromagnetic state. One transistor according to any one of claims 1 to 26 ;
A first wiring connected to the gate electrode;
A second wiring connected to the drain;
And a third wiring for grounding the source. Between the second wiring and the third wiring, the degree to which the ferromagnetic semiconductor of the channel changes from a ferromagnetic state having a large coercive force to a paramagnetic state or a ferromagnetic state having a sufficiently small coercive force In this state, a current that induces a magnetic field that can change the magnetization direction of the ferromagnetic semiconductor of the channel is caused to flow through the first wiring, and the magnetization direction of the ferromagnetic semiconductor of the channel is changed to the current. in response to the orientation in the state of being parallel magnetization or antiparallel magnetization to the magnetization direction of the ferromagnetic material of the source or the drain, by a switching benzalkonium the bias, the ferromagnetic semiconductor of the magnetization information of the channel 28. The memory element according to claim 27 , further comprising information rewriting means for rewriting. With respect to the third wiring, the second wiring and the third wiring when a predetermined voltage is applied to the second wiring and the first wiring, respectively. 28. The memory element according to claim 27 , wherein information is read based on a magnitude of a current flowing therebetween. A plurality of transistors according to any one of claims 1 to 26 ;
A ground line commonly grounding the sources of the transistors of the first group selected from the plurality of transistors;
A word line commonly connecting the gates of the transistors of the first group;
Bit lines that are individually connected to the drains of the transistors of the first group and that commonly connect the drains of corresponding transistors of the second group including transistors that do not belong to the first group;
A memory circuit. A plurality of transistors according to any one of claims 1 to 26 ;
A ground line for commonly grounding the sources of the transistors belonging to the transistor row composed of the plurality of transistors extending in one direction;
A word line commonly connecting the gates of the transistors belonging to the transistor row;
A memory circuit having a plurality of bit lines individually connecting drains of the transistors belonging to the transistor row; A plurality of transistors according to any one of claims 1 to 26 arranged in a matrix,
A plurality of ground lines commonly connecting the sources of the plurality of transistors arranged in a column direction;
A plurality of word lines commonly connecting gate electrodes of the plurality of transistors arranged in a column direction;
A memory circuit having a plurality of bit lines commonly connecting drains of the transistors arranged in a row direction. A bias is applied between the bit line and the ground line so that the ferromagnetic semiconductor of the channel changes from a ferromagnetic state having a large coercive force to a paramagnetic state or a ferromagnetic state having a sufficiently small coercive force. In this state, a current that induces a magnetic field that can change the magnetization direction of the ferromagnetic semiconductor of the channel is caused to flow through the word line, and the magnetization direction of the ferromagnetic semiconductor of the channel is changed according to the direction of the current. the state of parallel magnetization or antiparallel magnetization to the magnetization direction of the ferromagnetic material of the source or the drain, by a switching Turkey said bias information of the select transistor selected by said word lines and said bit lines The memory circuit according to any one of claims 30 to 32, further comprising information rewriting means for rewriting the data. Based on the magnitude of current flowing between the bit line and the ground line when a predetermined voltage is applied to the bit line and the word line with respect to the ground line, The memory circuit according to any one of claims 30 to 32 , wherein information of a selection transistor selected by the word line and the bit line is read. A plurality of transistors according to any one of claims 1 to 26 ;
A ground line commonly grounding the sources of the transistors of the first group selected from the plurality of transistors;
A bit line commonly connecting drains of the transistors of the first group;
A word line that is individually connected to the gates of the transistors of the first group and that commonly connects the gates of the corresponding transistors of the second group including transistors that do not belong to the first group;
A memory circuit. A plurality of transistors according to any one of claims 1 to 26 ;
A ground line for commonly grounding the sources of the transistors belonging to a transistor row composed of a plurality of the transistors extending in one direction;
A bit line commonly connecting the drains of the transistors belonging to the transistor row;
A memory circuit having a plurality of word lines individually connecting gates of the transistors belonging to the transistor row; A plurality of transistors according to any one of claims 1 to 26 arranged in a matrix,
A plurality of grounding wires for commonly connecting the sources of the plurality of transistors arranged in a row direction;
A plurality of word lines commonly connecting gate electrodes of the plurality of transistors arranged in a column direction;
A memory circuit having a plurality of bit lines commonly connecting drains of the transistors arranged in a row direction. A bias is applied between the bit line and the ground line so that the ferromagnetic semiconductor of the channel changes from a ferromagnetic state having a large coercive force to a paramagnetic state or a ferromagnetic state having a sufficiently small coercive force. In this state, a current that induces a magnetic field that can change the magnetization direction of the ferromagnetic semiconductor of the channel is caused to flow through the word line, and the magnetization direction of the ferromagnetic semiconductor of the channel is changed according to the direction of the current. the state of parallel magnetization or antiparallel magnetization to the magnetization direction of the ferromagnetic material of the source or the drain, by a switching benzalkonium the bias, the information of the transistors selected by said ground line and said bit line memory circuit according to any one of claims 35 to 37, characterized in that it comprises information rewriting means for rewriting. Based on the magnitude of current flowing between the bit line and the ground line when a predetermined voltage is applied to the bit line and the word line with respect to the ground line, The memory circuit according to any one of claims 35 to 37 , wherein information of a selection transistor selected by the word line and the bit line is read. 40. The storage element or storage circuit according to any one of claims 27 to 39 , further comprising a yoke surrounding an outer periphery of the word line or the first wiring.

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