CN108899058A - The operating method of the four state ferroelectric transistor memories based on source drain regions otherness iron electric polarization - Google Patents
The operating method of the four state ferroelectric transistor memories based on source drain regions otherness iron electric polarization Download PDFInfo
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- 230000010287 polarization Effects 0.000 title claims abstract description 40
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 title claims abstract description 18
- 230000015654 memory Effects 0.000 title claims abstract description 12
- 238000011017 operating method Methods 0.000 title claims abstract description 10
- 229910052742 iron Inorganic materials 0.000 title claims abstract description 9
- 239000008186 active pharmaceutical agent Substances 0.000 claims description 35
- 239000004065 semiconductor Substances 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 230000005621 ferroelectricity Effects 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229920000642 polymer Polymers 0.000 claims description 5
- 230000033228 biological regulation Effects 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 abstract description 10
- 238000003860 storage Methods 0.000 abstract description 10
- 238000005516 engineering process Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 18
- 238000000034 method Methods 0.000 description 16
- 230000006870 function Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- MVPPADPHJFYWMZ-UHFFFAOYSA-N chlorobenzene Chemical compound ClC1=CC=CC=C1 MVPPADPHJFYWMZ-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- BGTOWKSIORTVQH-UHFFFAOYSA-N cyclopentanone Chemical compound O=C1CCCC1 BGTOWKSIORTVQH-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000012456 homogeneous solution Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
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- 150000002927 oxygen compounds Chemical class 0.000 description 1
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/223—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using MOS with ferroelectric gate insulating film
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2273—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2275—Writing or programming circuits or methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
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Abstract
The invention belongs to information technology field, the operating method of specially a kind of four state ferroelectric transistor memories based on source drain regions otherness iron electric polarization.The present invention makes source/drain region ferroelectric film have the iron electric polarization orientation not depended on mutually, can realize four storage states on a ferroelectric transistor by the combination of source/drain region iron electric polarization state by applying different voltage in three interpolar of source and drain grid.The present invention can directly make its memory capacity double in the case where not changing ferroelectric transistor memory preparation process and structure, applied widely.
Description
Technical field
The invention belongs to information technology fields, and in particular to the behaviour of the ferroelectric transistor memory with four state store functions
Make method.
Background technique
Nonvolatile ferroelectric transistorized memory utilizes the residual electric polarization characteristic of ferroelectric material layer, and regulation closes on semiconductor channel
The electric conductivity of layer.In traditional ferroelectric transistor write/erase operating process, the polarization shape of source area and drain region ferroelectric film
State is consistent, to only be able to achieve binary states (i.e. 0 and 1 state) store function.The present invention will pass through source and drain during regulation write/erase
The voltage value of three interpolar of grid realizes the otherness orientation polarization of source area and drain region ferroelectric film, thus in ferroelectric transistor
Realize four state store functions.
Summary of the invention
The purpose of the present invention is to provide the read-writes that one kind can realize four storage states on a ferroelectric transistor
Operating method, to improve the storage density of device.
Ferroelectric layer is carried out polarization operations by traditional Nonvolatile ferroelectric transistor as a whole, can only be realized in this way
Two kinds of storage states.Actually ferroelectric layer can be divided into different regions, the polarized state of different zones according to source-drain electrode
There are Different Effects to channel layer source-drain current.The source electrode and its near zone for generally producing carrier, which play source-drain current, to be determined
Property effect, but drain and its near zone effect it is equally very important.Therefore, the present invention utilizes this principle, proposes one kind
The operating method of new ferroelectric transistor information write/erase can realize four storage states on a ferroelectric transistor
Write-in, erasing and read operation, to improve the storage density of device.
Write-in, erasing and the read operation side provided by the invention that four storage states are realized on a ferroelectric transistor
Method is the source drain regions otherness iron electric polarization based on ferroelectric transistor.The structure of ferroelectric transistor is：A pair of of source/drain
Pole, a grid, a semiconductor channel layer and a ferroelectric layer.The method of the present invention by source and drain grid three extremely on apply electricity
The Reasonable Regulation And Control of pressure, realization polarize to the otherness of source area and drain region ferroelectric film, are combined by different polarized states,
Four state accessing operations are realized on one ferroelectric crystal tube device.
The ferroelectric transistor structure of bottom gate top contact as shown in connection with fig. 1 illustrates four state information write/erase of ferroelectric transistor
Method.It is emphasized that also just being meaned to previous already existing Information State while new Information State write-in
Erasing operation.That is, the writing process simultaneous erasing operation of four state information.Thus in following elaboration, only emphasize
To the writing process of specific four states information, without emphasizing the erasing operation to specific write-in state.When device operation, source electrode ground connection.
In order to illustrate conveniently, the upward polarized state of electric dipole differently- oriented directivity in ferroelectric film is defined as positive polarization state；And work as ferroelectricity
The downward polarized state of electric dipole differently- oriented directivity is defined as negative polarization state in film.Grid and voltage between source electrodes are denoted as VGS, grid
V is denoted as with leakage voltage across polesGD, voltage is denoted as V between drain-sourceDS, electric current is denoted as I between drain-sourceDS, electric current is denoted as I between grid sourceGS, ferroelectric film
Coercive voltage is VC.The write/erase operation that four states store information is as follows：
Write state 1：VGSAnd VGDFor positive value and it is all larger than VCWhen, the equal positive polarization of the ferroelectric film of source area and drain region, such as Fig. 2
(a) shown in.For the write state, if channel layer is p-type semiconductor material, transistor is in OFF state, IDSFor minimum value；
If channel layer is n-type semiconductor, transistor is in ON state, IDSFor maximum value.The write-in of state 1, also means that
To the erasing operation of previous already present write-in state；
Write state 2：VGSAnd VGDFor negative value and the two absolute value is all larger than VCWhen, the ferroelectric film of source area and drain region is negative
Polarization, as shown in Fig. 2 (b).For the write state, if channel layer is p-type semiconductor material, transistor is in ON state,
IDSFor maximum value；If channel layer is n-type semiconductor, transistor is in OFF state, IDSFor minimum value.State 2 is write
Enter, also means that the erasing operation to previous already present write-in state；
Write state 3：VGSFor positive value and it is greater than VC, while VGDFor negative value and its absolute value is greater than VCWhen, source area ferroelectric film is just
Polarization, and drain region ferroelectric film negative polarization, as shown in Fig. 2 (c).I at this timeDSCurrent value is between OFF state (minimum value) and on-state current
It is worth between (maximum value).When practical operation, positive V can also be applied on the basis of write state 2DSAnd VGSValue, and guarantee VDS<
VC<VGS, the write-in of state 3 is realized with this.The write-in of state 3 also means that the erasing to previous already present write-in state
Operation；
Write state 4：VGDFor positive value and it is greater than VC, while VGSFor negative value and its absolute value is greater than VCWhen, source area ferroelectric film is negative
Polarization, and drain region ferroelectric film positive polarization, as shown in Fig. 2 (d).I at this timeDSCurrent value is between OFF state (minimum value) and on-state current
It is worth between (maximum value).When practical operation, negative V can also be applied on the basis of write state 1DSAnd VGSValue, and guarantee | VDS
|<VC<|VGS|, the write-in of state 4 is realized with this.The write-in of state 4 is also meaned that previous already present write-in state
Erasing operation.
Compare the above write state 3 and write state 4.If channel layer is p-type semiconductor material, due to source electrode ferroelectricity
Film polarized state is to source-drain current IDSThe adjusting function of value is greater than drain electrode ferroelectric film polarization state, at this time the corresponding I of write state 3DS
Value is less than the corresponding I of write state 4DSValue.In contrast, if channel layer is n-type semiconductor, write state 3 at this time
Corresponding IDSValue is greater than the corresponding I of write state 4DSValue.
Thus via VGDAnd VGSThe reasonable combination of value is written with four kinds of different source-drain electrode ferroelectricities in ferroelectric transistor
Polarized state, different iron electric polarization states regulate and control channel layer source-drain current, generate different source-drain current values.That is, via right
Source-drain current value I under different polarization state combinationsDSMeasurement, realize reading to the storage information having been written into.
According to same principle, it can be achieved that other ferroelectric transistor structures（Such as the contact of bottom gate bottom, top-gated top contact, top-gated bottom
Contact etc.）Four states write-in, erasing and read operation.
In ferroelectric transistor memory construction, channel layer materials can be all kinds of materials with semiconductor function, such as oxygen
Compound semiconductor, silicon semiconductor, organic semiconductor, two-dimensional semiconductor etc..According to the difference of semiconductor material used, channel layer can
The deposition method of vacuum deposition or solution base can be used using different preparation processes, such as oxide semiconductor；Two-dimensional semiconductor
Vapor deposition, vacuum deposition, the equiprobable preparation process of mechanical stripping can be used；Vacuum and solution base can be used in organic semiconductor
Deposition method.
In ferroelectric transistor memory construction, ferroelectric layer can be all kinds of organic and inorganic ferroelectric material, such as inorganic iron
Transistor, inorganic ferroelectric ceramics, organic ferroelectricity small molecule and ferroelectric polymers etc..According to the difference of ferroelectric material used, use
Different preparation processes.As solution methods preparation can be used in ferroelectric polymer layer；Vacuum and solwution method can be used in inorganic ferroelectric film
Technique preparation.
The present invention can directly be such that its storage holds in the case where not changing ferroelectric transistor memory preparation process and structure
Measure it is double, it is applied widely.
Detailed description of the invention
Fig. 1 is bottom gate top contact ferroelectric transistor structural schematic diagram.
Fig. 2 is source area and drain region ferroelectric layer difference polarized state schematic diagram in ferroelectric transistor.
Fig. 3 is deposited by p-type organic semiconductor DPP-DTT and ferroelectric polymers P (VDF-TrFE) ferroelectric transistor constituted
The transfer characteristic curve figure of reservoir.
Fig. 4 is deposited by p-type organic semiconductor DPP-DTT and ferroelectric polymers P (VDF-TrFE) ferroelectric transistor constituted
Four storage state electric current versus time curves of reservoir.
Specific embodiment
It is clear in order to be more clear the object, technical solutions and advantages of the present invention, below in conjunction with specific embodiment, to this
Invention is described in further details, and example described herein is only a part of the invention, rather than whole examples, together
When by example to explain the present invention, be not intended to limit the present invention.
Embodiment 1
The present embodiment introduction is based on p-type organic semiconductor DPP-DTT and Ferroelectric Copolymers P (VDF-TrFE) and constructs ferroelectric memory
Preparation process.Device uses bottom gate top contact structure as shown in Figure 1, and wherein source-drain electrode materials are Copper thin film, for simplification
Device preparation technology process, using heavily doped n-type silicon chip as bottom-gate.Device preparation step is：
1, through successively drying after alcohol, acetone, deionized water ultrasonic cleaning, the substrate and grid as device make n-type silicon chip
With；
2, P (VDF-TrFE) is dissolved in cyclopentanone, is configured to the homogeneous solution that mass concentration is 10%, then uses spin coating
Solution is spin-coated on clean silicon wafer by technique；
3, the silicon wafer that spin coating has P (VDF-TrFE) film is placed on 90 DEG C of warm table and is toasted 10 minutes, removal residual is molten
Agent.It is then placed on 130 DEG C of warm table and anneals 3 hours, to improve its crystallinity；
4, DPP-DTT is dissolved in chlorobenzene with 3mg/mL concentration and is configured to homogeneous solution, P is spun in nitrogen glove box
(VDF-TrFE) it on film, then anneals 3 hours at 130 DEG C；
5, using mask plate method and vacuum thermal evaporation technique, copper source drain electrode is deposited on DPP-DTT film, forms transistor
Channel.70 μm of channel length, width 0.5mm.
Embodiment 2
How the present embodiment introduction realizes transistor four state store function via different combinations of voltages is applied in source and drain gate electrode
Energy.Ferroelectric transistor used is the transistor arrangement prepared in embodiment 1.When transistor operation, source electrode ground connection.The write-in of four states
In the process, the voltage range that source and drain grid is applied can be by the transfer characteristic curve (I of transistor as shown in Figure 3DS) and grid electricity
Flow curve (IGS) determine.When two curve determinations, the constant V of drain voltageDS- 140V is arrived in=- 40V, grid voltage 100V scanning.?
It can be seen that gate source current I in the left half-court Fig. 3 (a)GSThere is two peak positions, first corresponding VGSIt is source electrode covering for -60V
The Switching Currents of area's ferroelectric layer, second corresponding VGSIt is the Switching Currents of drain electrode overlay area for -100V.The
The absolute value of one peak position corresponds to the coercive voltage namely 60V of ferroelectric thin film.Later again by VGS100V is increased to by -140V,
It can see I in the right half-court Fig. 3 (a)GSTwo peak positions are equally existed, first is drain electrode reverse current peak value, and second is source
Umpolung current peak.It can be seen that when drain voltage is VDSWhen=- 40V：VGSIt, can only when more than -60V but not up to -100V
Realize that source electrode overlay area is inverted by positive negative polarization；VGSWhen more than 20V but not up to 60V, drain electrode overlay area can only be realized
It is inverted by negative sense positive polarization.Equally, as shown in Fig. 3 (b), as drain voltage VDSWhen for 40V：VGSMore than 60V but not up to 100V
When can only realize that source electrode overlay area is inverted by negative sense positive polarization；VGSIt can only realize that drain electrode is covered when more than -20V but not up to -60V
Cover area is inverted by positive negative polarization.Complex chart 3 (a) and (b), take VDS=40V, VGS=80V is the operation voltage of state 3, takes VDS
=-40V, VGS=-80V is the operation voltage of state 4.
Based on the above analysis, the write operation of four states is as follows：
Write state 1： VDS=40V, VGS=140V, the ferroelectric layer of entire device can guarantee as forward direction polarization, such as Fig. 2 at this time
(a) shown in.For p-type semiconductor, source-drain current value corresponding to this state is minimum in four states.
Write state 2：VDS=-40V, VGS=-140V, the ferroelectric layer of entire device can guarantee at this time polarizes for negative sense, such as
Shown in Fig. 2 (b).For p-type semiconductor, source-drain current value corresponding to this state is maximum in four states.
Write state 3：Apply V firstDS=-40V, VGS=-140V, write-in to state 2；Then apply VDS=40V, VGS=
80V, the polarization direction of the ferroelectric layer of source electrode overlay area becomes positive polarization at this time, and drain electrode is still negative polarization, as shown in Fig. 2 (c).
Write state 4：Apply V firstDS=40V, VGS=140V, write-in to state 1；Then apply VDS=-40V, VGS=-
80V, the polarization direction of the ferroelectric layer of source electrode overlay area becomes negative polarization at this time, and drain electrode is still positive polarization, as shown in Fig. 2 (d).
Test results are shown in figure 4 for four write-in states, it is seen that and apparent four state is distinguished, and four state electric currents are respectively 3.27 ×
10-7A, 1.83 × 10-7A, 5.58 × 10-8A and 4.51 × 10-9A。
Claims (5)
1. a kind of operating method of the four state ferroelectric transistor memories based on source drain regions otherness iron electric polarization, ferroelectricity
The structure of transistor is：A pair of of source/drain, a grid, a semiconductor channel layer and a ferroelectric layer；It is characterized in that,
By to source and drain grid three extremely on apply alive Reasonable Regulation And Control, realize the otherness pole to source area and drain region ferroelectric film
Change, combined by different polarized states, four state accessing operations are realized on a ferroelectric crystal tube device.
2. operating method according to claim 1, which is characterized in that electric dipole differently- oriented directivity in ferroelectric layer is upward
Polarized state is defined as positive polarization state, when the downward polarized state of electric dipole differently- oriented directivity in ferroelectric film is defined as negative polarization
State；Grid and voltage between source electrodes are denoted as VGS, grid and leakage voltage across poles are denoted as VGD, voltage is denoted as V between drain-sourceDS, electric current between drain-source
It is denoted as IDS, electric current is denoted as I between grid sourceGS, ferroelectric film coercive voltage is VC；The write operation that four states store information is as follows：
Write state 1：VGSAnd VGDFor positive value and it is all larger than VCWhen, the equal positive polarization of the ferroelectric film of source area and drain region；
Write state 2：VGSAnd VGDFor negative value and the two absolute value is all larger than VCWhen, the equal cathode of the ferroelectric film of source area and drain region
Change；
Write state 3：VGSFor positive value and it is greater than VC, while VGDFor negative value and its absolute value is greater than VCWhen, source area ferroelectric film is just
Polarization, and drain region ferroelectric film negative polarization；I at this timeDSCurrent value is between OFF state and on-state current value；When practical operation,
On the basis of write state 2, apply positive VDSAnd VGSValue, and guarantee VDS<VC<VGS, realize the write-in of state 3；
Write state 4：VGDFor positive value and it is greater than VC, while VGSFor negative value and its absolute value is greater than VCWhen, source area ferroelectric film is negative
Polarization, and drain region ferroelectric film positive polarization；I at this timeDSCurrent value is between OFF state and on-state current value；When practical operation,
On the basis of write state 1, apply negative VDSAnd VGSValue, and guarantee | VDS|<VC<|VGS|, realize the write-in of state 4.
3. operating method according to claim 2, which is characterized in that used ferroelectric material is selected from small point of organic ferroelectricity
Son, ferroelectric polymers, inorganic ferroelectric ceramics, inorganic ferroelectric crystal, two-dimentional ferroelectric.
4. operating method according to claim 2, which is characterized in that used semiconductor material be selected from silicon semiconductor,
Oxide semiconductor, organic semiconductor, two-dimensional semiconductor material.
5. operating method according to claim 2, which is characterized in that the structure of the ferroelectric transistor is top-gated apical grafting
Touching, the contact of top-gated bottom, the contact of bottom gate bottom or bottom gate top contact.
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| CN112687739A (en) * | 2020-12-28 | 2021-04-20 | 华中科技大学 | Two-dimensional material analog circuit and preparation method and application thereof |
| CN115064555A (en) * | 2022-06-09 | 2022-09-16 | 西安电子科技大学 | Multi-value memory device of ferroelectric assembled grid field effect transistor |
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