TW201010030A - Chip scale package structure, package structure and process thereof - Google Patents

Chip scale package structure, package structure and process thereof Download PDF

Info

Publication number
TW201010030A
TW201010030A TW098123735A TW98123735A TW201010030A TW 201010030 A TW201010030 A TW 201010030A TW 098123735 A TW098123735 A TW 098123735A TW 98123735 A TW98123735 A TW 98123735A TW 201010030 A TW201010030 A TW 201010030A
Authority
TW
Taiwan
Prior art keywords
wafer
substrate
heat sink
package structure
unit
Prior art date
Application number
TW098123735A
Other languages
English (en)
Inventor
Karl Appelt Bernd
Bradford J Factor
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Publication of TW201010030A publication Critical patent/TW201010030A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

201010030 -NEW-F1KAL-TW-20090714 六、發明說明： 【發明所屬之技術領域】 本發明是有關於-種晶片封農結構及其製作方法，且 特別是有關於一種晶片級封裝結構及其製作方法。 【先前技術】 ❹ 隨著晶Μ體赫小、電子树的運減度增加以及 裝密度增加’半導體封裝所產生的減大幅增加。為增進 封裝結構的散健力，-般—絲 器來協助晶片散熱。 月文熟 以習知的球格狀陣列封裝（baUgridarray，BGA)結 —散熱器配置於晶片上，並藉由—黏性材料黏著 ^板。H將散熱器—對—地配置於晶片上既費時又 買力。 的封結構㈣性需求，已發展出多種不同 =裝技t ’其中〜種發展良好的封裝技術為晶片級封裝 csp)技術。前述晶片、級封裝技術可 ::使其僅些微大於原本的晶片尺寸。 加重要。；曰曰及封裝結構相當緊密’因此散熱問題又更 【發明内容】 陣列的封裝結構，其利用 本發明提丨-種具有散熱器 c, \V-FINAL-T W-20090714 201010030 網狀 由晶片上彼此相連的散熱器單元所構成的一陣列或— 物來協助封裝結構散熱。 曰片種封裝製程’以製作散熱性質良好的 j級封裝結構。_散熱轉列，可簡化封裝製程 …益的设置與貼附，並可使其較不費力。再者，本發明之 封裝製程與習知的封裝製程及/或封裝設備相容。a 曰本發明提出-種晶片級封裝結構包括—基板單元、一 =熱器、-封裝膠體以及至少—銲球。基 片安裝於基板單元的安裝面 片之置於晶片上，且—接合膜配置於散熱器與晶 中散熱15具有一本體部、—延伸部與一傾斜部， 本體雜於晶片頂部並_至晶片，延伸部_至基板單 斜部連接本體部與延伸部。封裝賴覆蓋散熱器， 伸邻^^散熱11、晶片與基板單元之間，其巾散熱器的延 ^的-端暴露於封裝膠體外，且封裝膠體的一侧壁盘基 扳早凡的-㈣域。銲球配置於基板單摘背面。、 在本發明之-實施例中’晶片透過配置於晶片與基板 几之間的多個凸塊電性連接至基板單元。 膠，例中，晶片級封裝結構更包括—底 其配置於晶片與基板單元之間，並包覆凸塊。 露;^^發明之—實施财，散熱11的本體部的—頂面暴 路於封襞膠體外。 ^ 至茂發明之-實施射U透過？條導線電性連接 201010030 -NEW-FINAL-TW-20090714 在本發明之一實施例中，散熱器的本體部藉由配置於 其與晶片之間的一接合膜貼覆至晶片。 在本發明之一實施例中，接合膜包括一導線上薄膜 (film-over-wire > FOW)。 在本發明之一實施例中，封裝膠體更包括導熱填充 物。 在本發明之一實施例中，導熱填充物的材質包括氮化 铭顆粒、氧化鋁顆粒、氮化硼顆粒或奈米碳管。 在本發明之一實施例中，散熱器的本體部的形狀為圓 形、三角形、方形、矩形或多邊形。 本發明提出一種封裝製程如下所述。首先，提供—基 板，其中基板包括多個基板單元。接著，安裝多個晶片= 基板的基板單元，其中每一基板單元安裝有至少一晶片。 然後，設置並貼附-散熱器陣列至晶片上，並使散敎器陣 列位於基板上’其中散熱轉列包括多個彼此相連 器單元’每-散熱H單元對應—晶片。之後，在基板上形 成-封裝賴’以彳 1蓋散熱轉列U與基板單元。接 著’在基板的一背面形成多個銲球。然後，切割封裝膠體、 散熱器陣贿基板則彡成多觸裝單元，其巾各封裝單元 ί括7部份的封歸體、-散熱ϋ單元、-晶片、-基板 早TL與一銲球。 做 在本發明之—實關巾，設置並關散麵陣列的步 包括在散熱料列的—内表面上形成—接合膜。 在本發月之Μ &例中，設置並貼附散熱器陣列的步 5 iV-FJNAL-T W-20090714 201010030 驟更包括在晶片的頂部形成一接合膜。 在本發明之一實施例中，封裝製程更包括在將晶片安 裝至基板之前，形成多個凸塊於晶片與基板單元之間。 在本發明之一實施例中，封裝製程更包括於晶片與基 板單元之間形成一底膠，以包覆凸塊。 ^ 在本發明之-實施例中，封裝製程更包括在安裝晶片 至基板之後，形成多個導線於晶片與基板單元之間。 本發明提出-種封裝結構包括—基板、多個晶片、一 散熱斋陣列、一封裝膠體以及多個 板單元。各基板單元安裝有至少„ 個基 覆弋片，其中散熱器陣列包括多個彼此相連 具有-本體部、^ 1各散熱器單元 體部與延伸部。封早兀’傾斜部連接本 於散熱轉列f基板與散熱，並填充 面。 —與基板之間。銲球配置於基板的—背 在本發明之—眘 元之=個凸塊電二置於其軸 面暴露於體^施例中，散熱器單元的本體部的-頂 至基ΐΐί明之1施例中’晶片透過多條導線電性連接 在本备明之-實施例中，散熱器單元的本體部藉由配 厶-NEW-FINAL-TW-20090714 201010030 置於其與晶片之間的一接合膜貼覆至晶片。 在本發明之一實施例中，接合膜包括一導線上薄膜 (film-over-wire，FOW)。 在本發明之一實施例中，封裝膠體更包括導熱填充 物。 在本發明之一實施例中’導熱填充物的材質包括氮化 鋁顆粒、氧化鋁顆粒、氮化硼顆粒或奈米碳管。 綜上所述，由於本發明採用散熱器陣列，故本發明可 透過較為簡易的步驟，提升封裝結構的散熱功效。此外， 可使封裝結構的可靠度與產品良率增加。 為讓本發明之上述和其他特徵和優點能更明顯易 懂，下文特舉實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 下列所述的較佳實施例是以晶片級封裝技術為例，但 並非用以限定本發明之範圍。除了晶片級封裝技術之外， 晶圓級晶片尺寸封裝（wafer-level chip scale package，
WLCSP )技術、球格狀陣列封裝技術或面陣列覆晶技術 (area-array flip Chip technology)皆可用以製作本發明之 封裝結構。此外，在適合的情況下，可應用單晶片封裝、 堆疊式晶片封裝以及平面型的多晶片封裝（ multi-chip package，MCM)等晶片級封裝技術製作 之封裝結構。 X
圖1A為本發明一實施例之封裝結構的上視圖。圖1B 7 ts \V-F1NAL-TW-20090714 201010030 為本發明一實施例之散熱器陣列的局部示意圖。圖2八〜2£ 為本發明一實施例之晶片級封裝製程的剖面圖。請參照圖 1A，基板1〇〇具有多個區塊1〇1，各區塊1〇1包括^個'^ 板單兀102’且各區塊ι〇1上安裝多個晶片11〇。虛線代表 切割線，切割工具可沿前述切割線分割基板單元1〇2 裝的晶片110可藉由打線接合技術或覆晶技術電性連接至 基板100。在本實施例中，晶片11〇 一對一地安裝到基板 ^元102上。此外，當欲形成堆疊晶片封裝或多晶片二裝 時，可在單一基板單元1〇2上安裝多個晶片11〇。 圖2Α為圖1Α中單一基板單元1〇2的剖面圖的一個 例子。如圖2Α所示，晶片110安裝於基板1〇〇的基板單 兀102上。基板1〇〇例如是一多層線路板，且此多層線路 板的最外層具有多個接點104。為簡化起見，未繪示覆蓋 與接點104相連的跡線（trace)的防焊保護層。同樣地， 跡線/接點104通常是配置於基板100上，而非埋在基板 100内（如圖2A所示）。接點1〇4可依實際的應用與設計 需求而以不同的方式配置於基板1〇〇的晶片接合區上。各 晶片11〇具有一主動面112與相對於主動面112的一背面 1H。多個形成在主動面112上的凸塊12〇位置對應於基板 100的晶片安裝區域内的接點104，如此，則晶片u〇可透 過凸塊120電性連接至基板100。 如圖2A所示’為降低因晶片uo與基板1〇〇之間熱 膨脹係數不同而對晶片11〇與基板100所造成的損害，可 在b曰片110與基板1〇〇之間選擇性地填入一底膠I】？。然 201010030 NEW-FINAL-TW-20090714 而，由於底膠122有溢流的問題存在，因此可跳過填入底 膠122的步驟。 、一 請同時參照圖1B與圖2B，一散熱器陣列14〇配置於 晶片110上，且一接合膜130配置於散熱器陣列14〇與晶 片110之間。舉例來說，如圖1B所示，散埶器陣 包括多個散熱器單元H2,其彼此相連而形成一網狀物。 請參照圖1B，各散熱器單元142包括一本體部M2a以及 φ 與本體部142a連接的多個分支142b，散熱器單元142藉 由分支142b彼此相連。也就是說，各散熱器單元142的分 支142b連接至鄰近的散熱器單元142。散熱器陣列14〇的 材質例如為銅、鎳、鎳銅及其合金或是其他適合的金屬。 在另厂方面，陶瓷型的散熱器陣列14〇的材質例如為碳化 矽（silicon carbide ’ SiC )或是其他高導熱性質的陶瓷材料。 本體部142a的形狀例如為圓形、方形、三角形、矩形或多 邊形，分支142b的數目不限於四、六或八，而可為任何大 於的整數。散熱盗單元142與/或本體部142a的尺寸或 圖案可依封裝結構10的設計需求而調整，而本體部 與分支142b的面積比可調整或定做，以達到封裝結構 所需的散熱係數。 當散熱器陣列140配置於晶片11〇上，各散熱器單元 142對應一晶片11〇，散熱器單元142的本體部M2a經由 接合膜130黏著至晶片ι10的背面114。較佳地，在將散 熱态陣列140配置於晶片11〇上之前，接合膜13〇配置於 散熱器陣列140的-内表面14〇a上，或者是配置於晶片 201010030 —-------iiW-FINAL-TW-20090714 110的背面114上。接合膜130例如為一膜狀黏著劑或是 一導線上薄膜（film-over-wire，FOW)型的晶片連結膜。 清同時參照圖1B與圖2C，進行一模鍛製程（stamping process )’以將平板狀的散熱器陣列屡成一沉置 (down-set)的散熱器結構144,並形成多個立體的散熱器 早元146，其覆盍晶片Π〇與基板1〇〇的部分接點。平 板狀的散熱器皁元142抵壓住晶片11〇，且本體部i46a仍 為平板狀’分支142b則是被向下彎折而成為立體散熱器單 元146中的一傾斜部146b與一延伸部146c。傾斜部146b 位於本體部146a與延伸部146c之間，且延伸部146c配置 於基板100上。在一迴銲製程（refl〇w pr〇cess)或一固化 製程（curing process)之後，沉置的散熱器結構144例如 透過焊料或黏著劑126貼附至基板1〇〇。在模锻製程之前， 焊料或黏著劑126可事先配置於基板1〇〇上或是散熱器陣 列1=上。因此，沉置的散熱器結構144導熱性地^接至 基板單元102。選擇性地，沉置的散熱器結構144可透過 一個或多個接點104電性連接與導熱性連接至基板單元 102，以提供接地或是屏蔽的功效。 土 請參照圖2D ’進行一封膠製程，以在基板1〇〇的頂 面上形成-封裝膠體15〇,其覆蓋沉置的散熱器結構144 與其下的晶片110以及基板100的頂面。若是省略填入底 膠122此一選擇性步驟，封裝膠體150可覆蓋凸塊以 及基板100的接點104，此即所謂的單一封膠技術 (mold-only approach)。較佳地，沉置的散熱器結構144 ：-i^EW-FiNAL-TW-20〇9〇714 ❹ 囈 201010030 的主體部146a的頂面（外表面）⑽暴露於該封裝膜越 150之外’以提升散熱效果。封裝膠體15()可為― 脂（Ρ〇1—η)。此外，導熱填充物例如是氮= 粒、氧化铭顆粒、氮化石朋顆粒、奈米碳管或 敎 質良好的填錄f，前料熱填充物皆可添;; 150中以提升散熱效率。 請參照圖2E ’在形成銲球17〇之後，例如沿著切 獨封10 ’以將封裝結構10切單成;個 獨立的封裝早凡叫如圖逆所示）。各封料元 至少基板單凡搬、—晶片11〇、一立體的散熱器 146與部分的封裝膠體15〇。 圖2F為本發明一實施例之切單後之晶片級封裝姓 ，面圖。請參照圖2F，在封裝單元15中，立體的黄^ =早兀1=配置於基板單元102上並覆蓋晶片11〇。本體 I5 146a藉由接合膜130黏著至晶片ι1〇，且本體部1奶& 的外表面144b暴露於封裝膠體150外。埋在封裝膠體i5〇 中的傾斜部146b連接本體部146a與外延部146c。封装膠 體15〇後蓋配置於基板單元1〇2的頂面上的外延部h6c， 但封裝膠體150的侧壁15〇a暴露出外延部的末端 H7。虽切割基板1〇〇、散熱器結構144與封裝膠體15〇而 =成，立的封裝單元15時，封裝膠體15〇的侧壁15〇&與 土板單元102的側壁i〇2a切齊且共平面。 圖2G為本發明另一實施例之切單後之晶片級封裝結 構的剖面圖。當封裝單元15如圖2G所示（其與圖迕的 11 201010030 c^-FINAL-T W-20090714 15相似），晶片110可直接配置於基板單元1〇2 ^並^過導線⑽電性連接至基板單元搬。在圖2g的 μ ^兀15中’接合膜130配置於晶片110的主動面112 ^ ’接合膜DCH列如是導線上薄膜（跑_〇ver wire，f〇w) 合膜。因為導線上_的材f適於流動並包覆連 :曰曰片UG的導線16G，故接合膜13㈣位置與尺寸較有 译性而不會妨礙導線160的配置。 t較於配置個別的散熱器的製程效率差且費時，配置 =的=^^連獅賴騎顺為«，錄熱器 車歹m用法相谷於已知的封衷製程 熱器陣列可設計為相容於已知的 卜=連^放 有較高的成本效益。 ⑽社㈣構件’故可具 此用，度，句且具有適當的流動性的接合膜，因 力膠之前另外使用黏著劑固定散熱器，進而增
Q 制良好的間距。在二二= 片之間的空隙。因此，可 =2:靠性。此外，可添加導熱填充物射 裝膠或接合财’吨升縣結_散㈣效。 本發明以實施例揭露如上’然其並非用以限定 明之精神和範圍内’當可作些許之更動與潤:不=2 明之保護_當視後社申請翻範_界定者鱗。' 12 201010030 „ NEW-FINAL-TW-20090714 【圖式簡單說明】 圖1A為本發明一實施例之封裝結構的上視圖。 圖圖1B為本發明-實施例之散熱器陣列的局部示意 面圖圖2A〜2E為本發明—實施例之晶片級封裝製程的剖 的剖為本發明—實施例之切單後之晶片級封裝結構 圖2G為本發明另—杳士 構的剖關。 實_之切早後之晶片級封裝結 【主要元件符號說明】 10 :封裝結構 15 :封裝單元
100 ·基板 101 :區塊 102 :基板單元 102a、150a :側壁 104 :接點 11〇 :晶片 112 :主動面 114 :背面 120 .凸塊 13 201010030^ A^-FINAL-TW-20090714 122 :底膠 126 :焊料或黏著劑 130 :接合膜 140 :散熱器陣列 140a ··内表面 142 :散熱器單元 142a、146a :本體部 142b :分支 144:散熱器結構 ® 144b:頂面或外表面 146 :散熱器單元 146b :傾斜部 146c ··延伸部 147 ··末端 150 :封裝膠體 160 ·導線 170 :銲球 Θ 14

Claims (1)

  1. .NEW-F1NAL-TW-20090714 七、申請專利範園： 1 · 一種晶片級封裝結構’包括： 一基板單元，具有一安裝面與一背面； 一晶片’安裝於該基板單元的該安裝面上； 一散熱器，配置於該晶片上，且一接合膜配置於該散 熱益與該晶片之間，其中散熱器具有—本體部、一延伸部 與一傾斜部，該本體部位於該晶片頂部並貼附至該晶片， % 該延伸部貼附至該基板單元，該傾斜部連接該本體部與該 延伸部； 一封裝膠體，覆蓋該散熱器，並填充於該散熱器、該 晶片與該基板單元之間，其中該散熱器的該延伸部的一端 暴露於該封裝膠體外，且該封裝膠體的一側壁與該基板單 元的一側壁切齊；以及 至少一銲球’配置於該基板單元的該背面。 2. 如申請專利範圍第1項所述之晶片級封裝結構，其 魯 中該晶片透過配置於該晶片與該基板單元之間的多個凸塊 電性連接至該基板單元。 3. 如申請專利範圍第2項所述之晶片級封裝結構，更 包括： 一底膠’配置於該晶片與該基板單元之間，並包覆該 些凸塊。 4·如申請專利範圍第2項所述之晶片級封裝結構，其 中該散熱器的該本體部的一頂面暴露於該封裝膠體外。 5.如申請專利範圍第1項所述之晶片級封裝結構，其 15 ^V-FINAL-TW-20090714 201010030 c, 中該晶片透過多條導線電性連接至該基板單元。 6. 如申請專利範圍第1項所述之晶片級封裝結構，其 中該散熱器的該本體部藉由配置於其與該晶片之間的一接 合膜貼覆至該晶片。 7. 如申請專利範圍第6項所述之晶片級封裝結構，其 中δ亥接合膜包括一導線上薄膜（mm_〇ver_wire，F〇w)。 8. 如申請專利範圍第1項所述之晶片級封裝結構，其 中該封裝膠體更包括導熱填充物。
    9·如申請專利範圍第8項所述之晶片級封裝結構，其 中該導熱填充物的材質包括氮化鋁顆粒、氧化鋁顆粒、氮 化硼顆粒或奈米碳管。 1〇·如申請專利範圍第1項所述之晶片級封裝結構， 其中該散熱裔的該本體部的形狀為圓形、三角形、 矩形或多邊形。 π· —種封裝製程，包括： 提供一基板，其中該基板包括多個基板單元；
    安裝多個晶片至該基板的該些基板單元，其中每一基 板單元安裝有至少一晶片； 。。設置並貼附-散熱器陣列至該些晶片上，並使該散 盗陣列位於該基板上，其中該散熱^陣列包括多個彼此 連的散熱器單元，每—散熱H單元對應-晶片； 基板上形成—封震膠體，以覆蓋該散熱器陣列 5亥些日日片與該些基板單元； 在該基板的—背娜成？鑛球；以及 16 201010030 ^EW-F^AL-TW~20090714 切割該封裝膠體、該散熱器陣列血嗦 封裝單元，其中各封裝單元包括—部份的多個 散熱器單m —基板單元與n域膠體、- 、12·如申請專利範圍第u項所述之封裝製程， 置並貼附該散熱器陣列的步驟更包括： 、’ 在散熱器陣列的一内表面上形成一接合膜。 、13.如申請專利範圍第u項所述之封裝製程，其中設 置並貼附該散熱器陣列的步驟更包括： ^
    在該晶片的頂部形成一接合膜。 14.如申請專利範圍第u項所述之封裴製程，更包 在將該些晶片安裝至該基板之前，形成多個凸塊於該 晶片與該基板單元之間。 15.如申請專利範圍第14項所述之封裝製程，更包 括： 於該晶片與該基板單元之間形成一底膠，以包覆該些 凸塊。
    16.如申請專利範圍第η項所述之封裝製程，更包 括： 在女裝該些晶片至該基板之後，形成多個導線於該晶 片與該基板單元之間。 —種封裝結構，包括： —基板，具有多個基板單元； 多個晶片’其中各基板單元安裝有至少一晶片； —散熱器陣列’配置於該基板上並覆蓋該些晶片，其 17 «V-HNAL-TW-200907I4 201010030 !> 器單元對應一晶;元’各韻 二該=部貼附至該基板單元’該傾斜部連接該本 一封裴膠體，覆蓋該基板與該散熱器陣列，並埴 該散熱器陣列、該些晶片與該基板之間，·以及/、 ? 多個銲球，配置於該基板的一背面。
    18·如申請專利範圍第17項所述之封裝結構，其中言少 曰曰^透過配置於其與該基板單元之間的多個凸塊電性連接 至該基板單元。 如申請專利範圍第18項所述之封裝結構，其中該 散熱益單元的該本體部的一頂面暴露於該封裝膠體外。 曰20.如申請專利範圍第17項所述之封裝結構，其中該 晶片透過多條導線電性連接至該基板單元。 ^
    21.如申請專利範圍第17項所述之封裝結構，其中該 散熱器單元的該本體部藉由配置於其與該晶片之間的一^ 合膜貼覆至該晶片。 22·如申請專利範圍第21項所述之封裝結構，其中該 接合膜包括一導線上薄膜（fjlm_over_wire，F〇W )。 23. 如申請專利範圍第17項所述之封裝結構，其中該 封裝膠體更包括導熱填充物。 24. 如申請專利範圍第23項所述之封裝結構，其中該 導熱填充物的材質包括氮化鋁顆粒、氧化鋁顆粒、氮化爛 顆粒或奈米碳管。 18
TW098123735A 2008-08-27 2009-07-14 Chip scale package structure, package structure and process thereof TW201010030A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/199,121 US20100052156A1 (en) 2008-08-27 2008-08-27 Chip scale package structure and fabrication method thereof

Publications (1)

Publication Number Publication Date
TW201010030A true TW201010030A (en) 2010-03-01

Family

ID=41724091

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098123735A TW201010030A (en) 2008-08-27 2009-07-14 Chip scale package structure, package structure and process thereof

Country Status (3)

Country Link
US (1) US20100052156A1 (zh)
CN (1) CN101661913A (zh)
TW (1) TW201010030A (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI447868B (zh) * 2010-06-15 2014-08-01 Chipmos Technologies Inc 散熱型電子封裝結構及其製備方法
TWI761864B (zh) * 2020-06-19 2022-04-21 海華科技股份有限公司 散熱式晶片級封裝結構
TWI766164B (zh) * 2019-05-28 2022-06-01 力成科技股份有限公司 封裝結構
TWI828054B (zh) * 2022-01-28 2024-01-01 群創光電股份有限公司 電子裝置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8067256B2 (en) * 2007-09-28 2011-11-29 Intel Corporation Method of making microelectronic package using integrated heat spreader stiffener panel and microelectronic package formed according to the method
TWI420640B (zh) * 2008-05-28 2013-12-21 矽品精密工業股份有限公司 半導體封裝裝置、半導體封裝結構及其製法
CN102130571B (zh) * 2011-03-21 2013-12-04 华为技术有限公司 一种电源封装及其装置
JP5799541B2 (ja) 2011-03-25 2015-10-28 株式会社ソシオネクスト 半導体装置及びその製造方法
CN103390596B (zh) * 2012-05-09 2017-03-01 旭宏科技有限公司 半导体的绝缘封装装置及其制造方法
CN105161467B (zh) * 2015-08-14 2019-06-28 株洲南车时代电气股份有限公司 一种用于电动汽车的功率模块
US20220352055A1 (en) * 2021-04-30 2022-11-03 Texas Instruments Incorporated Heat-dissipating wirebonded members on package surfaces

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6150353A (ja) * 1984-08-20 1986-03-12 Oki Electric Ind Co Ltd Ｅｐｒｏｍ装置
KR970005712B1 (ko) * 1994-01-11 1997-04-19 삼성전자 주식회사 고 열방출용 반도체 패키지
US6359335B1 (en) * 1994-05-19 2002-03-19 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures
US6117797A (en) * 1998-09-03 2000-09-12 Micron Technology, Inc. Attachment method for heat sinks and devices involving removal of misplaced encapsulant
TW418511B (en) * 1998-10-12 2001-01-11 Siliconware Precision Industries Co Ltd Packaged device of exposed heat sink
US6215180B1 (en) * 1999-03-17 2001-04-10 First International Computer Inc. Dual-sided heat dissipating structure for integrated circuit package
JP2001210761A (ja) * 2000-01-24 2001-08-03 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US6599779B2 (en) * 2001-09-24 2003-07-29 St Assembly Test Service Ltd. PBGA substrate for anchoring heat sink
US7196415B2 (en) * 2002-03-22 2007-03-27 Broadcom Corporation Low voltage drop and high thermal performance ball grid array package
US6838761B2 (en) * 2002-09-17 2005-01-04 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield
US7259445B2 (en) * 2002-09-30 2007-08-21 Advanced Interconnect Technologies Limited Thermal enhanced package for block mold assembly
US7061103B2 (en) * 2003-04-22 2006-06-13 Industrial Technology Research Institute Chip package structure
US6747350B1 (en) * 2003-06-06 2004-06-08 Silicon Integrated Systems Corp. Flip chip package structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI447868B (zh) * 2010-06-15 2014-08-01 Chipmos Technologies Inc 散熱型電子封裝結構及其製備方法
TWI766164B (zh) * 2019-05-28 2022-06-01 力成科技股份有限公司 封裝結構
TWI761864B (zh) * 2020-06-19 2022-04-21 海華科技股份有限公司 散熱式晶片級封裝結構
TWI828054B (zh) * 2022-01-28 2024-01-01 群創光電股份有限公司 電子裝置

Also Published As

Publication number Publication date
US20100052156A1 (en) 2010-03-04
CN101661913A (zh) 2010-03-03

Similar Documents

Publication Publication Date Title
TW201010030A (en) Chip scale package structure, package structure and process thereof
US9741638B2 (en) Thermal structure for integrated circuit package
CN104716109B (zh) 具有降低热串扰的热管理部件的封装件及其形成方法
TWI445140B (zh) 半導體封裝基板
US20180040592A1 (en) Interconnect structure with improved conductive properties and associated systems and methods
TW423120B (en) Semiconductor device having a sub-chip-scale package structure and method for forming same
US7847415B2 (en) Method for manufacturing a multichip module assembly
CN104733329B (zh) 半导体封装结构和工艺
KR20190045374A (ko) 고효율 열 경로 및 몰딩된 언더필을 구비한 적층형 반도체 다이 조립체
US10004161B2 (en) Electronic module with laterally-conducting heat distributor layer
WO2013074454A2 (en) Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
TW201201329A (en) Thermally enhanced electronic package and method of manufacturing the same
TWI359483B (en) Heat-dissipating semiconductor package and method
US10504841B2 (en) Semiconductor package and method of forming the same
US8536701B2 (en) Electronic device packaging structure
TWI255047B (en) Heat dissipating semiconductor package and fabrication method thereof
US7768104B2 (en) Apparatus and method for series connection of two die or chips in single electronics package
TWI536515B (zh) 具有散熱結構之半導體封裝元件及其封裝方法
CN218867084U (zh) 一种导出型散热结构、扇出型封装结构及集成电路
TWI225296B (en) Chip assembly package
CN115312406A (zh) 芯片封装结构及制备方法
TW200826261A (en) Thermally enhanced BGA package apparatus & method
TWI755319B (zh) 晶片封裝結構
CN102769004A (zh) 电子元件封装结构
CN116314043A (zh) 含有多层级电力基板的射频封装和相关联制造方法