201007182 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種測試裝置，尤指一種pCI (Peripheral Component Interconnection，週邊組件互連） 介面測試卡。 【先前技術】 電腦發展曰新月異，功能愈來愈多，各種外接卡亦愈 ❹來愈夕特別疋具有pci介面之各種外接設備在不斷之發 展與增多。PCI介面是主機板之主要擴展介面，透過插接 不同之擴展卡可以獲得目前電腦能實現之幾乎所有外接功 能。為了保證電腦主機板上PCI外接擴展卡正常工作，需 ，對m介面中匯流排之時脈、重定、中斷、資料及位址 等訊就進行訊號完整性測試，以驗證是否符合pci規範之 要求。 目别之測δ式方法通常是選用一塊或幾塊符合PCI規範 擴展卡（如PCI網路卡等）作為測試設備，在擴展卡 引出時脈、重定、中斷、資料、位址等幾類訊號，然後 ==地回路，再用探棒進行探測。該㈣試方法需要在 下盤山上焊接多個訊號測試點和地線來進行測試，造成以 策4冑展卡上用於焊接延長線之訊號點未必是符合訊 二，測試需求之訊號點，若不是的話會嚴重影響到 W面讯號測試結果之準確性^ ^ ^ ^ ^ ^ ^ 地線供探棒洌試#於3 Λ , 秌用坏接桌唬延長線和 測試不夠準轉長了訊號之傳輸長度’造成 且¥接品質之好壞亦影響到測試結果之 201007182 精確度，擴展卡上之時脈、重定、中斷、資料、位址等气 號並未在卡上標示出來，每次測試皆需要測試人員透過線 路圖來確認，影響了測試效率；多次焊接容易造成擴展卡 損壞，增加測試成本。 【發明内容】 鑒於上述内容，有必要提供一種測試準確、使用方便 之PCI介面測試卡。201007182 IX. INSTRUCTIONS: [Technical Field] The present invention relates to a test device, and more particularly to a pCI (Peripheral Component Interconnection) interface test card. [Prior Art] Computer development is changing with each passing day, and more and more functions are being used. Various external cards are becoming more and more popular, and various external devices with a pci interface are constantly developing and increasing. The PCI interface is the main expansion interface of the motherboard. By plugging in different expansion cards, almost all external functions that can be realized by the current computer can be obtained. In order to ensure the normal operation of the PCI external expansion card on the motherboard of the computer, the signal integrity test is performed on the clock, re-determination, interruption, data and address of the bus in the m interface to verify whether the requirements of the pci specification are met. . The method of measuring the delta type usually adopts one or several PCI-compliant expansion cards (such as PCI network cards) as the test equipment, and extracts clocks, re-determination, interruption, data, address and other signals on the expansion card. Then, == ground loop, and then probe with probe. The (4) test method needs to weld multiple signal test points and ground lines to the test on the lower plate mountain. The signal points used to weld the extension lines on the card is not necessarily in compliance with the signal requirements of the test. If not, it will seriously affect the accuracy of the W-signal test results ^ ^ ^ ^ ^ ^ ^ Ground line for the test rod test #于3 Λ, use the bad table, the extension line and the test is not enough to turn the signal The transmission length 'causes the quality of the connection and the quality of the connection also affects the accuracy of the test result 201007182. The clock number, re-determination, interruption, data, address and other air numbers on the expansion card are not marked on the card. Tests need to be confirmed by the tester through the circuit diagram, which affects the test efficiency; multiple welds are likely to cause damage to the expansion card and increase the test cost. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a PCI interface test card that is accurate and easy to use.
❹ 一種PCI介面測試卡，包括一 PCI介面晶片、複數PCI 接腳及複數與該PCI介面晶片引腳對應相連之PCI測試引 腳，該PCI介面晶片與該等PCI接腳連接，該等pci接腳 用於插接一待測主機板上之PCI插槽，以使該PCI介面晶 片與該待測主機板進行通訊，該等PCI測試引腳用於電性 接觸一電子測試設備之探針以透過該電子測試設備對 訊號進行測量。 相較習知技術，該PCI介面測試卡上設置複數PCI β訊號引腳及相對應之接地引腳之方法供電子測試設備之探 針使用，消除了測試點不準確引起之測量誤差及延長線之 使用引起之訊號失真，從而保證了測試精確度；而且設置 PCI訊號引腳之方法避免了在測試設備上多次焊接而造成 設備損壞，節約了測試成本。 【實施方式】 請參照圖i，本發明PCI介面測試卡之較佳實施方式 包括;"PCI介面晶片1〇、複數PCI接腳30(即俗稱之“金 手指”）及複數PCI測試引腳4〇 (本實施方式中為十個 201007182 PCI測試引腳）。每一個PCI測試引腳40均包括一訊號引 腳J及一接地引腳GND。該十個PCI測試引腳之訊號引腳 J分別為匯流排命令/位元組允許引腳C/BE、PCI週期幀引 腳FRAME、PCI主控準備好訊號引腳IRDY、PCI目標準 備好訊號引腳TRDY、PCI時脈訊號引腳CLOC、電壓引腳 VCC、停止訊號引腳STOP、三個位址/資料複用引腳AD0、 ADI、AD2。該匯流排命令/位元組允許引腳C/BE、PCI週PCI A PCI interface test card, comprising a PCI interface chip, a plurality of PCI pins, and a plurality of PCI test pins connected to the PCI interface chip pins, wherein the PCI interface chip is connected to the PCI pins, and the PCI interfaces are connected to the PCI pins. The pin is used for plugging a PCI slot on the motherboard to be tested, so that the PCI interface chip communicates with the motherboard to be tested, and the PCI test pins are used for electrically contacting the probe of an electronic test device. The signal is measured by the electronic test equipment. Compared with the prior art, the method of setting a plurality of PCI β signal pins and corresponding ground pins on the PCI interface test card is used for the probes of the electronic test equipment, thereby eliminating measurement errors and extension lines caused by inaccurate test points. The signal distortion caused by the use ensures the accuracy of the test; and the method of setting the PCI signal pin avoids the equipment damage caused by multiple soldering on the test equipment, thereby saving the test cost. [Embodiment] Referring to FIG. 1, a preferred embodiment of the PCI interface test card of the present invention includes: a PCI interface chip, a plurality of PCI pins 30 (referred to as "golden fingers"), and a plurality of PCI test pins. 4〇 (Ten 201007182 PCI test pins in this embodiment). Each PCI test pin 40 includes a signal pin J and a ground pin GND. The signal pins J of the ten PCI test pins are bus command/biter enable pin C/BE, PCI cycle frame pin FRAME, PCI master ready signal pin IRDY, PCI target ready signal Pin TRDY, PCI clock signal pin CLOC, voltage pin VCC, stop signal pin STOP, three address/data multiplexed pins AD0, ADI, AD2. The bus command/bytes allow pin C/BE, PCI week
赢期幀引腳FRAME、PCI主控準備好訊號引腳IRDY、PCI ❺ * 目標準備好訊號引腳TRDY、時脈訊號引腳CLOC、電壓 引腳VCC、停止訊號引腳STOP、三個位址/資料複用引腳 ADO、ADI、AD2分別對應連接該PCI介面晶片1〇之匯流 排命令/位元組允許引腳、PCI週期幀引腳、PCI主控準備 好訊號引腳、PCI目標準備好訊號引腳、時脈訊號引腳、 電壓引腳、停止訊號引腳、三個位址/資料複用引腳，每一 PCI測試引腳40中之接地引腳GND均與該PCI介面晶片 ❿10之接地引腳連接。本實施方式中，每一 PCI測試引腳之 訊號引腳J之一侧設一三角形標示，以與接地引腳GND區 分。 該PCI介面晶片10與PCI接腳30對應連接，該PCI 介面測試卡之PCI接腳30用於插接一待測主機板（未示 出）上之對應PCI插槽，以使該PCI介面測試卡上之PCI 介面晶片10與該待測主機板進行通訊。該PCI測試引腳 40用於電性接觸一電子測試設備（如示波器）之探針以透 過該電子測試設備對該待測主機板之PCI插槽中之時脈、 201007182 •重定、中斷、資料、位址等訊號之參數進行測量。 • 本實施方式中，該PCI介面晶片10設於該PCI介面 測試卡之中央位置並靠近頂邊，該pCI接腳3〇設於該Pd 面測4卡之底邊位置並置於右侧。該十個pci測試引腳 40設置於該pCI介面晶片10之週圍，且每—pci測試引 腳40之旁邊皆標示有相對應之訊號引腳之名稱。該 介面晶片10及該PCI接腳30可以根據實際需要設置於該 ❹PCI介面測試卡之其他位置。 測試時，將該PCI介面測試卡透過該等PCI接腳3〇 插接在該待測主機板之PCI插槽上，將該示波器之探針接 觸到要測量之PCI測試引腳40之訊號引腳J(如時脈引腳） 上，上電啟動該待測主機板，此時該示波器上顯示出訊號 引腳J之波形，根據該波形即可判斷該訊號引腳J對應之 訊號（如時脈訊號）是否符合PCI規範。當需要測試其他 訊號引腳J時’首先關閉該待測主機板，然後將該示波器 β之探針接觸到待測訊號引腳Ji，其測試原理與測試該時 脈引腳之測試原理相同，這裡不再贅述。 本發明之PCI介面測試卡上設置複數PCI訊號引腳及 相對應之接地引腳之方法供示波器探針使用，相對習知技 術直接應用PCI擴展卡焊接延長線之測試方法，本發明消 除了測試點不準確引起之測量誤差及延長線之使用引起之 汛號失真，從而保證了測試精確度；該PCI介面測試卡上 之pci δίΐ號中之時脈、重定、中斷、資料、位址等訊號均 有明顯地標示出來，避免了測試過程中測試人員需要透過 201007182 線路圖來確認訊號引腳，從而提高了測試效率，而且在今 PCI介面測試卡上設置複數PCi訊號引腳之方法避免了在 測試，備上多次料而造成設備損壞，節約了測試成本。 綜上所述，本發明符合發明專利要件，爰依法提出專 利申請。惟，以上所述者僅為本發明之具體實施方式，舉 凡熟悉本案技藝之人士，在爰依本發明精神所作之等效修 飾或變化’皆應涵蓋於以下之申請專利範圍内。Win frame pin FRAME, PCI master ready signal pin IRDY, PCI ❺ * Target ready signal pin TRDY, clock signal pin CLOC, voltage pin VCC, stop signal pin STOP, three addresses /Data Multiplexing Pins ADO, ADI, and AD2 are respectively connected to the bus interface of the PCI interface chip. The bus enable command/bit tuple enable pin, PCI cycle frame pin, PCI master ready signal pin, PCI target preparation Good signal pin, clock signal pin, voltage pin, stop signal pin, three address/data multiplexed pins, ground pin GND in each PCI test pin 40 and the PCI interface chip ❿10 ground pin connection. In this embodiment, one side of the signal pin J of each PCI test pin is provided with a triangular mark to distinguish it from the ground pin GND. The PCI interface chip 10 is connected to the PCI pin 30. The PCI pin 30 of the PCI interface test card is used for plugging a corresponding PCI slot on a motherboard (not shown) to be tested. The PCI interface chip 10 on the card communicates with the motherboard to be tested. The PCI test pin 40 is used for electrically contacting a probe of an electronic test device (such as an oscilloscope) to pass the electronic test device to the clock slot of the PCI slot of the motherboard to be tested, 201007182 • Reschedule, interrupt, data The parameters of the signal such as the address are measured. In the embodiment, the PCI interface chip 10 is disposed at a central position of the PCI interface test card and adjacent to the top edge. The pCI pin 3 is disposed at a bottom edge of the Pd surface 4 card and is disposed on the right side. The ten pci test pins 40 are disposed around the pCI interface chip 10, and the name of the corresponding signal pin is indicated next to each of the pci test pins 40. The interface chip 10 and the PCI pin 30 can be disposed at other locations of the PCI interface test card according to actual needs. During the test, the PCI interface test card is inserted into the PCI slot of the motherboard to be tested through the PCI pins 3, and the probe of the oscilloscope is touched to the signal of the PCI test pin 40 to be measured. On the foot J (such as the clock pin), the host board to be tested is powered on. At this time, the waveform of the signal pin J is displayed on the oscilloscope, and the signal corresponding to the signal pin J can be judged according to the waveform (eg Whether the clock signal is in compliance with the PCI specification. When it is necessary to test other signal pins J, 'first close the motherboard to be tested, and then touch the probe of the oscilloscope β to the signal pin to be tested, the test principle is the same as the test principle for testing the clock pin. I won't go into details here. The method for setting a plurality of PCI signal pins and corresponding ground pins on the PCI interface test card of the present invention is used by the oscilloscope probe, and the test method for directly applying the PCI expansion card soldering extension line is compared with the prior art, and the invention eliminates the test. The measurement error caused by the inaccuracy of the point and the nickname distortion caused by the use of the extension line ensure the test accuracy; the clock, reset, interrupt, data, address and other signals in the pci δ ΐ ΐ on the PCI interface test card It is clearly marked to avoid the testers need to confirm the signal pin through the 201007182 circuit diagram, which improves the test efficiency. Moreover, the method of setting multiple PCi signal pins on the PCI interface test card avoids Test, spare multiple materials and cause equipment damage, saving test costs. In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only for the specific embodiments of the present invention, and those skilled in the art will be able to devise the equivalent modifications or variations in the spirit of the present invention.
【圖式簡單說明】 圖1為本發明PCI介面測試卡之較佳實施方式之示意 圖。 【主要元件符號說明】 PCI介面晶片10 PCI接腳30BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic view of a preferred embodiment of a PCI interface test card of the present invention. [Main component symbol description] PCI interface chip 10 PCI pin 30
PCI測試引腳40 訊號引腳JPCI test pin 40 signal pin J
接地引腳 GNDGround pin GND