CN107345986A - A kind of impedance detecting method of De- embedding mode - Google Patents
A kind of impedance detecting method of De- embedding mode Download PDFInfo
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- CN107345986A CN107345986A CN201710470142.8A CN201710470142A CN107345986A CN 107345986 A CN107345986 A CN 107345986A CN 201710470142 A CN201710470142 A CN 201710470142A CN 107345986 A CN107345986 A CN 107345986A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/28—Measuring attenuation, gain, phase shift or derived characteristics of electric four pole networks, i.e. two-port networks; Measuring transient response
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2822—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere of microwave or radiofrequency circuits
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- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Tests Of Electronic Circuits (AREA)
- Measurement Of Resistance Or Impedance (AREA)
Abstract
The invention discloses a kind of impedance detecting method of De- embedding mode, comprise the following steps, 1, hardware prepare, 2nd, coherence measurement, 3, determine that microstrip line removes panel, 4, determine the installation electric capacity of chip, 5th, determine that final testing impedance removes panel, 6, measurement, this series of steps.Long invention replaces original cycle using high frequency probe test chip impedance and expensive method of testing, the substantially three day time in the method cycle of the S parameter provided in the present invention, greatly reduce the cycle of radio frequency chip Impedance measurement, method of testing in the present invention it also avoid the test limitation of rf probe needle point spacing fixation, and reduce the cost of testing impedance.
Description
Technical field
The present invention relates to a kind of detection method, specifically a kind of impedance detecting method of De- embedding mode.
Background technology
As the progress of semiconductor technology and the rapid development of information industry, RF/Microwave semiconductor device application are more next
It is more extensive, therefore the concern of measurement during design to device parameters all the more.Not only the designer of chip needs to know how precisely
The parameter for measuring chip, the user of chip also is intended to that accurate parameter can be obtained.In the S parameter of Microwave Net
The measurement of measurement chips parameter inherently runs into chip bonding lines with the measurement error caused by transmission line.Also have at present
Special unit designs corresponding rf probe fixture test chip parameter, bibliography (1, a kind of be directed to modular probe S
The calibration method of parameter amplitude versus frequency characte；2nd, a kind of calibration method of microwave device standard sample of photo) there is respective method, still
These test rf probes itself have chip testing PAD apart from limitation, be in addition equipped with the chip test probe cycle compared with
Costly, so cause production design cycle and cost all increases long and price, and the efficiency of design declines.
It is low and can be in the method for the corresponding S parameter of test chip to design a kind of shorter cost of general cycle, it appears outstanding
To be important.
The content of the invention
It is an object of the present invention to provide a kind of impedance detecting method of De- embedding mode, this method cycle, shorter cost was low simultaneously
And can be in the method for the corresponding S parameter of test chip.
In order to solve the above-mentioned technical problem, the technical solution adopted by the present invention is：
A kind of impedance detecting method of De- embedding mode, comprises the following steps：
(1) hardware prepares：
Bonding pcb boards needed for test；
(2) coherence measurement：
The chip COB that bonding is completed is measured, record compares its S11 file, observes its consistency；Carried according to survey side is sent
The tag sensitivity situation of confession, uniformity test should select appropriate power points；
(3) determine that microstrip line removes panel
Using the pcb plate consistent with chip bonding, the higher small capacitances of precision are fixed on pcb with the mode of welding
On, measure its S11 using net point and preserve S1P files；Measurement goes panel both-end parameter and preserves S2P files；According to going embedding calculation
Method, computing is carried out to S1P files using S2P files, obtains corresponding capacitance value；Selection is measured as more closest to capacitance
Go panel carry out microstrip line go it is embedding；
(4) the installation electric capacity of chip is determined
Measure the accurate capacitors and use the element S11 parameters of bonding modes, and save as corresponding S1P files；Make
Panel is gone to remove installation electric capacity that is embedding, and calculating actual chips to it with what is determined in 3；
(5) determine that final testing impedance removes panel
Embedding computing is carried out to the bonding plates of the electric capacity, from go it is embedding after for the electric capacity go panel to enter chip
Row it is final go it is embedding；
(6) measure
Chip after having bound obtains S1P files and to finally going panel to carry out De- embedding meter in step 5
Calculate, you can draw the impedance value of chip.
Preferably, the step hardware prepares：Embedding microstrip line pcb board is removed needed for test, this standard used removes panel
Numbering is A4-A10, and its micro-strip line length is 660-780mil, stepping 20mil.
The beneficial effects of the invention are as follows：
Long invention replaces original cycle using high frequency probe test chip impedance and expensive test side
Method, the substantially three day time in method cycle of the S parameter provided in of the invention, greatly reduce radio frequency chip Impedance measurement
Cycle, the method for testing in the present invention it also avoid the test limitation of rf probe needle point spacing fixation, and reduce resistance
The cost of anti-test.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description.
Fig. 1 is present invention connection diagram in kind.
Fig. 2 is present invention connection diagram in kind.
Fig. 3 is simulation algorithm schematic diagram one of the present invention.
Fig. 4 is simulation algorithm schematic diagram two of the present invention.
Fig. 5 is simulation algorithm schematic diagram three of the present invention.
Fig. 6 is simulation algorithm schematic diagram four of the present invention.
Fig. 7 is simulation algorithm schematic diagram five of the present invention.
Fig. 8 is that the present invention removes embedding microstrip line pcb board schematic diagram.
Fig. 9 is coherence measurement schematic diagram in method of testing of the present invention.
Embodiment
Embodiments of the invention are described in detail below in conjunction with accompanying drawing, but the present invention can be limited by claim
Fixed and covering multitude of different ways is implemented.
As shown in figs 1-9, wherein, 1- vector network analyzers, 2- transmission cables, 3- samples, 4- cables conversion connect
Mouthful, 5-SMA adapters A, 6- video transmission line, 7-PCB binding PAD, 8- chip bonding lines, the binding of 9- chip under test PAD, 10-
PAB test circuit plates, 11- chips to be measured, 12-SMA adapters B, 13- different length microstrip line.
A kind of impedance detecting method of De- embedding mode, comprises the following steps：
(1) hardware prepares：
Bonding pcb boards needed for test；
(2) coherence measurement：
The chip COB that bonding is completed is measured, record compares its S11 file, observes its consistency；Carried according to survey side is sent
The tag sensitivity situation of confession, uniformity test should select appropriate power points；
(3) determine that microstrip line removes panel
Using the pcb plate consistent with chip bonding, the higher small capacitances of precision are fixed on pcb with the mode of welding
On, measure its S11 using net point and preserve S1P files；Measurement goes panel both-end parameter and preserves S2P files；According to going embedding calculation
Method, computing is carried out to S1P files using S2P files, obtains corresponding capacitance value；Selection is measured as more closest to capacitance
Go panel carry out microstrip line go it is embedding；
(4) the installation electric capacity of chip is determined
Measure the accurate capacitors and use the element S11 parameters of bonding modes, and save as corresponding S1P files；Make
Panel is gone to remove installation electric capacity that is embedding, and calculating actual chips to it with what is determined in 3；
(5) determine that final testing impedance removes panel
Embedding computing is carried out to the bonding plates of the electric capacity, from go it is embedding after for the electric capacity go panel to enter chip
Row it is final go it is embedding；
(6) measure
Chip after having bound obtains S1P files and to finally going panel to carry out De- embedding meter in step 5
Calculate, you can draw the impedance value of chip.
Preferably, the step hardware prepares：Embedding microstrip line pcb board is removed needed for test, this standard used removes panel
7 altogether, numbering A4-A10, each standard goes to panel both ends to set SMS, and its micro-strip line length is 660-780mil, stepping
20mil。
Wherein go the basic principle of embedding operation method：
1st, the De- embedding simulation algorithm of single port S parameter
Single port DUT equivalent circuits such as Fig. 3：
2nd, the target of measurement is to obtain accurate S11.
Equivalent circuit such as Fig. 4 that test is added after parasitic microstrip line or Bonding lines first：
3rd, S parameter such as Fig. 5 of its test parasitic circuit of S22 is obtained by measurement：
4 obtain S33, S34, S43, S44.
According to S22 and S33, S34, S43, S44 calculates S11, and formula is：
5th, simulation result is illustrated in fig. 6 shown below：
Wherein S11 is DUT to be measured S parameter, and S11B is the parasitic S parameter of actual measurement circuit band；Because parasitism causes both
Between have certain deviation.
6th, such as Fig. 7 wherein S11A are the S parameter according to the S11B of the actual measurement DUT to be measured being calculated.It can be seen by upper figure
Go out, it is completely the same according to the S11A that above step is calculated and S11 that emulation obtains, show the errorless of calculating process
Physical connection mode：
The S parameter of sample is obtained, it is necessary to be changed by 1 vector network analyzer by 2 transmission cables and 4 signals
Interface (SMA heads) is connected on the adapter of 3 samples.But there was only the S of 7 chip to be measured as shown below in 3 samples
Parameter is only the test sample of real demand, therefore we need to exclude shadow caused by 5~10 pairs of samples in figure below
Ring.
During 3 samples are as shown below includes 5~11 parts, wherein the principal element for influenceing chip testing is 6
Radio-frequency transmission line and 8 chip bonding lines.
Two step De- embedding modes are broadly divided into the testing scheme of design 6 radio-frequency transmission lines are removed by De- embedding plate
With 8 chip bonding lines caused by influence --- (3) in test process are with (5) two steps.
The embodiments of the present invention described above are not intended to limit the scope of the present invention.It is any in the present invention
Spirit and principle within the modifications, equivalent substitutions and improvements made etc., should be included in the claim protection model of the present invention
Within enclosing.
Claims (2)
1. a kind of impedance detecting method of De- embedding mode, it is characterised in that comprise the following steps：
(1) hardware prepares
Bonding pcb boards needed for test；
(2) coherence measurement
The chip COB that bonding is completed is measured, record compares its S11 file, observes its consistency；According to sending what survey side provided
Tag sensitivity situation, uniformity test should select appropriate frequency and power points；
(3) determine that microstrip line removes panel
Using the pcb plate consistent with chip bonding, the higher small capacitances of precision are fixed on pcb with the mode of welding, made
Its S11 is measured with net point and preserves S1P files；Measurement goes panel both-end parameter and preserves S2P files；According to embedding algorithm is removed, make
Computing is carried out to S1P files with S2P files, obtains corresponding capacitance value；Choose measure for more closest to capacitance go it is embedding
Plate progress microstrip line goes embedding；
(4) the installation electric capacity of chip is determined
Measure the accurate capacitors and use the element S11 parameters of bonding modes, and save as corresponding S1P files；In 3
Determine to go panel to go it embedding, and calculate the installation electric capacity of actual chips；
(5) determine that final testing impedance removes panel
Embedding computing is carried out to the bonding plates of the electric capacity, from go it is embedding after for the electric capacity go panel to chip carry out most
Whole going is embedding；
(6) measure
Chip after having bound obtains S1P files and to finally going panel to carry out De- embedding calculating in step 5, you can
Draw the impedance value of chip.
2. the impedance detecting method of De- embedding mode according to claim 1, it is characterised in that the step hardware is accurate
It is standby：Embedding microstrip line pcb board is removed needed for test, it is A4-A10 that this standard used, which goes panel numbering, and its micro-strip line length is
660-780mil, stepping 20mil.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710470142.8A CN107345986B (en) | 2017-06-20 | 2017-06-20 | Impedance testing method in de-embedding mode |
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| CN201710470142.8A CN107345986B (en) | 2017-06-20 | 2017-06-20 | Impedance testing method in de-embedding mode |
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| CN107345986B CN107345986B (en) | 2020-03-03 |
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Cited By (6)
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| CN109633273A (en) * | 2018-11-30 | 2019-04-16 | 上海无线电设备研究所 | One kind being used for open-cell load impedance test macro and its method |
| CN110298086A (en) * | 2019-06-12 | 2019-10-01 | 深圳市一博科技股份有限公司 | A kind of emulation mode for testing cabling DUT performance |
| CN110958765A (en) * | 2019-12-18 | 2020-04-03 | 深圳宝龙达信创科技股份有限公司 | Printed circuit board and detection system and detection method thereof |
| CN112462178A (en) * | 2020-11-17 | 2021-03-09 | 海光信息技术股份有限公司 | Test structure and test method for S parameter of chip socket |
| CN112798863A (en) * | 2020-12-30 | 2021-05-14 | 西北核技术研究所 | Totally-enclosed and calibratable magnetic ring impedance measurement clamp and magnetic ring impedance measurement method |
| CN113671352A (en) * | 2021-08-26 | 2021-11-19 | 上海集成电路技术与产业促进中心 | Automatic matching type chip sensitivity testing device and method |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109633273A (en) * | 2018-11-30 | 2019-04-16 | 上海无线电设备研究所 | One kind being used for open-cell load impedance test macro and its method |
| CN109633273B (en) * | 2018-11-30 | 2021-06-04 | 上海无线电设备研究所 | Open-hole load impedance test system and method |
| CN110298086A (en) * | 2019-06-12 | 2019-10-01 | 深圳市一博科技股份有限公司 | A kind of emulation mode for testing cabling DUT performance |
| CN110958765A (en) * | 2019-12-18 | 2020-04-03 | 深圳宝龙达信创科技股份有限公司 | Printed circuit board and detection system and detection method thereof |
| CN110958765B (en) * | 2019-12-18 | 2021-07-30 | 深圳宝新创科技股份有限公司 | Printed circuit board and detection system and detection method thereof |
| CN112462178A (en) * | 2020-11-17 | 2021-03-09 | 海光信息技术股份有限公司 | Test structure and test method for S parameter of chip socket |
| CN112798863A (en) * | 2020-12-30 | 2021-05-14 | 西北核技术研究所 | Totally-enclosed and calibratable magnetic ring impedance measurement clamp and magnetic ring impedance measurement method |
| CN113671352A (en) * | 2021-08-26 | 2021-11-19 | 上海集成电路技术与产业促进中心 | Automatic matching type chip sensitivity testing device and method |
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