CN113671352A - Automatic matching type chip sensitivity testing device and method - Google Patents
Automatic matching type chip sensitivity testing device and method Download PDFInfo
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- CN113671352A CN113671352A CN202110985997.0A CN202110985997A CN113671352A CN 113671352 A CN113671352 A CN 113671352A CN 202110985997 A CN202110985997 A CN 202110985997A CN 113671352 A CN113671352 A CN 113671352A
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- 230000035945 sensitivity Effects 0.000 title claims abstract description 47
- 238000012360 testing method Methods 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 12
- 230000005540 biological transmission Effects 0.000 claims description 17
- 238000010521 absorption reaction Methods 0.000 claims description 8
- 238000004891 communication Methods 0.000 claims description 7
- 238000003466 welding Methods 0.000 abstract description 3
- 239000003990 capacitor Substances 0.000 abstract description 2
- 238000005259 measurement Methods 0.000 abstract description 2
- 239000000523 sample Substances 0.000 description 18
- 238000013461 design Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000004088 simulation Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000002847 impedance measurement Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2822—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere of microwave or radiofrequency circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
Abstract
The invention discloses an automatic matching type chip sensitivity testing device and method, and relates to the field of chip testing. The invention replaces the mode of estimating the measurement sensitivity by using a manual welding capacitor matching circuit, and does not need to make a matching circuit by measuring impedance, thereby improving the accuracy of measuring the sensitivity of the chip and saving the time for trying to weld and match.
Description
Technical Field
The invention relates to the field of chip testing, in particular to an automatic matching type chip sensitivity testing device and method.
Background
With the rapid expansion of the domestic semiconductor chip industry, the application of radio frequency/microwave semiconductor chips is more and more extensive, and domestic passive RFID chip design companies are more and more. The most important parameter of such radio frequency/microwave semiconductor chips is chip sensitivity, and a common sensitivity measurement method is to directly test the lowest power that the chip can respond to after matching the impedance of the chip. However, the impedance designed for such a chip is different from the actual impedance of the chip produced by the actual tape-out, which will cause the sensitivity of the chip not to match with the impedance designed, but only to be measured by a network analyzer equipped with a high-precision probe station. Even if the measured impedance is the actual impedance value of the chip, the actual impedance value cannot be directly used for designing a matching circuit so as to measure the sensitivity of the chip. Because the chip can be used only by bonding a gold wire or a copper wire with certain length and sensitivity in the using process, the originally designed impedance and the actually measured impedance only have reference value, and finally the matching circuit matches the circuit to a proper state in a continuous trial and error mode, and then the lowest power which can be responded by the chip is measured to determine the sensitivity of the chip. The method for measuring the actual sensitivity of the chip is not the actual sensitivity of the chip, and when the impedance of the chip is measured, probes which are consistent with the PAD pitch of the chip are required to be customized to measure the impedance of the chip, and the customization is very expensive and takes a long time.
At this time, it is important to design a general method that has a short period and a low cost and can test the chip sensitivity.
A paper is disclosed in the prior art: an automatic impedance matching method of a passive ultrahigh frequency RFID electronic tag is shown as an automatic impedance matching network design block diagram in figure 1. However, in the technology, mainly, the negative feedback type automatic adjustment is performed on the radio frequency matching circuit in the chip simulation design stage, although the chip sensitivity can be simulated, the simulation result is influenced by different degrees due to different tape-out processes, so that the difference between the actual sensitivity value and the simulation result is large.
There is also a paper disclosed in the prior art: the automatic Impedance matching network design block diagram shown in FIG. 2 is provided for the sensing and Impedance Measurements on UHF RFID Transponder Chips. However, in the technology, mainly the chip is mainly in the actual test stage of the sensitivity and the impedance of the RFID chip, firstly, the system required by the technology is more complex, and the chip matching circuit is also realized by adopting 2 tuner; secondly, the system can not realize automatic matching, and is time-consuming and labor-consuming.
Disclosure of Invention
Based on the technical problems in the background art, the invention provides an automatic matching type chip sensitivity testing device and method with short period and low cost in order to replace the sensitivity calibration method with the difference between the design simulation result and the actual test result.
The technical scheme adopted by the invention is as follows:
the automatic matching type chip sensitivity testing device is characterized by comprising a vector network analyzer, a transmission cable, an impedance tuner and a control computer, wherein the vector network analyzer is connected with the impedance tuner through the transmission cable, the impedance tuner is in communication connection with the control computer through a first network cable, the control computer is in communication connection with the vector network analyzer through a second network cable, and the impedance tuner is connected to a tested sample.
Further, the automatic matching type chip sensitivity testing device is characterized in that the tested sample comprises a chip to be tested and a matching device, and the chip to be tested is installed on the matching device and then connected with the impedance tuner.
Further, an automatic matching formula chip sensitivity testing arrangement, a serial communication port, matching device includes that SMA adapter, radio frequency transmission line, PCB bind PAD, quilt survey chip and bind PAD, PAB test circuit board, SMA adapter, PCB bind PAD and install respectively on the PAB test circuit board, SMA adapter and PCB bind and are connected through radio frequency transmission line between the PAD, PCB binds PAD and is connected through chip binding line with quilt survey chip binding PAD, quilt survey chip binding PAD is installed on the chip that awaits measuring, SMA adapter be used for with the impedance modulation is connected.
An automatic matching type chip sensitivity testing method is characterized by comprising the following steps:
(1) connecting the vector network analyzer with the impedance tuner through a transmission cable, and then connecting the vector network analyzer to a sample to be tested to obtain the chip sensitivity of the sample to be tested;
(2) the impedance tuner is set into different matching circuits by a control computer through a first network cable, and the matching circuits are set into all points which can be set on a Smith chart through the control computer;
(3) the vector network analyzer records the lowest reflected energy and the corresponding frequency point, transmits the lowest reflected energy and the corresponding frequency point to a computer through a second network cable and records the lowest energy absorption parameter under the specified chip working frequency, and fixes the parameter value of the impedance tuner as the lowest energy absorption parameter through a control computer;
(4) the impedance tuner and the tested sample are taken as a whole, and the chip to be tested is in a matching state;
(5) the sensitivity of the whole impedance tuner and the tested sample is tested by using a sensitivity testing device.
The invention has the advantages that:
the invention replaces the mode of estimating the measurement sensitivity by using a manual welding capacitor matching circuit, and does not need to make a matching circuit by measuring impedance, thereby improving the accuracy of measuring the sensitivity of the chip and saving the time for trying to weld and match.
The chip sensitivity testing method provided by the invention has the period of half a day, so that the period of testing the chip sensitivity by the radio frequency chip is greatly reduced, the testing method does not need to measure and measure the impedance through the fixed length of the radio frequency probe, and the cost is greatly reduced.
Drawings
Fig. 1 is a block diagram of an automatic impedance matching network in an automatic impedance matching method of a passive ultrahigh frequency RFID tag.
FIG. 2 is a block diagram of an automatic Impedance matching network design in the paper sensing and Impedance Measurements on UHF RFID Transponder Chips.
FIG. 3 is a schematic diagram of an automatic matching chip sensitivity testing apparatus according to the present invention.
FIG. 4 is a schematic view of a device for matching a sample to be tested.
In the figure: the device comprises a vector network analyzer 1, a transmission cable 2, an impedance tuner 3, a tested sample 4, a first network cable 5, a control computer 6 and a second network cable 7;
the device comprises an SMA adapter 8, a radio frequency transmission line 9, a PCB binding PAD10, a chip binding line 11, a tested chip binding PAD12, a PAB test circuit board 13 and a chip 14 to be tested.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Example 1.
As shown in fig. 3 and 4, an automatic matching chip sensitivity testing device includes a vector network analyzer 1, a transmission cable 2, an impedance tuner 3, and a control computer 6, wherein the vector network analyzer 1 is connected to the impedance tuner 3 through the transmission cable 2, the impedance tuner 3 is in communication connection with the control computer 6 through a first network cable 5, the control computer 6 is in communication connection with the vector network analyzer 1 through a second network cable 7, and the impedance tuner 3 is connected to a sample 4 to be tested.
The tested sample 4 comprises a chip 14 to be tested and a matching device, and the chip 14 to be tested is installed on the matching device and then connected with the impedance tuner 3.
The matching device comprises an SMA adapter 8, a radio frequency transmission line 9, a PCB binding PAD10, a tested chip binding PAD12 and a PAB test circuit board 13, the SMA adapter 8 and the PCB binding PAD10 are respectively installed on the PAB test circuit board 13, the SMA adapter 8 is connected with the PCB binding PAD10 through the radio frequency transmission line 9, the PCB binding PAD10 is connected with a tested chip binding PAD12 through a chip binding line 11, the tested chip binding PAD12 is installed on a chip 14 to be tested, and the SMA adapter 8 is used for being connected with the impedance tuner 3.
An automatic matching type chip sensitivity testing method comprises the following steps:
(1) connecting the vector network analyzer 1 with the impedance tuner 3 through the transmission cable 2, and then connecting the vector network analyzer to the tested sample 4 to obtain the chip sensitivity of the tested sample 4;
(2) the impedance tuner 3 is set into different matching circuits by the control computer 6 through the first network cable 5, and the matching circuits are set into all points which can be set on the Smith chart through the control computer 6;
(3) the vector network analyzer 1 records the lowest reflected energy and the corresponding frequency points, transmits the lowest reflected energy and the corresponding frequency points to the computer 6 through the second network cable 7 for recording, records the parameters of the impedance tuner 3 when the energy absorption is lowest under the working frequency of the specified chip, and fixes the parameter values of the impedance tuner 3 as the parameters when the energy absorption is lowest through the control computer 6;
(4) the impedance tuner 3 and the tested sample 4 are taken as a whole, and the chip 14 to be tested is in a matching state;
(5) the sensitivity of the whole of the impedance tuner 3 and the sample 4 to be measured is measured by using a sensitivity measuring instrument.
In the invention, the conventional method is improved, the mode of welding capacitance and inductance is changed into the mode of using an impedance coordinator (Tuner)3 as a matching circuit, the energy absorption of all working frequencies is taken out by traversing a Smith chart, the parameter of the point with the best absorption is set in the impedance coordinator 3, the impedance coordinator 3 and the sample 4 to be measured are used as a whole to carry out sensitivity calibration, and the sensitivity at the moment is the actual sensitivity of the chip.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.
Claims (4)
1. The automatic matching type chip sensitivity testing device is characterized by comprising a vector network analyzer (1), a transmission cable (2), an impedance tuner (3) and a control computer (6), wherein the vector network analyzer (1) is connected with the impedance tuner (3) through the transmission cable (2), the impedance tuner (3) is in communication connection with the control computer (6) through a first network cable (5), the control computer (6) is in communication connection with the vector network analyzer (1) through a second network cable (7), and the impedance tuner (3) is connected to a tested sample (4).
2. The automatic matching type chip sensitivity testing device according to claim 1, wherein the tested sample (4) comprises a chip (14) to be tested and a matching device, and the chip (14) to be tested is mounted on the matching device and then connected with the impedance tuner (3).
3. The automatic matching type chip sensitivity testing device according to claim 2, wherein the matching device comprises an SMA adapter (8), a radio frequency transmission line (9), a PCB binding PAD (10), a tested chip binding PAD (12) and a PAB testing circuit board (13), the SMA adapter (8) and the PCB binding PAD (10) are respectively installed on the PAB testing circuit board (13), the SMA adapter (8) and the PCB binding PAD (10) are connected through the radio frequency transmission line (9), the PCB binding PAD (10) and the tested chip binding PAD (12) are connected through a chip binding line (11), the tested chip binding PAD (12) is installed on the chip (14) to be tested, and the SMA adapter (8) is used for being connected with the impedance tuner (3).
4. A method for testing an automatic matching type chip sensitivity testing device according to any one of claims 1 to 3, comprising the following steps:
(1) connecting the vector network analyzer (1) with the impedance tuner (3) through the transmission cable (2), and then connecting the vector network analyzer to the sample (4) to be detected to obtain the chip sensitivity of the sample (4) to be detected;
(2) the impedance tuner (3) is set into different matching circuits by a control computer (6) through a first network cable (5), and the matching circuits are set into all points which can be set on a Smith chart through the control computer (6);
(3) the vector network analyzer (1) records the lowest reflected energy and corresponding frequency points, transmits the lowest reflected energy and corresponding frequency points to the computer (6) through a second network cable (7) for recording, records the parameters of the impedance tuner (3) when the energy absorption is lowest under the working frequency of the specified chip, and fixes the parameter values of the impedance tuner (3) as the parameters when the energy absorption is lowest through the control computer (6);
(4) the impedance tuner (3) and the tested sample (4) are taken as a whole, and the chip (14) to be tested is in a matching state;
(5) the sensitivity of the whole of the impedance tuner (3) and the sample (4) to be tested is measured by using a sensitivity measuring device.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110985997.0A CN113671352A (en) | 2021-08-26 | 2021-08-26 | Automatic matching type chip sensitivity testing device and method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110985997.0A CN113671352A (en) | 2021-08-26 | 2021-08-26 | Automatic matching type chip sensitivity testing device and method |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102236069A (en) * | 2010-04-27 | 2011-11-09 | 中芯国际集成电路制造(上海)有限公司 | Test system and test method |
| CN104375011A (en) * | 2014-11-04 | 2015-02-25 | 中国电子科技集团公司第四十一研究所 | Random impedance testing circuit and method for vector network analyzer material testing |
| CN104991124A (en) * | 2015-07-06 | 2015-10-21 | 上海斐讯数据通信技术有限公司 | Characteristic impedance calibration system and test method |
| CN105759194A (en) * | 2016-05-12 | 2016-07-13 | 中国电子科技集团公司第四十研究所 | Method for quickly positioning optimal impedance point of semiconductor impedance test based on tuner |
| CN107026325A (en) * | 2017-06-06 | 2017-08-08 | 中国电子技术标准化研究院 | A kind of RFID antenna impedance matching attachment means |
| CN107345986A (en) * | 2017-06-20 | 2017-11-14 | 上海集成电路技术与产业促进中心 | A kind of impedance detecting method of De- embedding mode |
| CN109412685A (en) * | 2018-09-14 | 2019-03-01 | 武汉电信器件有限公司 | A kind of semiconductor chip detection device and detection method |
-
2021
- 2021-08-26 CN CN202110985997.0A patent/CN113671352A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102236069A (en) * | 2010-04-27 | 2011-11-09 | 中芯国际集成电路制造(上海)有限公司 | Test system and test method |
| CN104375011A (en) * | 2014-11-04 | 2015-02-25 | 中国电子科技集团公司第四十一研究所 | Random impedance testing circuit and method for vector network analyzer material testing |
| CN104991124A (en) * | 2015-07-06 | 2015-10-21 | 上海斐讯数据通信技术有限公司 | Characteristic impedance calibration system and test method |
| CN105759194A (en) * | 2016-05-12 | 2016-07-13 | 中国电子科技集团公司第四十研究所 | Method for quickly positioning optimal impedance point of semiconductor impedance test based on tuner |
| CN107026325A (en) * | 2017-06-06 | 2017-08-08 | 中国电子技术标准化研究院 | A kind of RFID antenna impedance matching attachment means |
| CN107345986A (en) * | 2017-06-20 | 2017-11-14 | 上海集成电路技术与产业促进中心 | A kind of impedance detecting method of De- embedding mode |
| CN109412685A (en) * | 2018-09-14 | 2019-03-01 | 武汉电信器件有限公司 | A kind of semiconductor chip detection device and detection method |
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