201003063 六、發明說明： 【發明所屬之技術領域】 本發明係關於平板顯示器（flat panel display ; FPD )中之缺陷 之檢測，更具體而言，係關於利用正面照明以檢測平板顯示器内 之缺陷。 【先前技術】 於平板液晶（liquid crystal ; LC )顯示器之製造過程中，大且透 明之薄玻璃板係作為一基板以供沉積薄膜電晶體（thin film transistor ; TFT)陣列。通常，將數個獨立之TFT陣列包含於一 個玻璃基板内’即稱為TFT面板。或者，一主動矩陣（active matrix ) 式LCD (或稱為AMLCD )涵蓋如下種類之顯示器：其於每一畫 素或次畫素處利用一電晶體或二極體，因此這種玻璃基板亦可稱 為AMLCD面板。亦可利用有機LED ( organic LED ; 0LED)技 術製作平板顯示器’並且儘管通常係製作於玻璃上，然亦可製作 於塑膠基板上。 TFT圖案沉積係實施於許多階段，其中於各該階段中，按照一 預定圖案沉積一特定材料（例如金屬、氧化銦錫（indium tin oxide ; ITO)、晶體矽、非晶矽等）於一先前層（或玻璃）之頂部。各該 階段通常包括若干步驟，例如沉積、遮罩、蝕刻、剝離等。 於各該階段以及各該階段之不同步驟中，可能出現許多製造缺 陷’該些缺陷將影響LCD產品最終之電性及/或光學性能。此等缺 陷包括但不限於ITO 112中之金屬突起11〇、金屬116中之ITO 突起114、所謂的缺口（ mouse bite ) 118、開路120、電晶體124 4 201003063 令之短路122、異物顆粒126及畫素下之殘留物128，如第】圖所 不。晝素128下之非晶石夕（a_si )殘留物可能係因餘刻不足 (under-etching)或微影（丨ith〇graphy)問題而引起。其它缺陷則 包括遮罩問題、過餘刻（〇ver etching )等。 儘管TFT沉積製程受到嚴格控制，然缺陷之發生係無法避免 的。這將會限制產品良率並不利地影響製造成本。通常，在關鍵 的沉積製程步驟之後，利用一或多個自動光學檢驗（aut〇mated optical inspection ; AOI)系統檢驗TFT陣列，並利用一電·光檢驗 機（electro-optical inspection machine)，例如由位於 5970 Optical Court, San Jose, California, 95138，USA 之 photon Dynamics (Orbotech公司）所製造之電-光檢驗機，且亦稱為陣列測試儀或 陣列檢查儀（array checker ; AC )測試做好的TFT陣列。 非晶石夕缺陷特別麻煩’乃因其對光較為敏感；亦即，非晶^夕於 一暗態中，將具有作為一絕緣體之作用；但當其暴露於光時，則 具有作為一導體之作用。事實上，其薄膜電阻Rsi將隨著光的強度 而降低。第4圖即繪示此種相關性。薄膜電阻與光強度之相關性 則意味著，當以不同程度暴露於光時，因缺陷而引起之畫素電壓 變化亦將產生變化。因此，若於最終FPD組件完成之前未檢測到 缺陷’則最終使用者將很容易注意到該缺陷，此因當FPD在正常 工作中’該缺陷係暴露於顯示器之背光中所致。因此，檢測此等 缺陷係迫切需要的。 遺憾的是，習知技術未能提供一種適於在面板製造之不同階段 中，有效地檢測因非晶矽殘留物形成LCD面板之缺陷之方法。 5 201003063 【發明内容】 本發明係應用於多種方法及系統，其能實質消除與lcd面板顯 示器中會形成缺陷之非晶矽殘留物之檢測相關聯之—或多種前段 所述之問題及其它問題。 根據本發明之一態樣，係提供一種用於檢測—受試面板之缺陷 之系統。該系統包含一正面照明子系統，用以傳送一正面照明光 束至該受試面板。該正面照明光束具有改變該等缺陷之電氣特性 之能力，俾利於該等缺陷之檢測。該系統更包含—檢測子系統， 用以根據該等缺陷之該等已改變的電氣特性，檢測該等缺陷。該 系統中所用之該正面照明光束係脈衝激發且其持續時間及強度係 最佳化，俾該等缺陷之檢測最大化並使偽缺陷（falsedefec〇之被 檢測最小化。此外，該正面照明光束具有與該等缺陷之最大吸收 光學特性匹配之一波長。 根據本發明之另一態樣，係提供一種用於檢測一受試面板之缺 陷之系統。該系統包含一正面照明子系統，用以傳送一正面照明 光束至該受試面板。該正面照明光束具有改變該等缺陷之電氣特 性之能力，俾利於該等缺陷之檢測。該系統更包含一檢測子系統’ 用以根據該等缺陷之該等已改變之電氣特性’檢測該等缺陷。該 前述檢測子系統更包括一電壓成像光學裝置’用以形成可指示該 受試面板之一空間電壓分佈之一影像。該等缺陷係根據該形成之 影像被檢測之。於該系統中，該前述正面照明子系統係整合於該 電壓成像光學裝置之一光學路徑内。此外，該正面照明光束具有 與該等缺陷之最大吸收光學特性匹配之一波長。 6 201003063 再根據本發明之另一態樣，係提供一種用於檢測一受試面板之 缺陷之系統。該系統包含一正面照明子系統，用以傳送一正面照 明光束至該受試面板《該正面照明光束具有改變該等缺陷之電氣 特性之能力，俾利於該等缺陷之檢測。該系統更包含—檢測子系 統’用以根據該等缺陷之該等已改變之電氣特性，檢測該等缺陷。 該檢測子系統包括一電壓成像光學裝置，用以形成可指示該受試 面板之一空間電壓分佈之一影像。該等缺陷係根據該形成之影像 被檢測之。該正面照明子系統係設置於該電壓成像光學裝置之一 光學路徑外。此外，該正面照明光束具有與該等缺陷之最大吸收 光學特性匹配之一波長。 與本發明相關之其它態樣將於下文說明甲部份地提及，並且根 據該說明將部份地顯而易見，或者可藉由實踐本發明而知悉。本 發明之悲樣可藉由下文詳細說明及隨附申請專利範圍中所具體描 述之元件以及各種元件和態樣之組合而實現和達成。 應理解，上文及下文說明僅係為例示性及闡釋性說明，並非旨 在以任何方式限制本發明或其應用。 【實施方式】 於下文說明中，將參照附圖，其中相同之功能元件將賦予相同 之編號。上述附圖係以舉例說明方式而非限定方式顯示根據本發 明原理之具體實施職㈣方案。該等實施方㈣被足夠詳細地 加以描述，以使此技術領域射財知識者㈣實踐本發明，並 且應理解，亦刊料讀施方㈣且可對各種元件作出結構上 之改4及/或替代，此並不背離本發明之範圍及精神。因此，下文 201003063 詳細說明不應被限定本㈣之敘述。此外，本文所述之本發明之 各實施例可被實施為_專用硬體或軟體與硬體之—組合之形式。 技術V貝域具有通常知識者將瞭解陣列測試儀可利用在例如 美國專利公告號4,983,91 1、5,〇97,2()1及5.，奶中所述之電壓 成像測試裝置及方法’以辨識液晶顯示ϋ之缺陷，該等美國專利 以引用方式併人本文中。利用特定圖案電驅動液晶顯示器内之畫 素’例如’在美國專利公告號5,235刀2及5,459,41〇中所述，該 等美國專利之全文以引用方式倂人本文中。因液晶顯示器係由畫 素陣列構成，故當電驅動液晶顯示器時，與缺陷相關聯之某些晝 素電I·生行為將不同於正常晝素，因而可利用一電壓成像感測器 及相關影像處理軟體偵測此等差別。藉由利用不同驅動圖案之組 σ可推斷出第i圖所繪示之諸多缺陷的類型及位置。 然而，於ITO中，具有a_Si殘留物128之缺陷畫素在利用標準 陣列測試方法之陣刺試中，將非常難以檢測。具有__ a_si殘留 τ旦素200之一實例的剖視圖顯示於第2圖中。晝 。構00形成於一玻璃才反2〇2上。閘極絕緣體崩係設置於玻 璃上接著錢覆一:貝料金屬線2〇6，然後再沉積呈一透明導電材 料，例如氧化域（indium tin 〇xide ; ϊτ〇) 21〇形式之該畫素特 徵。最後，沉積-純化層，例如氣化石夕（siUc〇n ; _χ ) 2〇8。 非晶石夕或資料金屬殘留物212可得以保留，並以圖形方式被表示 為隨後位於ITO層下方之線特徵（⑹㈣⑽）之一延伸部。殘 留物212與畫素（IT0) 21〇間之交疊區域μ形成具有寄生電容 CP之—電容器216。 8 201003063 第3圖係為一畫素中之a_Si殘留物之一等效電路圖。於本實例 中：201003063 VI. Description of the Invention: [Technical Field] The present invention relates to the detection of defects in flat panel displays (FPD), and more particularly to the use of front lighting to detect defects in flat panel displays. [Prior Art] In the manufacturing process of a liquid crystal (LC) display, a large and transparent thin glass plate is used as a substrate for depositing a thin film transistor (TFT) array. Typically, a plurality of individual TFT arrays are contained within a single glass substrate, i.e., referred to as a TFT panel. Alternatively, an active matrix LCD (or AMLCD) covers a display that uses a transistor or a diode at each pixel or sub-pixel, so the glass substrate can also It is called AMLCD panel. It is also possible to fabricate a flat panel display using organic LED (organic LED; 0LED) technology and, although usually fabricated on glass, can be fabricated on a plastic substrate. The TFT pattern deposition is carried out in a plurality of stages in which a specific material (for example, metal, indium tin oxide (ITO), crystalline germanium, amorphous germanium, etc.) is deposited in a predetermined pattern in each of the previous stages. The top of the layer (or glass). Each of these stages typically includes several steps, such as deposition, masking, etching, stripping, and the like. At various stages and at various stages of the various stages, many manufacturing defects may occur. These defects will affect the ultimate electrical and/or optical performance of the LCD product. Such defects include, but are not limited to, metal protrusions 11 in ITO 112, ITO protrusions 114 in metal 116, so-called mouse bite 118, open circuit 120, transistor 124 4 201003063 short circuit 122, foreign particles 126 and Residue 128 under the picture, as shown in the figure. The amorphous australis (a_si) residue under the alizarin 128 may be caused by under-etching or lithography. Other defects include masking problems, 〇ver etching, and so on. Although the TFT deposition process is strictly controlled, the occurrence of defects is unavoidable. This will limit product yields and adversely affect manufacturing costs. Typically, after a critical deposition process step, the TFT array is inspected using one or more automated optical inspection (AOI) systems, and an electro-optical inspection machine is utilized, for example by An electro-optical inspection machine manufactured by photon Dynamics (Orbotech) of 5970 Optical Court, San Jose, California, 95138, USA, also known as array tester or array checker (AC) test TFT array. Amorphous stone defects are particularly troublesome because they are more sensitive to light; that is, amorphous, in a dark state, will function as an insulator; but when exposed to light, it has a conductor The role. In fact, its sheet resistance Rsi will decrease with the intensity of the light. Figure 4 shows this correlation. The dependence of the sheet resistance on the light intensity means that when exposed to light to varying degrees, the pixel voltage change due to defects will also change. Therefore, if the defect is not detected before the final FPD component is completed, the end user will easily notice the defect because the FPD is in normal operation and the defect is exposed to the backlight of the display. Therefore, detecting such defects is urgently needed. Unfortunately, conventional techniques fail to provide a method for effectively detecting defects in the formation of LCD panels due to amorphous germanium residues in different stages of panel fabrication. 5 201003063 SUMMARY OF THE INVENTION The present invention is applied to various methods and systems that substantially eliminate the problems associated with the detection of amorphous ruthenium residues that may form defects in an LCD panel display - or a variety of problems described in the preceding paragraphs and other problems . According to one aspect of the invention, a system for detecting defects in a panel under test is provided. The system includes a front illumination subsystem for transmitting a front illumination beam to the panel under test. The front illumination beam has the ability to alter the electrical characteristics of the defects to facilitate detection of such defects. The system further includes a detection subsystem for detecting the defects based on the changed electrical characteristics of the defects. The front illumination beam used in the system is pulsed and its duration and intensity are optimized, maximizing the detection of such defects and minimizing false defects (falsedefec〇 is detected. In addition, the front illumination beam Having one wavelength that matches the maximum absorption optical characteristics of the defects. According to another aspect of the invention, a system for detecting defects in a panel is provided. The system includes a front illumination subsystem for Transmitting a front illumination beam to the panel to be tested. The front illumination beam has the ability to change the electrical characteristics of the defects to facilitate detection of such defects. The system further includes a detection subsystem 'based on the defects The altered electrical characteristics 'detect the defects. The aforementioned detection subsystem further includes a voltage imaging optics' for forming an image indicative of a spatial voltage distribution of the panel under test. The formed image is detected. In the system, the foregoing front illumination subsystem is integrated in the voltage imaging optical device In addition, the front illumination beam has one wavelength that matches the maximum absorption optical characteristic of the defects. 6 201003063 In accordance with another aspect of the present invention, a defect for detecting a panel is provided. System. The system includes a front illumination subsystem for transmitting a front illumination beam to the panel to be tested. The front illumination beam has the ability to change the electrical characteristics of the defects to facilitate detection of such defects. The inclusion-detection subsystem is configured to detect the defects based on the changed electrical characteristics of the defects. The detection subsystem includes a voltage imaging optics for forming a spatial voltage indicative of the panel being tested Distributing one of the images. The defects are detected based on the formed image. The front illumination subsystem is disposed outside an optical path of the voltage imaging optics. In addition, the front illumination beam has the largest defect The absorption optical characteristic matches one of the wavelengths. Other aspects related to the present invention will be referred to in the following section And the invention will be apparent from the description, or may be understood by the practice of the invention. The invention is to be considered as illustrative and illustrative, and is not intended to limit the invention or its application in any way. [Embodiment] In the following description, reference will be made to The same reference numerals are given to the same elements in the accompanying drawings, which are illustrated by way of example and not of limitation. FIG. It is to be understood that the skilled person in this technical field (4) has practiced the present invention, and it should be understood that it is also possible to make a structural change and/or substitution of various components without departing from the scope and spirit of the present invention. Therefore, the detailed description of 201003063 below should not be limited to the description of (4). Furthermore, the various embodiments of the invention described herein can be implemented in the form of a dedicated hardware or a combination of software and hardware. The V-domains of the art have a general knowledge of an array tester that can be utilized in, for example, U.S. Patent Publication Nos. 4,983, 91, 5, 〇97, 2() 1 and 5. 'To identify defects in liquid crystal display, such U.S. patents are incorporated herein by reference. The use of a particular pattern to electrically drive a pixel in a liquid crystal display is described in, for example, U.S. Patent No. 5,235, the entire disclosure of which is incorporated herein by reference. Since the liquid crystal display is composed of a pixel array, when the liquid crystal display is electrically driven, some of the elemental electric currents associated with the defect will be different from the normal element, and thus a voltage imaging sensor and related can be utilized. The image processing software detects these differences. The type and location of the many defects depicted in Figure i can be inferred by using the set σ of different drive patterns. However, in ITO, defective pixels with a_Si residue 128 would be very difficult to detect in a burst test using standard array test methods. A cross-sectional view of one example having __ a_si residual τ dans 200 is shown in FIG. Oh. The structure 00 is formed on a glass to be reversed 2〇2. The gate insulator is disintegrated on the glass and then covered with a bead wire 2〇6, and then deposited as a transparent conductive material, such as an oxidized domain (indium tin 〇xide; ϊτ〇) 21 之 in the form of the pixel feature. Finally, a deposition-purification layer, such as gasification fossil (siUc〇n; _χ) 2〇8. Amorphous or material metal residue 212 may be retained and graphically represented as an extension of one of the line features ((6)(d))(10)) that is subsequently located beneath the ITO layer. The overlap region μ between the residue 212 and the pixel (IT0) 21 turns to form a capacitor 216 having a parasitic capacitance CP. 8 201003063 Figure 3 is an equivalent circuit diagram of one of the a_Si residues in a pixel. In this example:
Cp ksiN*S〇* Arearesidue/dgate siN 方程式 1Cp ksiN*S〇* Arearesidue/dgate siN Equation 1
Cst — ksiN*s〇*Wpixe|Wst/dpasssiN 方程式 2 其中，cp係為寄生電容，KsiN係為SiN之介電常數如係為空氣 中之介電常數（permittivity c〇nstant)，W—丨係為畫素之寬度， 而Wst係為儲存電容器之寬度（電容為G 及^ s,N分 別係為鈍化層及閘極至SiN層之厚度，Arearesidues為所討論之殘 留物缺陷的面積。 於陣歹丨測減中，將施加一驅動電壓至液晶板，並藉由一電壓成 像感測器可觀察到畫素響應。對於例如資料金屬殘留物及a_si等 缺陷，可使用正-負（PN)驅動圖案，其中資料電壓於影像擷取之 月’J下降至負值。於此圖案中，資料電壓之下降將存在於IT〇資料 線交疊區域之晝素上引起一電壓降。若該資料電壓降係為△%，則 晝素電壓降AVP可表示為下式： AVP= AVd —^P 1-exp -_ 古名口斗、】 .Cs/ + CpJ[ (Rsi{Cst + cP)) 方矛王式 3 其中，cp係為ITO-資料線殘留物交疊區域之寄生電容，係為 儲存電谷益之電谷，並且RSi係為非晶石夕之薄膜電阻。 方程式1及3顯示關於a_Si之二關鍵點。第一關鍵點在於，寄 生電容係為缺陷大小（Ar隱sidue)之-函數。第二關鍵點則為 薄膜電阻RSi之指數相關性。在絕緣體狀態（不存在光）中， 201003063 Τ'非常尚（處於千彳思歐姆/平方之數量級），因而由方程式3可見， 當不暴露於光時’ Δνρ近似等於△vACp/D，且其具有最大值。 因Cp<cst’故當不暴露於光時之最大將非常小。因此，在不 存在光時’該等缺陷將不容易被檢測之。端視交疊面積而定，根 據一習知之64灰階驅動方案，此變化可造成數個灰階之偏移量。 -連續灰階間之電壓步階約為5〇毫伏特。因該值非常小而無法將 缺陷與正常晝素區分開。 此外’由於與大小相關（方程式Ο，甚至在暴露於光時，亦可 能無法檢測到極小之a_Si缺陷。 儘s利用AOI可發現某些a_Si缺陷，並且可利用習知缺陷檢測 技術’精由AC來檢測某些缺陷。然而，無法在早期辨識出此等缺 陷之-較大比例’而只能於TFT_LCD單元組件已製成後，即於液 晶板已劃分成面板並被組裝成模組很長時間後方可被檢測到。於 單元測試中，一背光模組在被電驅動時，將提供TFT-LCD用於顯 不影像之光源。a-Si之光敏感特性使其可於該等條件下，被檢測 出具有此種缺陷。然而，期望於單元組裝步驟之前儘早捕捉到該 等缺陷，並且有效地於陣列檢驗步驟中捕捉到該等缺陷，乃因利 用—雷射修復系統可相對容易地移除殘留物。此外，在製造製程 之早期階段並且在單元組裝之前檢測該等缺陷，冑可節約與組裝 製程及與所需濾色鏡玻璃相關聯之成本。 LCD陣列檢驗設備一般不具有外部光源，因而』殘留物之檢 测非常困難。由Photon Dynamics，Inc，（現已被〇rb〇tech Ud收購） 製造之AC47xU 口口口系列之陣列測試儀包含一短》皮長背光燈，該短 10 201003063 波長背光燈係與一對分軸型系統（_ aXis-type system)之一透 明夹盤結合使用’其，檢驗區域以及該夹盤，將被限制至單一調 變器列。然而，於夹盤覆蓋整個玻璃大小之門架型系統（gamrytypeCst — ksiN*s〇*Wpixe|Wst/dpasssiN Equation 2 where cp is the parasitic capacitance, and KsiN is the dielectric constant of SiN such as the dielectric constant in the air (permittivity c〇nstant), W—丨The width of the pixel, and Wst is the width of the storage capacitor (the capacitance is G and ^ s, N is the thickness of the passivation layer and the gate to SiN layer respectively, and Arearesidues is the area of the residue defect in question. In the 减 measurement, a driving voltage is applied to the liquid crystal panel, and a pixel response can be observed by a voltage imaging sensor. For defects such as data metal residues and a_si, positive-negative (PN) can be used. Driving the pattern, wherein the data voltage drops to a negative value in the month of image capture. In this pattern, the drop in the data voltage will cause a voltage drop on the element of the overlapping area of the IT data line. The voltage drop is Δ%, then the voltage drop AVP of the halogen can be expressed as: AVP = AVd —^P 1-exp -_ Ancient name, 】 .Cs/ + CpJ[ (Rsi{Cst + cP)) Fangmaowang type 3, where cp is the parasitic capacitance of the overlapping area of the ITO-data line residue. Electric power storage valley valley benefit of, and non-RSi-based thin-film resistor of the spar evening. Equations 1 and 3 show the key points about a_Si. The first key point is that the parasitic capacitance is a function of the defect size. The second key point is the exponential correlation of the sheet resistance RSi. In the insulator state (the absence of light), 201003063 Τ 'very good (on the order of thousands of ohms / square), and thus can be seen from Equation 3, Δνρ is approximately equal to ΔvACp/D when not exposed to light, and its Has the maximum value. Because of Cp<cst', the maximum will be very small when not exposed to light. Therefore, these defects will not be easily detected when there is no light. Depending on the overlap area, this variation can result in several grayscale offsets, according to a conventional 64 grayscale drive scheme. - The voltage step between successive gray levels is approximately 5 〇 millivolts. Because this value is very small, it is impossible to distinguish defects from normal elements. In addition, 'because of the size (the equation Ο, even when exposed to light, it may not be able to detect a small a_Si defect. Some AOI can be used to find some a_Si defects, and can use the known defect detection technology 'fine AC To detect certain defects. However, it is impossible to identify the large-scale of these defects at an early stage. Only after the TFT_LCD unit assembly has been fabricated, the liquid crystal panel has been divided into panels and assembled into a long module. After the time is detected, in the unit test, a backlight module will provide a TFT-LCD for displaying the light source when it is electrically driven. The light sensitivity of a-Si makes it possible under these conditions. Having such defects is detected. However, it is desirable to capture such defects as early as possible prior to the unit assembly step, and to effectively capture such defects in the array inspection step, as the use of the laser repair system can be relatively easy Residue removal. In addition, these defects are detected early in the manufacturing process and prior to unit assembly, saving the cost associated with the assembly process and the desired color filter glass LCD array inspection equipment generally does not have an external light source, so the detection of residues is very difficult. The AC47xU mouth-and-mouth series array tester manufactured by Photon Dynamics, Inc. (now acquired by 〇rb〇tech Ud) contains one Short" leather long backlight, the short 10 201003063 wavelength backlight is combined with a transparent chuck of a pair of split-type systems (_ aXis-type system), which, the inspection area and the chuck, will be limited to Single modulator column. However, the chuck covers the entire glass-sized gantry type system (gamrytype
SyS_)中，亦將需要相關之背光燈藉由移動（例如，單行運動） 或靜態地（例如，完全覆蓋）覆蓋整個玻璃大小，可能既不切實 際亦不具成本效益。 其中’對於a-Si殘留物覆蓋TFT之閘極金屬的某些情形，背光 將無法穿過該閘極特徵，因而難以檢測閘極上之a_si殘留物。在 某二/、有几餘TFT之畫素設計中，具體而言，在冗餘TFT被電性 隔離而不連接至該畫素之情形中，此係為頻繁出現之缺陷。當㈣ 殘留物橋接畫素TFT與冗餘TFT時，將會影響效能，因而被視為 一種缺陷。a-Si殘留物會增大Cgd (閘極_汲極寄生電容）。由於 間極-汲極電容器搞合效應，當閘極關斷（電壓擺動：時， 畫素電壓降低。此被稱為反衝效應（kick_backeffect)。晝素電壓 降Δνρ可表示為： △Vp = AVg * cgd / (Cgd+Cst+Ck)。 方程式 4 其中，Clc係為單元電容（僅存在於單元驅動情形中）。將晝素 TFT連接至冗餘TFT之閘極a-Si殘留物會增大閘極-汲極電容，此 又會進一步增大晝素電壓下降。 其它非電壓成像陣列測試儀，例如利用電子束之測試儀，可藉 由以電子喷射缺陷、使電子積聚於該缺陷區域中來檢測a Si殘留 物。電子之此種積聚會增大a-Si導電率，進而使相關之成像方法 可檢測到缺陷。 11 201003063 根據本發明之一實施例，提供正面照明裝置及方法，俾能夠在 單元組裝步驟之前，於陣列測試步驟中檢測a-Si殘留物缺陷。同 時’具體而言，檢測一 TFT陣列單元之閘極絕緣體上之a_Si殘留 物。此領域具有通常知識者將瞭解，在TFT陣列測試中，當不暴 露於光時’ a-Si具有高電阻率。另一方面，當a-si殘留物係以光 照射時’其電阻率將減小，轉而改變TFT陣列單元之電特性。此 時了利用電壓成像光學系統（v〇ltage imaging 〇ptical syStem ; VI〇S )進行檢測，例如由位於5970 Optical Court, San Jose,In SyS_), it will also be necessary to cover the entire glass size by moving (e.g., single line motion) or statically (e.g., full coverage), which may be neither practical nor cost effective. In some cases where the a-Si residue covers the gate metal of the TFT, the backlight will not pass through the gate feature, making it difficult to detect the a_si residue on the gate. In the case of a certain TFT design with a few TFTs, specifically, in the case where the redundant TFT is electrically isolated and not connected to the pixel, this is a frequently occurring defect. When (4) the residue bridges the pixel TFT and the redundant TFT, it will affect the performance and is considered as a defect. The a-Si residue increases the Cgd (gate 汲 汲 parasitic capacitance). Due to the effect of the interpole-drain capacitor, when the gate is turned off (voltage swing: the pixel voltage is reduced. This is called the kick_back effect. The voltage drop Δνρ can be expressed as: △Vp = AVg * cgd / (Cgd + Cst + Ck) Equation 4 where Clc is a cell capacitor (only in the case of cell driving). The gate a-Si residue connecting the halogen TFT to the redundant TFT increases Large gate-drain capacitance, which in turn increases the voltage drop of the pixel. Other non-voltage imaging array testers, such as those using an electron beam tester, can accumulate electrons in the defect area by electron ejection defects. The a Si residue is detected to increase the a-Si conductivity, thereby enabling the associated imaging method to detect defects. 11 201003063 According to an embodiment of the invention, a front illumination device and method are provided,俾 can detect a-Si residue defects in the array test step before the unit assembly step. At the same time, 'specifically, detect the a_Si residue on the gate insulator of a TFT array unit. It will be appreciated that in TFT array testing, 'a-Si has a high resistivity when not exposed to light. On the other hand, when the a-si residue is illuminated by light, its resistivity will decrease, and The electrical characteristics of the TFT array unit are changed. At this time, the voltage imaging optical system (v〇ltage imaging 〇ptical syStem; VI〇S) is used for detection, for example, by 5970 Optical Court, San Jose,
California, 95138，USA 之 Photon Dynamics ( Orbotech 公司）所 製造者。此種系統之一實施例詳述於前述美國專利公告號 4,983,91 1、5，()97,2G1及5,124,635 t，該等美國專利將以引用方 式併入本文中。相應地，於本發明之一實施例中，俾使TFT陣列 單元暴露於光脈衝之照明中，於·彻5進行之測試中，影響該 TFT面板之頂面。 根據一實施例’該正面照明係沿著與在VIOS中用於電壓成像之 照明相同之路徑前進。於一實施例中， 部份中執行VI0S照明。於一 於可見波長範圍之該紅色Produced by Photon Dynamics (Orbotech) of California, 95138, USA. An embodiment of such a system is described in detail in the aforementioned U.S. Patent Nos. 4,983, 91, 5, (), 97, 2, G, and 5,124, 635, each of which is incorporated herein by reference. Accordingly, in one embodiment of the present invention, the TFT array unit is exposed to the illumination of the light pulse, and in the test conducted by the R. 5, the top surface of the TFT panel is affected. According to an embodiment, the front illumination is advanced along the same path as the illumination for voltage imaging in the VIOS. In one embodiment, the VI0S illumination is performed in the portion. The red in the visible wavelength range
因檢測缺陷（a-Si)之能 12 201003063 力係為光強度之函數，故該TFT單元之該正面照明必須適當地均 勻並在檢测區域中可重複。此外，用於檢測a_Si之該照明及光學 裝置不得干擾VIOS測試儀查找TFT單元中可出現之其它類型缺 ^之功此’某些缺陷已闡述於上文中。 於本發明之一實施例中，提供一種用於L C D陣列測試過程中產 生對該受試面板之該LCD結構之正面照明之系統，以利於檢測因 感光製造之缺陷，例如該LCD畫素之結構上殘留之a_Si殘留物（例 如閘極結構上或附著至資料線上之a_Si殘留物）。於本發明系統 之一實施例中，用光照射面板之正面，該光所具有之一波長不同 於在該VIOS中用於電壓成像之光之波長。此係出於至少數種原 因。首先，在該VIOS照明中所用之光具有不容許有效地檢測a Si 殘召物及/或其匕感光缺陷之波長。第二，該Vios調變器之設計 使得S亥VIOS中用於電壓成像之光幾乎完全被該前述調變器之薄 膜反射，因而不會到達該面板。相應地，用於正面照明之光係被 選擇成fb致此（改變電特性）該a-Si殘留物並被該薄臈透射。 最後，整個系統包括用於分離該二光束並防止用於正面照明之 光干擾該VIOS成像（其利用該前述各種光波長之差異）之方法（第 5圖所示之低通濾鏡510)。 本發明雙波長光學照明系統500之一實施例之一圖式顯示於第 5圖中。該圖式僅供用於例示目的，而不應被視為限制本發明之範 圍。如第5圖所示，為一基於電壓成像光學系統（VI〇s)之陣列 檢驗及測試系統結合使用，一雙波長照明裝置（dual wavelength illuminator;DWI)512被置於VIOS照明裝置之光學柱中。該VI〇s 13 201003063 照明裝置之構造描述於例如美國專利公告號5，124,635中，該美國 專利之全文將以引用方式倂入本文中。 如第5圖所示’雙波長照明裝置512將藍光照明裝置502所產 生之一藍光504 (例如’具有455奈米之波長，a-Si缺陷對該波長 尤其敏感）耦合至與由用於缺陷成像之紅光照明裝置5〇1所產生 之可見光505(例如波長為630奈米）相同之光路徑中。具體而言， 第8圖顯示a-Si之典型光吸收曲線8〇1，其顯示波長為衫允爪之 光802 ’將對於a-Si而言具有最高之吸收係數。 該前述二種不同波長光束之耦合係在雙波長照明裝置512内利 用分色鏡（分光鏡）503完成，分色鏡503實質透射藍色光束504 並實質反射紅色光束505,以產生具有二種波長之組合光束。如熟 習此項技藝者將瞭解，不同波長光束之耦合可按許多其它方式達 成，其中某些方式將在下文參照本發明之其它實施例予以說明。 因此，第5圖所示雙波長照明裝置512之具體設計不應被視為限 制本發明之範圍。 请重新參見第5圖所示之系統’在穿過分色鏡（分光鏡）5〇3 後，共線之藍色及紅色光束被分光鏡5〇6反射並隨後穿過透鏡組 507’透鏡組507用於光學調變器5〇8及受試面板5〇9上達成所期 望之照明分佈圖案。 如上所述，在本發明之各種其它或替代實施例中，可按數種不 同方式達成調變器5〇8及受試面板5〇9之雙波長共線照明。舉例 ；實細*例中’可採用多重波長發光二極體（light emitting diode ’ LED) ’其中可限制該等多重波長二極體之波長選擇。於 14 201003063 此種配置中，僅需制-個採用該前述多重波長發光二極體之昭 明裝置以取代例如光源5〇2,同時從該照明系統中去 501及分色鏡503。 於再一替代實施例中，可在同樣可用於取代光源502之單—光 源中，使複數單波長紅色LED與複數單波長藍色咖在空間上散 置於一起。同樣，於此種配置中，需要自該照明系統中去除第二 光源則及分色鏡503。然‘應注意者，於此種利用二種不同波 長之散置LED之配置中，該照明之均勾度可有所折衷。 於一實施例中，VI0S調變器具有一薄膜515，薄膜515在 工間上緊罪4又4面板之欠试LCD結構，並位於調變^ 5〇8之表 面上’薄膜515具有專門選取之光學特性，俾使照明裝置5〇1所 產生之紅光被其反射、但照明裝置地所產生之藍光係被薄膜Μ 透射。调變器5G8根據受試面板之頂面（第5圖）上之電位 分佈，調變薄膜5U所反射之紅光之強度，其中受試面板在 空間上’緊靠著調變器，之薄膜放置。在被薄膜反射後，經調 變之紅光穿過透鏡組507、分光鏡5〇6及低通濾鏡51〇。在穿過低 通濾鏡510後，反射之紅光撞擊至CCD裝置511之感光元件上， 以利用該等感光元件形成受試面板之—影像。為防止用於照射⑽ 殘留物之任何藍光干擾VIOS之CCD影像感測器511，CCD裝置 511設置有一低通濾鏡510。該濾鏡之光學透射特性被設計成大幅 衰減§亥藍光並容許該紅光無衰減地穿過。此可防止正面照明之藍 光到達CCD裝置511並干擾受試面板5〇9之頂面上之電位所形成 之景> 像。應注意者，於本發明之一實施例中，該藍光僅用於改變 15 201003063 以使其更易於被VIOS檢測到，而不產 該a-Si殘留物之電特性 生缺陷本身之一影像。 利用電壓源513對受試面板5〇9之表面的受試Lcd結構施加 偏壓，同時利用電壓源514對調變器谓之頂面516 (帛5圖）施 加偏壓。於本發明之—實_中，該线之所有光學元件皆具有 適宜之光學塗層，以達成最佳之光透射及反射。應注意者，該二 長（藍色及紅色）之光之照明均勾度將類似，且通常於本發明 之實她例中，差距將不超過於約25%。典型之照明均句度之範 圍係’I於1〇%與15%之間。因此，帛5圖所示之本發明雙波長照 月概心及配置此約α a_Sl缺陷最敏感之波長照射㈣缺陷，但不 降低或干擾電壓成像測試（VI〇s)硬體之功能。 應注意者，本發明並不限於僅以紅光及藍光照射該調變器及該 文试面板。如本領域具有通常知識者將瞭解，係可選擇另一照明 光波長以獲得恰當吸收之a_Si殘留物，藉以充分地改變其電特性 以達成檢測並降低正面照明對VI〇s運作（其用於在受試面板上重 新形成一電壓分佈圖案）之干擾。 根據第6圖所示本發明雙波長照明概念之一第二替代實施例， 並且亦為與基於VI〇S之陣列檢驗及測試系統結合使用，將一環形 照明裝置601包含於調變器座600中。環形照明裝置6〇1係安裝 於調變器508上方，並且單波長（藍色或近似455奈米之波長） 光源603 (例如複數個LED)將位於該VIOS照明裝置之光學路徑 以外，以防止影像裁切。如在前段所述之第一實施例相同，調變 器508之薄膜（圖未繪示）透射藍光；並反射紅色照明裝置 16 201003063 所產生且為電壓成像調變器娜之功能所需的可見波長之光。光 源603形成照明圖案604。於本發明之-實施例中，安裝環601 之每一側承載4個LED 6G3 1而，此領域具有通常知識者將瞭 解y利用在女裝壞601 i，以任何恰當方式相間之任何其它適 宜數量之LED來獲得所期望之強度及照明均勾度。因此，本發明 係不限於照明裝置環6(H、調變器座6〇〇及光源⑷之所示佈局。 於本發明之各種實施例中，照明裝置環6〇1具有一正方形、矩形、 八邊形、圓形、橢圓形或其它適當形狀。光源㈣所產生之光穿 過調變器602，並昭兮為·>+工& > τ γ 艾’，、、射试面板之正面，以影響該受試面板上 a-Si殘留物之電特性。 此領域具有通常知識者將瞭解，視調變器508之面積大小而定， 於某些情形中，特別是當LED 603之數量相對較小時，相較參照 圖所述之雙波長照明裝置之實施例，在本實施例中可能更難 以獲得較佳之均勻度。然而，相較參照第5圖所述之雙波長照明 裝置之實施例所能達成者，將LED 603之數量增大至每側多於1〇 個（總共多於40個）可利於達成更大之照明均勻度及均勻度特性。 為於整個調變器區域範圍内達成最佳之均勻度，必須控制該led 之發光角度。如於此項技術中眾所習知，某些LED具有朗伯 (Lambertian)發光輪廓，因而以非常大之立體角發光，將不利於 獲得局照明均勻度之期望目標，乃因更多的光係被不均衡地發送 至該調變器中央。有數種替代解決方案可用於克服此種不足。於 一實施例中’利用專門之複數定向LED作為光源603並引導其照 明調變器508之最内部分。 17 201003063 於一替代實施例中’增設準直透鏡（collimating lens )或較佳地 將其光學耦合至每一通用LED ’以容納朗伯輪廓之擴展。用於將 準直透鏡耦合至LED之各種方法係於此技術領域中眾所習知。於 一實施例中，各該LED配備有其自身之準直透鏡。此等準直透鏡 有利於增強正面照明之均勻度。於又一實施例中，藉由於LED側 面增設一中性密度濾、光片（neutral density filter)而施加定向衰 滅。此外，可使用散光器以：（1)消除各該LED之空間不均一 性；及（2)提高組合LED分佈之總體照明均勻度。舉例而言， 於一實施例中，可利用由位於Torrance, California, USA之Luminit 公司（Physical Optics Corporation公司）製造和出售之散光器。 於一實施例中，可利用用於形成橢圓形輻射分佈之光束形成散 光器以提高正面照明均勻度。於相同或不同之實施例中，亦可利 用一光’弯曲或轉向膜以提高正面照明均勻度。 在第6圖中顯示之多光源配置中，用於對受試面板509表面之 a_Si殘留物提供正面照明之光源603係安裝於一單獨之安裝環 上，該安裝環係設置於第5圖所示雙波長照明系統上方、調變器 508之附近，其中第二光源整合於VIOS自身結構中，該多光源配 置之主要優點在於，在現有門架型系統上進行更新（retrofit)將 更為容易和廉價。此外，第6圖所示之發明概念可應用於需要均 勻周邊照明之缺陷檢測技術（例如基於電子束之檢測器，還可能 包括全接觸式探針測試儀）。然而，應注意者’如前面所述，電 子束檢測器不與藍光照射相容。 此技術領域具有通常知識者將瞭解’用於提供正面照明並包含 18 201003063 設置光源於調變器附近之系統配置可按不同於第6圖所示實施例 之諸多其它方式達成。因此，第6圖所示照明系統之特定具體設 計不應被視為限制本發明之範圍。 第7圖係為用於檢測平板顯示器内之缺陷之系統700之一方塊 示意圖，其採用本發明概念之實施例其中之一。本發明之系統包 含VIOS 702，其包括雙波長照明裝置703，雙波長照明裝置703 之一實例性實施例已參照第5圖闡述於上文中（元件512)。照明 裝置703所產生之一第一波長之光束（例如藍光）射向安裝於一 玻璃支架上之LCD面板701。照明裝置703所產生之一第二波長 之光束（例如紅色可見光）射向調變器705上，調變器705用以 透過一電一光傳感器（所述調變器）將承受偏壓之受試LCD面板 上之電場變換成空間調變光信號，該光信號受到調變器705之薄 膜（圖未示出）反射。反射光被透鏡系統704聚焦至CCD裝置7U， 由CCD裝置711在反射紅光中形成受試LCD面板之區域之影像， 所形成之影像可指示受試面板701上電位之分佈。實例性系統700 可更包括影像擷取/影像處理PC 709，用以自CCD裝置711接收 影像資料、利用所接收影像資料產生受試面板之影像並處理所產 生影像以辨識具缺陷之LCD細胞，包括此等缺陷細胞於受試面板 上之位置。可記錄該等缺陷之位置資訊以供進一步處理，例如以 修正所檢測之缺陷。 於本發明之一實施例中，VIOS 702係安裝於一可移動之X/Y/Z 平台總成706上，X/Y/Z平台總成706可在平台/10控制模組707 控制下移動。於本發明之另一實施例中，多於一個VIOS 702安裝 19 201003063 706上，俾利用不同之VIOS 7〇2同時檢驗該受 於同一 Χ/Υ/Ζ平台 試面板之不同區域 最後’設置測試信號圖案產生器710，以提供驅動電壓圖案至受 試LCD面板，藉以控制昭昍挞里 &利’、、、明裝置觸發並提供所需之偏壓至調變器。 應注意者’於本發明之—實施例中，正面照明系統可完全整合 於VI0S子系統中’而不叫何方式受上述檢測技術之限制，俾提 供最佳之吸收效率及照射均勺产 、耵巧9度。第ό圖所不之正面照明技術亦 可適用於根據電子束之檢測系統。然而，照射均勾度對於上文所 述及第5圖所示之雙波長照明裝置設計應尤其較佳，其中用於a_Si 致能之藍㈣循與該主f VI〇s照明光相同之光學路徑到達 器。 於本發明之-具體實施例中，該正面照明係脈衝激發，且其持 續時間及強度已最佳化以使相對於TFT畫素之錄缺陷檢測最大 化L言’正面照明光所具有之—波長與光敏缺陷之最大吸 收光學特性相匹配。於—具體實施例中，係利用波長小於销奈 米之藍光對a-Si殘留物實施正面照明。 2本發明之—實施财，為得到最佳之正Φ光效率，選擇用於 提高該非日日日秒殘留物之導電率之波長，使其與材料之吸收特性相 匹配。通常’ a-Si在低波長（藍光）範圍中具有一吸收邊緣參 見第8圖中之曲線80卜對於較大之波長（能量更低），吸收性急 劇下降，而對於較短之波長，吸收性則幾乎不變化。應注意者， 基於電子束之缺陷檢測與藍光之使用不相容，乃因其會於係用於 里測畫素電麼之二次電子檢測器中引起顯著量之雜訊。其原因有 20 201003063 二。首先，短波長之光子（例如藍光）較紅色波長之光子具有更 大之能® ’因此當其撞擊為該檢測電子所需之閃燦器·光電倍增器 (SdntiUat〇r-Ph〇tomuItipIier)時會產生多餘之雜訊信號。其^ 因一·人電子進入檢測器之能量可能受到電子及光子碰撞之影響， 故可存在更大之信號變化，進而有助於總體雜訊。 非晶石夕對紐波長之光較為敏感，因而於照射後產生移動之光電 子導致a-Si缺陷之導電率增加。於某些實施例中，選取具有"ο 奈米C或更短）波長之藍光’此部份係因為其具有相對更高之功 率，在a-Si中係可被更有效地吸收並且具有一更低之薄膜電阻。 第4圖例示在二種不同波長（47〇奈米（曲線4〇1)及53〇奈米（曲 線402))下’薄膜電阻與光強度之函數曲線圖。由該等曲線圖可 知’隨著強度之增加，該二波長中之較短者（4〇1)使電阻更快地 減小。因對應於較短波長之光之信號可更強，故較短波長光之使 用亦可達成較小尺寸缺陷之檢測（方程式1及3)。Due to the ability to detect defects (a-Si) 12 201003063 The force is a function of light intensity, so the front illumination of the TFT unit must be properly uniform and repeatable in the detection area. In addition, the illumination and optics used to detect a_Si must not interfere with the VIOS tester's ability to find other types of defects that may occur in the TFT unit. Some of the drawbacks are set forth above. In an embodiment of the present invention, a system for generating front illumination of the LCD structure of the panel under test during an LCD array test is provided to facilitate detection of defects caused by photosensitive manufacturing, such as the structure of the LCD pixel. Residual a_Si residue (such as a gate structure or a_Si residue attached to the data line). In one embodiment of the system of the present invention, the front side of the panel is illuminated with light having a wavelength different from the wavelength of the light used for voltage imaging in the VIOS. This is for at least several reasons. First, the light used in the VIOS illumination has a wavelength that does not allow for effective detection of the a Si remnant and/or its defects. Second, the Vios modulator is designed such that the light used for voltage imaging in the Shai VIOS is almost completely reflected by the film of the aforementioned modulator and thus does not reach the panel. Accordingly, the light system for front illumination is selected such that fb causes (changes in electrical characteristics) the a-Si residue to be transmitted by the thin crucible. Finally, the overall system includes a method (the low pass filter 510 shown in Figure 5) for separating the two beams and preventing the light for front illumination from interfering with the VIOS imaging (which utilizes the differences in the various wavelengths of light described above). One of the embodiments of one embodiment of the dual wavelength optical illumination system 500 of the present invention is shown in FIG. This drawing is for illustrative purposes only and should not be taken as limiting the scope of the invention. As shown in Figure 5, a dual wavelength illuminator (DWI) 512 is placed in the optical column of the VIOS illuminator for a combination of an array inspection and test system based on a voltage imaging optical system (VI〇s). in. The construction of the illuminating device is described in, for example, U.S. Patent No. 5,124,635, the entire disclosure of which is incorporated herein by reference. As shown in FIG. 5, the dual-wavelength illumination device 512 couples one of the blue light 504 generated by the blue illumination device 502 (eg, 'having a wavelength of 455 nm, the a-Si defect is particularly sensitive to the wavelength) to be used for defects The visible red light illumination device 5〇1 produces visible light 505 (eg, having a wavelength of 630 nm) in the same optical path. Specifically, Fig. 8 shows a typical light absorption curve 8〇1 of a-Si, which shows that the light 802' having a wavelength of the cap will have the highest absorption coefficient for a-Si. The coupling of the two different wavelength beams is performed by a dichroic mirror (beam splitter) 503 in the dual-wavelength illumination device 512. The dichroic mirror 503 substantially transmits the blue beam 504 and substantially reflects the red beam 505 to produce two types. A combined beam of wavelengths. As will be appreciated by those skilled in the art, the coupling of beams of different wavelengths can be achieved in a number of other ways, some of which are described below with reference to other embodiments of the invention. Therefore, the specific design of the dual-wavelength illumination device 512 shown in Figure 5 should not be construed as limiting the scope of the invention. Referring again to the system shown in Figure 5, after passing through the dichroic mirror (beam splitter) 5〇3, the collinear blue and red beams are reflected by the beam splitter 5〇6 and then passed through the lens group 507' lens group. 507 is used on the optical modulator 5〇8 and the panel 5〇9 to achieve the desired illumination distribution pattern. As noted above, in various other or alternative embodiments of the present invention, dual wavelength collinear illumination of modulator 5〇8 and panel 5〇9 can be achieved in a number of different ways. For example, a thin-wavelength light emitting diode 'LED' can be used to limit the wavelength selection of the multiple wavelength diodes. In this configuration, it is only necessary to make an illumination device using the aforementioned multi-wavelength light-emitting diode instead of, for example, the light source 5〇2, while removing the 501 and the dichroic mirror 503 from the illumination system. In still another alternative embodiment, a plurality of single-wavelength red LEDs can be spatially interspersed with a plurality of single-wavelength blue coffee in a single-light source that can also be used in place of light source 502. Also, in such a configuration, the second source and the dichroic mirror 503 need to be removed from the illumination system. However, it should be noted that in such a configuration using two different wavelengths of interspersed LEDs, the uniformity of the illumination can be compromised. In one embodiment, the VIOS modulator has a film 515 which is closely related to the under-test LCD structure of the 4 and 4 panels on the work surface and is located on the surface of the modulation film 5. The film 515 has a special selection. The optical characteristics are such that the red light generated by the illumination device 5〇1 is reflected by the red light, but the blue light generated by the illumination device is transmitted by the film. The modulator 5G8 modulates the intensity of the red light reflected by the film 5U according to the potential distribution on the top surface (Fig. 5) of the panel to be tested, wherein the panel under test is spatially 'close to the modulator, the film Place. After being reflected by the film, the modulated red light passes through the lens group 507, the beam splitter 5〇6, and the low-pass filter 51〇. After passing through the low pass filter 510, the reflected red light impinges on the photosensitive element of the CCD device 511 to form an image of the test panel using the photosensitive elements. To prevent any blue light used to illuminate the (10) residue from interfering with the VIOS CCD image sensor 511, the CCD device 511 is provided with a low pass filter 510. The optical transmission characteristics of the filter are designed to substantially attenuate the louver blue light and allow the red light to pass without attenuation. This prevents the blue light of the front illumination from reaching the CCD device 511 and interfering with the scene formed by the potential on the top surface of the test panel 5〇9. It should be noted that in one embodiment of the invention, the blue light is only used to change 15 201003063 to make it easier to detect by the VIOS without producing an image of the electrical characteristic of the a-Si residue itself. A voltage source 513 is used to bias the surface of the test Lcd of the surface of the panel 5 to 9 under test, while the voltage source 514 is used to bias the top surface 516 of the modulator (Fig. 5). In the present invention, all optical components of the wire have suitable optical coatings for optimum light transmission and reflection. It should be noted that the illumination of the two long (blue and red) lights will be similar, and usually in the case of the present invention, the difference will not exceed about 25%. The typical range of illumination degrees is between 1% and 15%. Therefore, the dual-wavelength illumination center of the present invention shown in Fig. 5 and the wavelength sensitive (4) which is most sensitive to the configuration of the α a_Sl defect are not degraded or interfere with the function of the voltage imaging test (VI〇s) hardware. It should be noted that the present invention is not limited to illuminating the modulator and the panel with only red and blue light. As will be appreciated by those of ordinary skill in the art, another illumination light wavelength can be selected to obtain a properly absorbed a_Si residue, thereby substantially altering its electrical characteristics to achieve detection and reducing front side illumination operation for VI〇s (which is used for The interference of a voltage distribution pattern is reformed on the panel under test. According to a second alternative embodiment of the dual wavelength illumination concept of the present invention shown in FIG. 6, and also for use with an array inspection and test system based on VI〇S, an annular illumination device 601 is included in the modulator mount 600. in. The ring illumination device 6〇1 is mounted above the modulator 508, and a single wavelength (blue or approximately 455 nm wavelength) source 603 (eg, a plurality of LEDs) will be located outside of the optical path of the VIOS illumination device to prevent Image cropping. As in the first embodiment described in the preceding paragraph, the film of the modulator 508 (not shown) transmits blue light; and reflects the visible color required by the red illumination device 16 201003063 and is a function of the voltage imaging modulator. Wave of light. Light source 603 forms an illumination pattern 604. In the embodiment of the invention, each side of the mounting ring 601 carries four LEDs 6G3 1 , and those skilled in the art will appreciate that any of the other suitable uses may be utilized in any suitable manner. A number of LEDs to achieve the desired intensity and illumination. Accordingly, the present invention is not limited to the illustrated layout of the illumination device ring 6 (H, modulator housing 6〇〇, and light source (4). In various embodiments of the invention, the illumination device ring 6〇1 has a square, rectangular, An octagonal shape, a circular shape, an elliptical shape, or other suitable shape. The light generated by the light source (4) passes through the modulator 602, and is described as ·>+工&> τ γ AI',,, test panel The front side to affect the electrical characteristics of the a-Si residue on the panel to be tested. It will be understood by those of ordinary skill in the art that depending on the size of the modulator 508, in some cases, particularly when the LED 603 When the number is relatively small, it may be more difficult to obtain better uniformity in this embodiment than the embodiment of the dual-wavelength illumination device described with reference to the figure. However, compared to the dual-wavelength illumination described with reference to Figure 5 Embodiments of the device can achieve that increasing the number of LEDs 603 to more than one turn per side (more than 40 in total) can be beneficial to achieve greater illumination uniformity and uniformity characteristics. To achieve the best uniformity within the area of the device, the LED must be controlled Illumination angles. As is well known in the art, certain LEDs have a Lambertian illumination profile and thus emit light at very large solid angles, which would be detrimental to the desired goal of achieving uniform illumination, but more A large number of light systems are sent unbalanced to the center of the modulator. There are several alternative solutions that can be used to overcome this deficiency. In one embodiment, 'use a dedicated complex directional LED as the light source 603 and direct its illumination modulator The innermost portion of 508. 17 201003063 In an alternative embodiment, 'a collimating lens is added or preferably optically coupled to each of the general purpose LEDs' to accommodate an extension of the Lambertian profile. Various methods of coupling a lens to an LED are known in the art. In one embodiment, each of the LEDs is equipped with its own collimating lens. These collimating lenses facilitate enhanced uniformity of frontal illumination. In another embodiment, the directional decay is applied by adding a neutral density filter to the side of the LED. In addition, a diffuser can be used to: (1) eliminate each of the LEDs. Spatial heterogeneity; and (2) improving the overall illumination uniformity of the combined LED distribution. For example, in one embodiment, it can be manufactured and sold by Luminit Corporation (Physical Optics Corporation), located in Torrance, California, USA. A astigmatism. In one embodiment, a diffuser can be formed using a beam of light for forming an elliptical radiation distribution to improve frontal illumination uniformity. In the same or different embodiments, a light 'bending or turning film can also be utilized. To improve the frontal illumination uniformity. In the multi-source configuration shown in Figure 6, the light source 603 for providing front illumination of the a_Si residue on the surface of the panel 509 is mounted on a separate mounting ring, the mounting ring It is disposed above the dual-wavelength illumination system shown in Figure 5, near the modulator 508. The second source is integrated into the VIOS structure. The main advantage of the multi-source configuration is that it is updated on the existing gantry system. (Retrofit) will be easier and cheaper. Furthermore, the inventive concept shown in Fig. 6 can be applied to defect detection techniques that require uniform peripheral illumination (e.g., electron beam based detectors, and may also include full contact probe testers). However, it should be noted that the electron beam detector is not compatible with blue light illumination as described above. Those skilled in the art will appreciate that the system configuration for providing front illumination and including 18 201003063 setting the source of light near the modulator can be accomplished in a number of other ways than the embodiment shown in FIG. Therefore, the specific design of the illumination system shown in Fig. 6 should not be construed as limiting the scope of the invention. Figure 7 is a block diagram of a system 700 for detecting defects in a flat panel display employing one of the embodiments of the inventive concept. The system of the present invention includes a VIOS 702 that includes a dual wavelength illumination device 703, an exemplary embodiment of which is described above with reference to Figure 5 (element 512). A light beam of a first wavelength (e.g., blue light) generated by the illumination device 703 is directed toward the LCD panel 701 mounted on a glass holder. A light beam of a second wavelength (for example, red visible light) generated by the illumination device 703 is incident on the modulator 705, and the modulator 705 is adapted to receive a bias voltage through an electric photosensor (the modulator). The electric field on the test LCD panel is converted into a spatially modulated optical signal that is reflected by a thin film (not shown) of the modulator 705. The reflected light is focused by the lens system 704 to the CCD device 7U, and the CCD device 711 forms an image of the area of the test LCD panel in the reflected red light, and the formed image can indicate the distribution of the potential on the test panel 701. The example system 700 can further include an image capture/image processing PC 709 for receiving image data from the CCD device 711, generating image of the panel under test using the received image data, and processing the generated image to identify defective LCD cells. This includes the location of these defective cells on the panel being tested. The location information of the defects can be recorded for further processing, for example to correct the detected defects. In one embodiment of the invention, the VIOS 702 is mounted on a movable X/Y/Z platform assembly 706, and the X/Y/Z platform assembly 706 is movable under the control of the platform/10 control module 707. . In another embodiment of the present invention, more than one VIOS 702 is installed on 19 201003063 706, and different VIOS 7〇2 are used to simultaneously verify the final 'set test' of different regions of the same Χ/Υ/Ζ platform test panel. The signal pattern generator 710 provides a driving voltage pattern to the panel of the test panel, thereby controlling the triggering of the device and providing the required bias voltage to the modulator. It should be noted that in the embodiment of the present invention, the front lighting system can be fully integrated into the VIOS subsystem, and the method is not limited by the above detection techniques, and the best absorption efficiency and illumination are provided. It is 9 degrees. The front lighting technology not shown in the figure can also be applied to the detection system according to the electron beam. However, the illumination uniformity is particularly preferred for the dual-wavelength illumination device design described above and illustrated in Figure 5, wherein the blue for the a_Si enable (four) follows the same illumination as the primary f VI〇s illumination. Path arriver. In a particular embodiment of the invention, the front illumination is pulsed and its duration and intensity have been optimized to maximize the detection of defects in the pixel of the TFT pixel. The wavelength matches the maximum absorption optical characteristic of the photosensitive defect. In a particular embodiment, the a-Si residue is front illuminated with a blue light having a wavelength less than that of the pin nano. In the present invention, in order to obtain an optimum positive Φ light efficiency, a wavelength for increasing the conductivity of the non-day/day second residue is selected to match the absorption characteristics of the material. Usually 'a-Si has an absorption edge in the low wavelength (blue) range. See curve 80 in Fig. 8. For larger wavelengths (lower energy), the absorption decreases sharply, while for shorter wavelengths, absorption Sex is almost unchanged. It should be noted that electron beam based defect detection is incompatible with the use of blue light because it causes a significant amount of noise in the secondary electron detector used to measure the pixel power. The reason is 20 201003063 II. First, a short-wavelength photon (such as blue light) has a greater energy than a red-wavelength photon®, so when it hits the flashlight/photomultiplier (SdntiUat〇r-Ph〇tomuItipIier) required for the detection of electrons Will generate unwanted noise signals. The energy of the human electron entering the detector may be affected by the collision of electrons and photons, so there may be a larger signal change, which in turn contributes to the overall noise. The amorphous stone is more sensitive to the light of the New Wave wavelength, and thus the photon which is moved after the irradiation causes the conductivity of the a-Si defect to increase. In some embodiments, the blue light having a wavelength of "o nano C or shorter is selected because this portion has a relatively higher power and can be more efficiently absorbed in a-Si and has A lower sheet resistance. Figure 4 illustrates a plot of film resistance as a function of light intensity at two different wavelengths (47 〇 nanometer (curve 4〇1) and 53 〇 nanometer (curve 402)). As can be seen from the graphs, as the intensity increases, the shorter of the two wavelengths (4〇1) causes the resistance to decrease more rapidly. Since the signal corresponding to light of a shorter wavelength can be stronger, the use of shorter wavelength light can also achieve detection of smaller size defects (Equations 1 and 3).
以a Si對其敏感之光之波長照射該前面板表面之一缺點在於， TFT通道亦暴露於相同之光照射。因TFT結構亦係由a_Si材料構 成，故撞擊正面照明將亦以形成缺陷之殘留物相同之方式增大該 TFT中a_Si材料之電導。當暴露於光時，該TFT之該關斷狀態電 導將增大，因而該TFT之漏電流將高於暗態中之相應值。此導致 晝素電壓之衰減增大，此可利用該TFT對缺陷檢測之電壓響應， 藉由電壓成像測試儀或其它類似測試方法檢測到。因此，即使TFT 通道實際上並無缺陷，端視晝素電壓之衰減而定，測試儀亦可錯 誤地將其視為具有缺陷。亦即，以正面照明光照射無缺陷之TFT 21 201003063 晝素或通道可導致觀察到偽缺陷。 —種使該TFT漏雷滿弓丨* 電弓丨起之晝素電壓衰減最小化、但同時使a_Si 殘留物之檢測響應最大化 之方法，係使該正面照明光脈衝激發並 μ该光脈衝之強度。第9圖係為—實例性圖形使用者介面 抑沖似1 USer "如―）_，顯示照明光定時相對於LCD驅動 圖案信號定時之圖式。信號則（奇數資料線）、9〇2 (偶數資料 線）、则（奇數閘極線）、_ (偶數閘極線）構成—lcd測試 驅動圖案。正面照明脈衝9〇5係由其強度、持續時間、開始時間 及結束時間表徵。 第10圖係為—可能之正面光圖案⑻之另—實例，其中正面 …月脈衝9G5之參數於—既定驅動圓案之每—碼框中皆不相同。 具體而言，於第-（A)碼框中，正面照明脈衝節之持續時間係 為3毫秒，起始時間為3·5毫秒，且強度為·。於第二⑻碼 框中，正面照明脈衝905斷開。於第三（c)碼框中，正面照明脈 衝娜之持續時間係為7毫秒，起始時間為〇毫秒，且強度為乃 %。最後’於第四（D)碼框t ’正面照明脈衝9()5之持續時間係 為3毫秒，起始時間為3.5毫秒，且強度為5〇%。調變器偏壓_ 於每一碼框中皆相同。 使由該a-Si殘留物引起之畫素電壓降低最大化、同時使tft洩 漏引起之«降低最小化，對應於使缺陷檢測靈敏度（如㈣ detection sensitivity; DDS)最大化；同時使該現場標準差（3加 standard deviation )較小或使 6亥訊雜比（signai_t〇_n〇ise 如丨❶；snr ) 較高。具體而言，該DDS之值係為缺陷對比度之量度，並被定義 22 201003063 為該正常畫素之畫素電壓與該缺陷之晝素電壓間之比較，即_ -(1 - Vdefect/vsite-av)，並且通常對於臨限值為3〇% (此係為在 缺陷檢測中通常使用之值）之檢測而言，DDS應大於〇,3。現場標 準差應保持小於〇,4V，而訊雜比SNR = (Vsite_av/標準差）可大於 25。 ' 第11A及11B圖顯示對於一種特定類型之缺陷（一種寄生資料_ 畫素電容型缺陷）。利用本發明系統之—實例性實施例獲得之測 試結果1100及12〇〇。該等圖顯示刪（第nA圖）及職（第 11B圖）與正面光結束時間之相關性。具體而$，針對9對強度 及開始時間值顯示第以圊之資料曲線11QM1G9。具體而言： 強度’ 1毫秒開始時間（曲線11G1);㈣強度，7毫秒開始時間° (曲線1102) ;1〇%強度，9毫秒開始時間（曲線UG3) ;5〇% 強度，1毫㈣始時間（曲線1H)4) ;5G%強度，7毫秒開始時間。 (曲線1105) ;5〇%強度，9毫秒開始時間（曲線ιι〇6) 強度，1毫秒開始時間（曲線蘭）；9〇%強度，7毫秒開始時間° (曲線1108);及90〇/〇強度，9毫秒開始時間（曲線ιι〇9)。第 ⑽圖戶斤示曲、線1201_1209對應於㈣UA _之相應曲線 "01-1109相同之強度/開始時間對。應注意者，脈衝持續時間、 強度及開始時間可因面板而異，並且可因不同之缺陷類型而異。 首先’由所提供曲線_-1109可知，则隨脈衝結束時間及 持續時間而增大（由於該正面光對該a_si殘留物之影響），而咖 隨脈衝結束時間及持續時間而減小（由於該正面光對該TFT之影 響）。其次，在10%與50%之強度之間，DDS之值増大、S脈= 23 201003063 值減小，但在更高之強度下則不變化。此指示存在飽和效應。第 三，在Tend> 14毫秒（在正調變器循環開始處取Τ = 0)時，DDS 及SNR之值看起來飽和。第四，當不存在晝素驅動時，侷限於該 負調變器偏壓循環之脈衝不具有影響。 如第11Α及11Β圖所示，於本發明概念之一特定實施例中，當 強度為50%或更時，且脈衝在調變器偏壓循環之正半循環開始後t =8至11毫秒結束（即脈衝與剛好在資料電壓下降後開始之保持 時間之交疊為1至3毫秒）時，滿足該最佳檢測，即DDS>〇 3且 SNR>25%。應注意者，具有較長持續時間之脈衝會因光致tft洩 漏而引起大到不可接受之SNR降低。為比較起見，在第UB圖中， 亦顯示對應於無正面光時之缺陷檢測之SNR值1 2 1 〇。 最後’應ί里解的是，本文所述方法及技術並非固有地與任何特 定裝置相關’其係可由任何適宜之元件組合實施。此外，根據本 文所述之教示㈣，可使料種類型之通用裝置。構造—專用裝 置以執行本文所述方法步驟亦可證明較佳。上文係參照特定實例 描述本發明，該等實例於每-方面皆旨在作為例示性而非限制性 實例。熟習此項技藝者將瞭解，硬體、軟體及㈣之許多不同組 合亦將適用於實施本發明。 此外，在閲讀本說明蚩及皆 β及實踐本發明之後，對於此 常知識者，本發明之其 ^具有通 種態樣及/或組件在太钚日日+ α 义貝她例之各 组入形式使用^ 檢㈣統中可單獨使用或以任何 太W 將本說明書及該特職為實例㈣明， 本發明之真正範圍及精神 ：紙兒明， 文甲5月專利軏圍及其等效範圍加 24 201003063 以指示。 【圖式簡單說明】 包含於本說明書中並構成其一部份之附圖係用以繪示本發明之 實施例，並且與本說明一同用於解釋和例示本發明之原理。具體 而言： 第1圖於具有週期性電晶體陣列之一較大平整圖案化媒體之一 部份之頂視圖中顯示各種非週期性缺陷； ' ' 第2圖顯示一非晶石夕殘留物之一剖視圖； 第3圖係為非晶矽殘留物相對於TFT晝素之一等效電路圖； 第4圖係為薄膜電阻（sheet resistance )與入射光波長之關係曲 線圖； 第5圖係為根據本發明之一實施例，一雙波長照明裝置（dual wavelength illuminator ; DWI)之一示意圖； 第6圖係為根據本發明之另一實施例之調變器座照明裝置 v ’ （ modulator mount illuminator ; MMI)之一示意圖； 第7圖係為用於檢測平板顯示器内之缺陷之本發明系統之一方 塊示意圖； 第8圖係為表示非晶矽之一典型吸收曲線之一曲線圖； 第9圖係為一可能之正面光及晝素圖案驅動器定時圖之一示意 圖； 第10圖係為一可能之正面光圖案之另一示意圖，其中脈衝於一 25 201003063 既定驅動圖案之每一碼框中皆不相同；以及 第11A及11B圖係為在不同之脈衝起始時間及脈衝強度下，缺 陷檢測靈敏度（defect detection sensitivity ; DDS )及訊雜比 (signal-to-noise ratio ; SNR)與正面光脈衝結束時間之函數曲線 圖。 【主要元件符號說明】 110 ： 金屬突起 112 ： ITO 114 ： ITO突起 116 ： 金屬 118: 缺口 120 ： 開路 122 ： 短路 124 ： 電晶體 126 ： 異物顆粒 128 ： 殘留物 200 ： TFT晝素 202 ： 玻璃板 204 ： 閘極絕緣體 206 ： 資料金屬線 208 ： 鈍化層 210 ： 晝素（ITO) 212 ： 殘留物 214 ： 交疊區域 216 ： 電容器 401 ： 曲線 402 ： 曲線 500 ： 雙波長光學照明系統 501 ： 第二光源 502 ： 藍光照明裝置 503 ： 分色鏡（分光鏡） 504 ： 藍色光束 505 ： 可見光 506 ： 分光鏡 507 ： 透鏡組 508 ： 調變器 509 ： 受試面板 510 ： 低通濾鏡 511 : CCD裝置 512 ·· 雙波長照明裝置 513 ： 電壓源 514 ： 電壓源 26 201003063 515 ： 薄膜 516 ： 調變器之頂面 518 ： 調變器 600 ： 調變器座 601 : 環形照明裝置 602 ： 調變器 603 : 光源 604 ： 正面圖案 700 : 系統 701 ： LCD面板 702 ： VIOS 703 ： 雙波長照明裝置 704 ： 透鏡系統 705 ： 調變器 706 ： X/Y/Z平台 707 ： 平台/10控制模組 709 : 影像擷取/影像處理PC 710 : 測試信號圖案產生器 711 ： CCD裝置 900 ： 圖形使用者介面 901 ： 信號 902 ： 信號 903 ： 信號 904 ： 信號 905 ： 正面照明脈衝 906 ： 調變器偏壓 1000 :正面光圖案 1100 :測試結果 1101 :曲線 1102 :曲線 1103 .曲線 1104 :曲線 1105 :曲線 1106 :曲線 1107 :曲線 1108 :曲線 1109 :曲線 1200 :測試結果 1201 :曲線 1202 :曲線 1203 :曲線 1204 :曲線 1205 :曲線 1206 :曲線 1207 :曲線 1208 :曲線 1209 :曲線 1210 :SNR 值 27One disadvantage of illuminating the front panel surface with the wavelength of light that is sensitive to a Si is that the TFT channel is also exposed to the same light illumination. Since the TFT structure is also composed of a_Si material, the impact front illumination will also increase the conductance of the a_Si material in the TFT in the same manner as the residue forming the defect. When exposed to light, the off-state conductance of the TFT will increase, and thus the leakage current of the TFT will be higher than the corresponding value in the dark state. This results in an increase in the attenuation of the pixel voltage, which can be detected by the voltage sensing of the defect detection by the TFT, by a voltage imaging tester or other similar test method. Therefore, even if the TFT channel is virtually free of defects, depending on the attenuation of the pixel voltage, the tester can mistakenly regard it as having a defect. That is, irradiating the defect-free TFT 21 201003063 with a front illumination light can cause a pseudo defect to be observed. a method for minimizing the decay of the voltage of the TFT by the electric bow, but at the same time maximizing the detection response of the a_Si residue, causing the front illumination light pulse to excite and μ the light pulse Strength. Figure 9 is an example graphical user interface. The suppression is like 1 USer " such as ")_, which shows the timing of the illumination light timing relative to the LCD drive pattern signal timing. The signal (odd data line), 9〇2 (even data line), then (odd gate line), _ (even gate line) constitute the lcd test drive pattern. The front illumination pulse 9〇5 is characterized by its intensity, duration, start time and end time. Figure 10 is an example of a possible frontal light pattern (8) in which the parameters of the front ... month pulse 9G5 are different in each frame of the given drive case. Specifically, in the - (A) code frame, the duration of the front illumination pulse section is 3 milliseconds, the start time is 3.5 minute, and the intensity is ·. In the second (8) code frame, the front illumination pulse 905 is turned off. In the third (c) code frame, the duration of the front illumination pulse is 7 milliseconds, the start time is 〇 milliseconds, and the intensity is %. Finally, the duration of the front illumination pulse 9() 5 in the fourth (D) code frame t' is 3 milliseconds, the start time is 3.5 milliseconds, and the intensity is 5%. The modulator bias _ is the same in each code frame. Maximizing the reduction of the pixel voltage caused by the a-Si residue while minimizing the decrease caused by the tft leakage, corresponding to maximizing the defect detection sensitivity (eg, (D) detection sensitivity; DDS); The difference (3 plus standard deviation) is small or the 6-hoax ratio (signai_t〇_n〇ise as 丨❶; snr) is higher. Specifically, the value of the DDS is a measure of defect contrast and is defined as 22 201003063 as a comparison between the pixel voltage of the normal pixel and the pixel voltage of the defect, ie _ -(1 - Vdefect/vsite- Av), and usually for the detection of a threshold of 3〇% (this is the value commonly used in defect detection), the DDS should be greater than 〇,3. The field standard deviation should be kept less than 〇, 4V, and the signal-to-noise ratio SNR = (Vsite_av/standard deviation) can be greater than 25. 'Figures 11A and 11B show defects for a particular type (a parasitic data_pixel capacitive defect). Test results 1100 and 12 obtained using an exemplary embodiment of the system of the present invention. These figures show the correlation between the deletion (n-A map) and the occupation (Fig. 11B) and the front light end time. Specifically, $, for the 9 pairs of intensity and start time values, shows the data curve 11QM1G9. Specifically: intensity '1 millisecond start time (curve 11G1); (iv) intensity, 7 milliseconds start time ° (curve 1102); 1〇% intensity, 9 milliseconds start time (curve UG3); 5〇% intensity, 1 milli (four) Start time (curve 1H) 4); 5G% intensity, 7 ms start time. (curve 1105); 5〇% intensity, 9 ms start time (curve ιι〇6) intensity, 1 ms start time (curve blue); 9〇% intensity, 7 ms start time ° (curve 1108); and 90〇/ 〇 intensity, 9 ms start time (curve ιι〇9). The figure (10) shows the same intensity/start time pair for the corresponding curve "01-1109 of UA _. It should be noted that the pulse duration, intensity and start time can vary from panel to panel and can vary from defect to defect type. First of all, 'from the curve _-1109 provided, it increases with the pulse end time and duration (due to the influence of the front light on the a_si residue), and the coffee decreases with the pulse end time and duration (due to The effect of the front light on the TFT). Secondly, between 10% and 50% intensity, the value of DDS is large, S pulse = 23 201003063, but it does not change at higher intensity. This indication has a saturation effect. Third, the value of DDS and SNR appears to be saturated at Tend > 14 milliseconds (taken Τ = 0 at the beginning of the positive modulator cycle). Fourth, when there is no halogen drive, the pulse limited to the bias loop of the negative modulator has no effect. As shown in Figures 11 and 11 , in a particular embodiment of the inventive concept, when the intensity is 50% or more, and the pulse is t = 8 to 11 milliseconds after the start of the positive half cycle of the modulator bias cycle The end (i.e., the overlap of the pulse and the hold time immediately after the data voltage drop is 1 to 3 milliseconds) is satisfied, i.e., DDS > 〇 3 and SNR > 25%. It should be noted that pulses with longer durations can cause unacceptable SNR degradation due to photo-induced tft leakage. For the sake of comparison, in the UB diagram, the SNR value 1 2 1 对应 corresponding to the defect detection when there is no front light is also displayed. Finally, it should be understood that the methods and techniques described herein are not inherently related to any particular device and can be implemented by any suitable combination of components. Further, according to the teachings (4) described herein, a general-purpose device of the type of the seed can be obtained. Construction-specific means to perform the method steps described herein may also prove to be preferred. The invention is described above with reference to specific examples, which are intended to be illustrative and not restrictive. Those skilled in the art will appreciate that many different combinations of hardware, software, and (d) will also be suitable for use in practicing the present invention. In addition, after reading this description and both the β and the practice of the present invention, the present invention has a general aspect and/or components in the group of the sun and the day. In the form of use, the test (4) can be used alone or in any case, the specification and the special job are examples (4), the true scope and spirit of the present invention: paper children, the May patent patent and its etc. The range of effects plus 24 201003063 is indicated. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in FIG. In particular: Figure 1 shows various aperiodic defects in a top view of a portion of a larger flat patterned medium having a periodic transistor array; ' ' Figure 2 shows an amorphous stone residue 1 is a cross-sectional view; Figure 3 is an equivalent circuit diagram of amorphous germanium residue relative to TFT halogen; Figure 4 is a plot of sheet resistance versus incident light wavelength; A schematic diagram of a dual wavelength illuminator (DWI) according to an embodiment of the present invention; and FIG. 6 is a modulator mount illuminator according to another embodiment of the present invention. Figure 1 is a schematic diagram of one of the systems of the present invention for detecting defects in a flat panel display; Figure 8 is a graph showing one of typical absorption curves of amorphous germanium; The figure is a schematic diagram of a possible front light and a halogen pattern driver timing diagram; FIG. 10 is another schematic diagram of a possible front light pattern, wherein the pulse is on a 25 201003063 established driving diagram Each code frame is different; and 11A and 11B are the defect detection sensitivity (DDS) and signal-to-noise at different pulse start times and pulse intensities. Ratio ; SNR) is a plot of the end light pulse duration. [Main component symbol description] 110 : Metal protrusion 112 : ITO 114 : ITO protrusion 116 : Metal 118 : Notch 120 : Open circuit 122 : Short circuit 124 : Transistor 126 : Foreign particle 128 : Residue 200 : TFT halogen 202 : Glass plate 204: gate insulator 206: data metal line 208: passivation layer 210: halogen (ITO) 212: residue 214: overlap region 216: capacitor 401: curve 402: curve 500: dual wavelength optical illumination system 501: second Light source 502: Blue light illumination device 503: Dichroic mirror (beam splitter) 504: Blue light beam 505: Visible light 506: Beam splitter 507: Lens group 508: Modulator 509: Test panel 510: Low pass filter 511: CCD Device 512 · Dual Wavelength Illumination Device 513: Voltage Source 514: Voltage Source 26 201003063 515: Film 516: Top Surface of Modulator 518: Modulator 600: Modulator Block 601: Ring Illuminator 602: Modulator 603 : Light source 604 : Front side pattern 700 : System 701 : LCD panel 702 : VIOS 703 : Dual wavelength photo Device 704: Lens System 705: Modulator 706: X/Y/Z Stage 707: Platform/10 Control Module 709: Image Capture/Image Processing PC 710: Test Signal Pattern Generator 711: CCD Device 900: Graphic Usage Interface 901: Signal 902: Signal 903: Signal 904: Signal 905: Front Illumination Pulse 906: Modulator Bias 1000: Front Light Pattern 1100: Test Result 1101: Curve 1102: Curve 1103. Curve 1104: Curve 1105: Curve 1106: Curve 1107: Curve 1108: Curve 1109: Curve 1200: Test Result 1201: Curve 1202: Curve 1203: Curve 1204: Curve 1205: Curve 1206: Curve 1207: Curve 1208: Curve 1209: Curve 1210: SNR Value 27