KR101610821B1 - Enhancement of detection of defects on display panels using front lighting - Google Patents

Abstract

A front-side illumination device and method are provided to generally enable detection of a-Si residue defects in an array test step prior to a cell step. It is difficult to detect defects in a conventional TFT-array test process because a-Si is highly resistant to light when it is not exposed to light. On the other hand, when a-Si is exposed to light, its resistivity decreases, thus changing the electrical characteristics of the TFT array cell, and changes in electrical properties may be detected using a voltage imaging optical system (VIOS) . In one embodiment, the TFT array cell is exposed to the illumination light pulse and impacts the top side of the TFT panel during testing performed using VIOSfmf. In one embodiment, the front side illumination travels along the same path as the illumination used for voltage imaging in the VIOS. In another embodiment, the front side illumination light source (s) is disposed in a space adjacent to the VIOS modulator.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a display panel,

Cross-reference to related application

This application claims priority to 35 U.S.C 119 from U.S. Provisional Patent Application No. 61 / 055,031, filed May 21, 2008, the entire contents of which are incorporated herein by reference.

Field of the Invention

FIELD OF THE INVENTION The present invention relates to the detection of defects in flat panel displays, and more particularly to the detection of defects in flat panel displays using front illumination.

During fabrication of flat panel liquid crystal (LC) displays, a wide clean thin glass substrate is used as a substrate for placement of thin film transistor (TFT) arrays. In general, several independent TFT arrays are included in one glass substrate and are often referred to as TFT panels. Alternatively, an active matrix LCD, or AMLCD, covers the display class using transistors or diodes in each pixel or sub-pixel, such that the glass substrate may be referred to as an AMLCD panel. Flat panel displays may be fabricated using organic LED (OLED) technology, typically fabricated on glass, but may also be fabricated on plastic substrates.

The TFT pattern placement is performed in a plurality of stages, and in each stage a specific material (such as indium tin oxide (ITO), crystalline silicon, amorphous silicon, etc.) is placed on top of the previous layer . Each stage typically includes a number of steps such as placement, masking, etching, stripping, and the like.

During each stage and at various stages within each stage, a number of product defects may occur that may affect the electrical and / or optical performance of the final LCD product. This defect is caused by the metal protrusion 110 to the ITO 112, the protrusion 114 to the metal 116, the so-called ratchet 118, the open circuit 120, the transistor 124, But are not limited to, a shorting 122 in outer layer 126, outer particles 126, and a residue 128 below the pixel. The amorphous silicon (a-Si) residue 128 below the pixel may also result from a bottom etch or lithography issue. Other defects include mask problems, overetching, and the like.

Even when the TFT arrangement process is tightly controlled, defect occurrence can not be avoided. This limits productivity and adversely affects product costs. Typically, the TFT array is fabricated using one or more automated optical inspection (AOI) system (s) following important batch processing steps and Photon Dynamic (San Jose, Calif.) 59708 San Jose, And is inspected using an electro-optic inspection machine, such as may be referred to as a checker (AC) or array tester to test the terminated TFT array.

a-Si is a particularly stiff bond, because a-Si acts as an insulator in the photosensitive, i.e., dark state, but acts as a conductor when exposed to light. In effect, the sheet resistance R _si as a function of the intensity of a-Si is reduced. Figure 4 shows its dependency. The sheet resistance dependence on light intensity ultimately means that as the exposure to light changes, the pixel voltage due to the defect also changes. As a result, if a defect is not detected before the completion of the final FPD assembly, the end user will easily recognize the defect because the defect is exposed to the backlight of the display during normal FPD operation. As a result, there is a strong incentive to detect such defects.

Unfortunately, the prior art has failed to provide a suitable method for effective detection of a-Si residue formation on LCD panels during various stages of panel manufacturing.

The present inventive method is directed to a method and system that substantially obviates one or more of the above problems and other problems associated with detecting a-Si residue formation in an LCD panel display.

According to one aspect of the present inventive method, a system for detecting defects in a panel under test is provided. The system includes a front side illumination subsystem configured to transmit a front side illumination light beam to a panel under test. The front side illumination light beam has a function of changing the electrical specification of the defect to facilitate the detection of the defect. The system further includes a detection subsystem configured to detect defects based on the electrical characteristics of the defective defects. The front side illuminating light beam used in the system is optimized and pulsed for period and intensity to maximize detection of defects and minimize false detection. Further, the front side illumination light beam has a wavelength that matches the maximum absorption optical characteristic of the defect.

According to yet another aspect of the present inventive method, a system for detecting defects in a panel during testing is provided. The system includes a front side illumination subsystem configured to transmit a front side illumination light beam to a panel under test. The front side illumination light beam has a function of changing the electrical specification of the defect to facilitate the detection of the defect. The system further includes a detection subsystem configured to detect defects based on the electrical characteristics of the defective defects. The detection subsystem includes a voltage imaging optical device configured to generate an image representative of a spatial voltage distribution across the panel under test. The defects of the panel under test are detected based on the generated image. System, the front side illumination subsystem is integrated into the optical path of the voltage imaging optical device. Furthermore, the front side illumination light beam has a wavelength that matches the maximum absorption optical characteristic of the defect.

According to yet another aspect of the present inventive method, a system for detecting defects in a panel during testing is provided. The system includes a front side illumination subsystem configured to transmit a front side illumination light beam to a panel under test. The front side illumination light beam has a function of changing the electrical specification of the defect to facilitate the detection of the defect. The system further includes a detection subsystem configured to detect defects based on the electrical characteristics of the defective defects. The detection subsystem includes a voltage imaging optical device configured to generate an image representative of a spatial voltage distribution across the panel under test. The defects of the panel under test are detected based on the generated image. The front side illumination subsystem is disposed outside the optical path of the voltage imaging optical device. Furthermore, the front side illumination light beam has a wavelength that matches the maximum absorption optical characteristic of the defect.

Additional aspects of the invention will be set forth in part in the description that follows, and in part will be obvious from the description, or may be learned by the teachings of the invention. Aspects of the present invention may be recognized and obtained by various elements and components and combinations of aspects specified in the following detailed description and the appended claims.

The foregoing and following description is illustrative and explanatory and is not intended to limit the invention of the claims or their application in any manner.

The present invention enables the detection of a-Si residue defects in the array test step prior to the cell step.

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain and demonstrate the principles of the invention.
1 shows various aperiodic defects in a top view of a portion of a large planar patterned medium with periodic transistor arrays.
Figure 2 shows an exemplary cross-sectional view of an amorphous silicon residue.
Figure 3 shows an exemplary equivalent circuit diagram for an a-Si residue associated with a TFT pixel.
4 is a sample graph of the dependence of sheet resistance on the incident light wavelength.
Figure 5 is an exemplary schematic diagram of a dual wavelength illuminator (DWI) according to an embodiment of the inventive concept.
Figure 6 is an exemplary schematic diagram of a modulator mount illuminator (MMI) according to another embodiment of the inventive concept.
Figure 7 shows an exemplary schematic block diagram of an inventive system for detecting defects in a flat panel display.
Figure 8 is an exemplary graph showing typical absorption curves for amorphous silicon.
9 is an example of timing diagrams of possible front light and pixel pattern driving.
10 is yet another example of a possible frontal light pattern in which the pulses are different for each frame of a given pattern.
11A is a plot of defect detection sensitivity (DDS) and signal-to-noise ratio (SNR) as a function of the front optical pulse end time while varying the pulse start and pulse intensities .

In the following detailed description, reference is made to the accompanying drawings in which like reference numerals designate like structural elements. The foregoing annexed drawings are for the purpose of explanation and not of limitation, and specific embodiments and implementations are in accordance with the principles of the present invention. These implementations will be described in detail so that those skilled in the art will be able to reproduce the invention, and other implementations may be used and structural changes and / or substitutions of various components may be made without departing from the scope and spirit of the invention. Accordingly, the following detailed description should not be construed in a limiting sense. In addition, various implementations of the invention as described may be implemented in the form of specified hardware, or a combination of hardware and software.

As will be appreciated by those skilled in the art, the array tester can be used to test defects in the LC display through the use of the voltage imaging test apparatus and methods disclosed in, for example, U.S. Patent Nos. 4,983,911, 5,097,201, and 5,124,635, . The pixels in the LC display are electrically driven using specific patterns, e.g., as disclosed in U.S. Patent Nos. 5,235,272 and 5,495,410, which are incorporated herein by reference in their entirety. When the LC display is electrically driven, some of the pixels associated with the defects may operate electrically different from the ideal pixels, so that the LC displays are made up of an array of pixels, Or may be detected using image processing software. Through the use of different combinations of drive patterns, the type and location of the plurality of defects shown in Fig. 1 may be deduced.

However, defective pixels with an a-Si residue (128) under ITO are very difficult to detect in array testing using standard array testing methods. A cross-sectional view of an example of a TFT pixel 200 having an a-Si defect is shown in Fig. A TFT pixel structure 200 is formed on a glass substrate 202. The gate insulator 204 is placed on the glass and thereafter the data metal line 206 is plated and a pixel configuration in the form of a transparent conductive material such as indium tin oxide (ITO) 210 is disposed. Finally, a passivation layer, such as silicon nitride (SiNx) 208, is disposed. Amorphous silicon or data metal residue 212 may remain and is plotted by the extension of the line configuration falling below the ITO layer. The overlap region 214 between the residue 212 and the pixel (ITO) 210 forms a capacitor 216 having a parasitic capacitance Cp.

3 is an equivalent view of the a-Si residue below the pixel. in this case,

C _p is the parasitic capacitance, _SiN K is the dielectric constant of the SiN, ε ₀ is the vacuum dielectric constant, the thickness of the W _pixel is a pixel, W _st is the storage capacitor (having a capacitance Cst), d _{pass SiN} and d _{gate SiN} are the distances from the passivation layer and the gate gate to the SiN layer, respectively, and the Area _residue is the area of the residual defect sought.

In an array test, a drive voltage may be applied to the LC substrate so that a pixel response may be observed by the voltage imaging sensor. For defects such as data metal residues and a-Si, a positive-negative (PN) drive pattern in which the data voltage is dropped prior to image acquisition may be used. In this pattern, the drop of the data voltage leads to a voltage drop on the pixel with the ITO data line overlap. When the data voltage drop is ΔV _d, the pixel voltage drop is ΔV _p

C _p is the parasitic capacitance of the ITO-data line residue overlap, C _st is the capacitance of the storage capacitor, and R _si is the sheet resistance of the amorphous silicon.

Equations (1) and (3) show two important points regarding a-Si. First, the parasitic capacitance is a function of the size of the defect (Arearesidue). Second, it is the exponential dependence of sheet resistance R _si . An insulator state (no light) from the, R _si is also significantly higher and (several hundred gigabytes per flat approximately every (square) ohms), so that by equation (3), if not exposed to light, ΔVp is ΔVd * (C _p / C _st ) and has a maximum value. Since Cp < Cst, the maximum DELTA Vp that is not exposed to light may be considerably small, so that the defect may not be easily mixed without using light. Depending on the overlap region, the change may cause some gray level shift under the conventional 64 gray level drive scheme. The voltage step between two consecutive gray levels is approximately 50 mV. This is too small to distinguish a defect from a normal pixel.

However, due to the size dependence (Equation 1), even when exposed to light, a significantly smaller a-Si defect may not be detectable.

While some a-Si defects can be detected using AOI and some can be detected using AC with conventional defect detection techniques, a significant portion of these defects are not identified early and only when the TFT-LCD assembly is complete And is well detected after being divided into LC substrate panels and assembled into modules. In a cell test, a backlight module provides a light source to a TFT-LCD panel to display an image, and is electrically driven. The photosensitive property of a-Si makes it possible to detect this defect under these conditions. However, it is desirable to catch defects prior to the cell assembly step, and it is more desirable to catch them in the array testing step, since the residue can be relatively easily removed using a laser repair system. In addition, detecting defects early in the manufacturing process and prior to cell assembly saves costs associated with the assembly process and the required color filter glass.

LCD array inspection equipment generally does not have an external light source, and as a result, the detection of a-Si may be difficult. The AC47xx family of array testers manufactured by Photon Dynamics, Inc. (obtained by Orbotech) includes a shortwave backlight for use with a transparent chuck on a split axis-type system, , The check area and the resulting chuck are limited to a single modulator row. In a gantry type system where the chuck covers the glass size, an associated backlight is required to move (e.g., single line) or statically (e.g., full coverage) to cover the entire glass site, As a result, it is less practical and less cost effective.

In some cases where the a-Si residue covers the gate metal of the TFT, the backlighting can not penetrate the gate structure and, as a result, the detection of a-Si on the gate residue is difficult. This is more frequent in some pixel designs with extra TFTs, especially when the extra TFTs are electrically isolated and not connected to pixels. When the a-Si residue bridges the pixel TFT and the extra TFT, this affects performance and is recognized as a defect. The a-Si residue increases the C _gd (gate-drain parasitic capacitance). When the gate is turned off (voltage swing: DELTA Vg) due to the gate-drain capacitor connection effect, the pixel voltage drops. This is referred to as a kick-back effect. The pixel voltage drop? Vp is expressed by the following equation (4).

Where C _IC is the cell capacitance (provided only for cell driving). The a-Si residue connecting the pixel TFT to the remaining TFT increases the gate-drain capacitance and also increases the pixel voltage drop.

Other non-voltage imaging array tester units, such as tester machines using an electron beam, may also detect an a-Si residue by spraying electrons to the defect and then accumulating in the defect area. The accumulation of these electrons increases the a-Si conductivity, and associated imaging methods may reveal defects.

In accordance with one embodiment of the present invention, a front side illuminator and method are provided to detect a-Si residue in an array test step, generally before the cell step, and more particularly to detect a-Si residue on the gate insulator of the TFT array cell Enabling detection of water. As will be appreciated by those skilled in the art, a-Si in a TFT-array test has a high resistivity unless exposed to light. On the other hand, if the a-Si residue is illuminated with light, the resistivity is reduced and, in turn, the electrical characteristics of the TFT array cell are changed by Photon Dynamic Inc. (Ovotech, Inc., 59708 San Jose, And may be detected using a voltage imaging optical system (VIOS) such as the manufactured product. Exemplary embodiments of such systems are disclosed in detail in the aforementioned U. S. Patent Nos. 4,983,911, 5,097,201, and 5,124,635, which are incorporated herein by reference in their entirety. Thus, in one embodiment of the present invention, the TFT array cell is exposed to the illumination light pulses and affects the top side of the TFT panel during testing performed using the VIOS.

According to one embodiment, the front side illumination proceeds in the same path as the illumination used for voltage imaging of the VIOS. In one embodiment, the VIOS illumination is performed in the red portion of the visible wavelength region. In one particular embodiment, the exemplary light wavelength is 630 nm. In another embodiment, the front side illumination consists of two or more wavelengths and is delivered in the vicinity of the voltage image modulator of the VIOS.

In an embodiment of the invention, the implementation of the top side or front side illumination into a flat panel array is accomplished in cooperation with the VIOS test device and its function. This results in cost savings and increased efficiency of the entire test system because several components of the VIOS column are used in both the front side illumination as well as the VIOS imaging. In particular, since the ability to detect the defect (a-Si) is a function of light intensity, the front side illumination of the TFT cell must be repeatable and suitably uniform across the detection region. In addition, illumination and optical devices for detecting defects in a-Si can occur in TFT cells, some of which should not interfere with the functionality of the VIOS tester in exploring other types of defects described above.

In an embodiment of the present invention, for the purpose of facilitating the detection of photosensitive fabrication defects such as a-Si residue remaining on structures such as on the gate structure of an LCD pixel or attached to a data line, There is provided a system configured to generate front side illumination of an LCD structure on a panel in a computer system. In an embodiment of this inventive system, the front side of the panel is illuminated with light having a wavelength different from the wavelength of the light used in the voltage imaging VIOS. This is done for at least some reasons. First, the light used in the VIOS illumination may have a wavelength that may not allow sufficient detection of the a-Si residue and / or other photosensitive defects. Second, the modulator of the VIOS is designed such that the light used in the VIOS for voltage imaging is almost completely reflected from the pellicle of the modulator described above and never reaches the panel. Thus, the front-side illumination light is selected to activate the a-Si residue (change electrical characteristics) and be transmitted through the pellicle.

Finally, the overall system includes means for isolating the two light beams and preventing the light used for the front side illumination from interfering with the VIOS imaging (low pass filter 510 shown in Figure 5) The difference between the respective light wavelengths described above is utilized.

A diagram illustrating an exemplary embodiment of a progressive dual wavelength optical illumination system 500 is provided in FIG. This exemplary diagram is provided for illustrative purposes only and is not to be construed as limiting the scope of the invention in any way. 5, a dual wavelength illuminator (DWI) is placed in the optical column of the VIOS illuminator for use in combination with a voltage imaging optical system (VIOS) based array inspection and test system . The construction of VIOS is disclosed as an example in U.S. Patent No. 5,124,635, which is incorporated herein by reference in its entirety.

5, the dual-wavelength illuminator 512 includes a blue light 504 (e.g., a-Si having a wavelength of 455 nm which is particularly sensitive) generated by the blue light illuminator 502, (For example, having a wavelength of 630 nm) generated by the red light illuminator 501 used for defect imaging. In particular, FIG. 8 shows a typical absorption light absorption curve 801 of a-Si showing light having a wavelength 802 at 455 nm with a maximum absorption coefficient for a-Si.

The coupling of the light beams of the two different wavelengths described above is performed by a color sorting (" S ") method that transmits a substantially blue light beam 504 and substantially reflects the red light beam 505 to produce a combined light beam having both wavelengths dichroic mirrors (beam splitter) 503 in the dual wavelength illuminator 512. As will be appreciated by those skilled in the art, coupling light beams of different wavelengths may be accomplished in a number of different ways, some of which are described below with reference to other embodiments of the present invention. Thus, the particular design of the dual wavelength illuminator 512 shown in FIG. 5 should not be construed as limiting in any way.

5, after passing through a color separating mirror (beam spiller) 503, collinear blue and red light beams are reflected by a beam splitter 506 and pass through a lens assembly 507, This is provided to obtain the desired light distribution pattern on the optical modulator 508 and panel 509 under test.

 As described above, in various further or alternative embodiments of the present invention, the dual wavelength, collinear illumination of modulator 508 and panel 509 under test can be obtained in several different ways. For example, in one embodiment, a multi-wavelength light emitting diode (LED) may be employed that may restrict wavelength selection. In this configuration, only one illuminator employing the above-mentioned multi-wavelength light emitting diode needs to be used in place of the light source 502, for example, while the second light source 501 and the color selection mirror 503 are excluded from the illumination system .

In another embodiment, red LEDs of a single wavelength may be partially disposed in a single light source with blue LEDs of a single wavelength, and a single light source may be used instead of the light source 502. Further, in this configuration, the second light source 501 and the color separating mirror 503 need to be excluded from the illumination system. In such a structure using two different wavelength arranged LEDs, the uniformity of the illumination may be compromised.

In one embodiment, the VIOS modulator 508 is provided with a pellicle, and the pellicle is located on the surface of the modulator 508, spatially close to the tested LCD structure of the panel under test. The red light produced by the illuminator 501 is reflected by the pellicle 515 and the blue light generated by the illuminator 502 is transmitted by the pellicle 515 so that the pellicle 515 can transmit the specially selected optical characteristics . The modulator 508 is configured to adjust the intensity of the red light reflected by the pellicle 515 based on the dislocation spread across the top surface (of Figure 5) of the panel 509 under test placed spatially close to the pellicle of the modulator 508 Lt; / RTI > After being reflected by the pellicle, the modulated red light passes through lens assembly 507, beam splitter 506 and low pass filter 510. After passing through the low pass filter 510, the reflected red light impinges on the photosensitive component of the CCD device 511 used to produce an image of the panel under test. A low pass filter 510 is provided in the CCD device 511 to prevent any blue light used to illuminate the a-Si residue from interfering with the CCD image sensor 511 of the VIOS. This filter has optical transmission characteristics designed to pass blue light without passing through weakly to weaken red light. This prevents the front side illumination of the blue light to reach the CCD device 511 and interfere with the generated image of the potential on the top surface of the panel 509 under test. In one embodiment of the present invention, the blue light is only used to alter the electrical properties of the a-Si residue, for example, to be more readily detectable by the VIOS and not to produce an image of the defect itself.

 The tested LCD structure on the surface of the panel 509 under test is biased using a voltage source 513 and the top surface 516 of the modulator 508 (on FIG. 5) is biased using a voltage source 514. In one embodiment of the present invention, all of the optical components of the system are provided with optical coatings that are optimal for optimal light transmission and reflection. The uniformity of illumination by light of both wavelengths (blue and red) will be similar and is typically not worse than about 25% in one embodiment of the present invention. Typical illumination uniformity is in the range of 10% to 15%. As a result, the progressive dual wavelength illumination concepts and arrangements shown in FIG. 5 allow a-Si defects to be illuminated at the most sensitive wavelength of a-Si without degrading or interfering with the functionality of the voltage imaging test (VIOS) hardware.

The invention is not limited to illumination of panels and modulators during testing by only red and blue light. As will be appreciated by those skilled in the art, to reduce the interference of the front side illumination and the operation of the VIOS used to fully vary the electrical characteristics of a-Si to enable detection and to regenerate the voltage distribution pattern across the panel under test , Another illumination light wavelength may be selected to achieve proper absorption by the a-Si residue.

6, for use in combination with a VIOS-based array inspection and testing system, a ring illuminator 601 is provided in the modulator mount 600 (see FIG. 6) . The ring illuminator 601 is placed on the modulator 508 and a single wavelength (blue or approximately 455 nm wavelength) light source 603, such as an LED, is placed outside the optical path of the VIOS to prevent image clipping. As in the first embodiment described above, the pellicle of the modulator 508 transmits blue light and reflects light of the visible wavelength generated by the red illuminator 501, which is necessary for the function of the voltage imaging modulator 508 . The light source 603 generates an illumination pattern 604. In an exemplary embodiment of the present invention, each side of the mounting ring 601 includes four LEDs 603. However, those skilled in the art will appreciate that other suitable numbers of LEDs may be disposed in mounting ring 601 in any suitable manner to obtain the desired uniformity and intensity of illumination. Thus, the present invention is not limited to the fixture ring 601, the modulator mount 600, and the light source 603. In various embodiments of the present invention, the fixture ring 601 has a square, rectangular, octagonal, circular, oval or other suitable shape. To affect the electrical characteristics of the a-Si residue on the panel under test, the light generated by the light source 603 passes through the modulator 602 to illuminate the front of the panel under test.

As will be appreciated by those skilled in the art, depending on the size of the area of the modulator 508, in some cases, especially when the number of LEDs 603 is relatively small, the dual wavelength illuminator DWI described with reference to FIG. It may be more difficult to obtain good uniformity in this embodiment. However, increasing the number of LEDs 603 to at least 10 (more than 40 in total) per side facilitates greater uniformity of illumination and can be achieved by the dual wavelength illuminator (DWI) described with reference to FIG. Uniformity characteristics comparable to uniformity may be obtained. For best uniformity over the full scale of the modulator area, the emission angle of the LEDs must be controlled. As is known in the art, some LEDs have a Lambertian emission profile, resulting in a desired object of emitting at a large solid angle to achieve a high level of illumination uniformity, Because it is transmitted non-uniformly to the center of. There are several alternative solutions that may be employed to overcome this drawback. In one embodiment, LEDs in a particular direction are used as the light source 603 and intended to illuminate the very center of the modulator 508.

In yet another embodiment, a collimating lens is added or preferably optically coupled to each common LED, including the spread of the Lambertian profile. Various methods of optically connecting collimating lenses to LEDs are known in the art. In one embodiment, each LED is equipped with its own collimating lens. Such a collimating lens facilitates improved uniformity of the front side illumination. In yet another embodiment, directional attenuation is applied by adding a neutral density filter on the side of the LED. Also, a diffuser can be used to (1) eliminate the spatial disparity of each LED and (2) improve the overall illumination uniformity of the combined LED distribution. For example, in one embodiment, a diffuser manufactured and sold by Lucent, Inc. (Physics Optics Corporation), Toronto, CA, may be used.

In one embodiment, a beamforming diffuser that produces elliptical bonsai may be used to improve front side illumination uniformity. In the same or different embodiments, the front side illumination uniformity may also be improved by using a bending or directional turning film.

The light source 603 providing the front side illumination of the a-Si residue on the surface of the panel 509 under test is illuminated by the illumination of the illuminator 508 over the dual wavelength illuminator system of FIG. 5 in which the second light source is integrated into the VIOS column itself. The main advantage of the multiple light source configuration shown in Fig. 6, which is mounted on a separate mounting ring disposed near it, is that it is easy to form on existing gantry type systems and is cheaper to retrofit. In addition, the inventive concept illustrated in FIG. 6 can be applied to defect detection techniques (such as electron beam-based detectors and full contact probe testers) that require uniform ambient illumination. However, as described above, the electron beam detector is incompatible with blue light illumination.

As will be appreciated by those skilled in the art, the system configuration for providing front side illumination, including placing a light source in the vicinity of the modulator, may be obtained in a number of ways in addition to the embodiment shown in FIG. Thus, the particular design of the fixture system shown in FIG. 6 should not be construed as limiting in any way.

FIG. 7 illustrates an exemplary schematic block diagram of a system 700 for detecting defects in a flat panel display employing one of the inventive conceptual embodiments. The progressive system includes a VIOS 702 that includes a dual wavelength illuminator 703, an exemplary embodiment of which has been described above with reference to FIG. 5 (component 512). The light beam of the first wavelength generated by the illuminator 703, for example, blue light, travels on the LCD panel 701 provided on the glass support. The light beam of the second wavelength generated by the illuminator 703, for example, red visible light, is used to interpret the electric field on the biased LCD panel during the test as an optical signal spatially modulated through an electro-optic transducer (Not shown) of the modulator 705, as shown in FIG. The reflected light is focused by the lense system 704 onto the CCD device 711 which produces an image of the LCD panel area under test in the reflected light, Distribution. Exemplary system 700 receives image data from CCD device 711, uses the received image data to generate an image of the panel under test, and processes the generated image to generate defective LCD cells And an image acquisition / image processing PC 709 configured to identify the location of such defects. The location information of the defect can be stored for further processing such as correction of the detected defect.

In one embodiment of the present invention, the VIOS 702 is mounted on a movable X / Y / Z stage assembly 706 that is movable under the control of the stage / IO control module 707. In one embodiment of the invention, one or more VIOS 702 is mounted on the X / Y / Z stage assembly 706 such that different areas of the panel under test are simultaneously inspected using different VIOS 702. [

Finally, a test signal pattern generator 710 is arranged to provide a drive voltage pattern to the LCD panel under test, control the illuminator trigger, and provide the bias voltage needed for the modulator.

In one embodiment of the present invention, the front light illumination system can be fully integrated into the VIOS subsystem, providing optimal absorption efficiency and illumination uniformity, and is not limited in any way by the fencing technique described above. The front light illumination technique described in Figure 6 may be employed for use in an electron beam based detection system. However, the illumination uniformity is described and shown above in Fig. 5 and is particularly good in a dual wavelength illuminator design where the blue light used for a-Si activation flows to the modulator with the same optical path as the main VIOS illuminator light.

In certain embodiments of the present invention, the front side illumination is pulsed and optimized for period and intensity to maximize the detection of photosensitive defects relative to TFT pixels. In particular, the front side illumination light has a wavelength that matches the maximum absorption optical characteristic of the photosensitive defect. In certain embodiments, blue light having a wavelength of less than 470 nm is used for front side illumination of the a-Si residue.

In one embodiment of the present invention, for optical frontal light efficiency, the wavelength used to increase the conductivity of the amorphous silicon residue is selected to match the absorption characteristics of the material. Typically, a-Si has an absorption edge in the low wavelength (blue light) range, as shown in curve 801 in Fig. For large wavelengths (low energy), the absorption decreases sharply, whereas for shorter wavelengths, the absorption does not change somewhat. Electron beam based defect detection is not compatible with the use of blue light because electron beam based defect detection induces a significant amount of noise in the secondary electron detector that the electron beam based defect detection uses to measure the pixel voltage. There are two reasons for this. First, when a photon with a short wavelength such as blue light has more energy than a photon with a red wavelength, and consequently a photon having a short wavelength hits a scintillator-photomultiplier tube necessary for detecting electrons, an undesired noise signal . Second, the energy of the secondary electrons directed to the detector can be influenced by the impulses of electrons and photons, and there may be a higher change in the signal, and the change contributes to the total noise.

Amorphous silicon is photosensitive to short-wavelength light, and as a result, moving photons are generated after irradiation, resulting in an increase in the conductivity of the a-Si defect. In some embodiments, the blue light having a wavelength of 470 nm (or shorter) is selected because blue light is relatively high in power, is absorbed more efficiently in a-Si, and has a lower sheet resistance I have. Figure 4 shows a plot of two sheet resistances as a function of light intensity for two different wavelengths, 470 nm (plot 401) and 530 nm (plot 402). As can be seen from the plot, the shorter wavelength 401 of the two wavelengths decreases the resistance more rapidly as the intensity increases. Since the signal corresponding to light having a shorter wavelength may be stronger, the use of shorter wavelength light may enable the detection of smaller size defects (equations 1, 3).

One drawback of a-Si illuminating the front panel surface with light having a sensitive wavelength is that the TFT channels are also exposed to the same light illumination. Because the TFT structure is also made of an a-Si material, affecting the front side illumination also increases the conductivity of the a-Si material of the TFT in the same way as the residue forming the defect. When exposed to light, the off-state conductivity of the TFT will increase, and thus the leakage current of the TFT will be higher than the corresponding value in the dark state. This causes an increase in the pixel voltage attenuation, which can be detected by a voltage image tester or other similar test method using the voltage response of the TFT for defect detection. As a result, even if the TFT is substantially free of defects, the tester may rely on the pixel voltage attenuation to incorrectly interpret it as having a defect. That is, illuminating a good TFT pixel or channel with the front side illumination light may cause a false defect to be observed.

One way to minimize pixel voltage attenuation due to TFT leakage current, while at the same time maximizing the detection response of a-Si residue is to pulse the front illumination light and change the period and intensity of the light pulse. FIG. 9 is an exemplary graphical user interface 900 illustrating a diagram of the front light timing with respect to the timing of the LCD driving pattern signal. The signals 901 (even data), 902 (odd data), 903 (even gate), and 904 (odd gate) constitute the LCD test drive pattern. The front side illumination pulse 905 is characterized by its intensity, duration, start time and end time.

10 is another example of a possible front light pattern 1000 in which the parameters of the front side illumination pulse 905 are different for every frame of a given driving pattern. Specifically, in the first (A) frame, the front side illumination pulse 905 has a period of 3 ms, a start time of 3.5 ms, and an intensity of 50%. In the second (B) frame, the front side illumination pulse 905 is turned off. In the third (C) frame, the front side illumination pulse 905 has a period of 7 ms, a start time of 0 ms, and an intensity of 25%. Finally, in the fourth (D) frame, the front side illumination pulse 905 has a period of 3 ms, a start time of 3.5 ms, and an intensity of 50%. The modulator bias voltage 906 is the same for each frame.

Maximizing the pixel-voltage reduction due to a-Si residue while minimizing the voltage drop due to TFT leakage can reduce defect detection sensitivity (DDS) while reducing the site standard deviation or increasing the signal-to-noise ratio (SNR) It corresponds to maximizing. In particular, DDS is a measure of the defect difference and is defined as the comparison between the pixel voltage for a normal pixel and the pixel voltage for a defective pixel, i.e. DDS = (1-V _defect / V _site-av) Must be greater than 0.3 for detection with a 30% threshold typically used for defect detection. The site standard deviation is kept below 0.4 V, and the signal-to-noise ratio, SNR = (V _{site - av /} Std.Dev) may be greater than 25.

FIGS. 11A and 11B show test results 1100 and 1200 obtained using one exemplary embodiment of a system for a particular type of defect (parasitic data = pixel capacitance type defect). These figures show the dependence of the DDS (FIG. 1A) and the SNR (FIG. 11B) on the front optical end time. Specifically, the data plots 1101-1109 of FIG. 11A are shown for nine pairs of intensity and start time values. Specifically, an intensity of 10%, a start time of 1 ms (plot 1101); 10% intensity, start time of 7 ms (plot 1102); 10% intensity, start time of 9 ms (plot 1103); 50% intensity, start time of 1 ms (plot 1104); Intensity of 50%, start time of 7 ms (plot 1105); Intensity of 50%, start time of 9 ms (plot 1106); Intensity of 90%, start time of 1 ms (plot 1107); Intensity of 90%, start time of 7 ms (plot 1108); And a 90% intensity, start time of 9 ms (plot 1109). The plots 1201 - 1209 shown in FIG. 11B correspond to the same intensity / start time pairs as the respective plots 1101 - 1109 of FIG. 11A. The pulse duration, intensity, and start time may vary from panel to panel, and may be different for different types of defects.

First, along with the pulse end time and duration from the provided plots 1101-1109, the DDS increases (due to the influence of the front light on the a-Si residue) and the SNR decreases (due to the influence of the front light on the TFT) . Second, between 10% and 50%, the value of DDS increases and the SNR decreases and does not change for higher intensities. This represents a saturation effect. Third, the values of DDS and SNR can saturate for T _end > 14 ms (T = 0 is given at the beginning of the positive modulator period). Fourth, pulses defined in the negative modulator bias cycle are not affected when pixel driving does not occur.

As shown in Figures 11a and 11b, in certain embodiments of the present inventive concept, the best detection, i.e., DDS > 0.3 and SNR > 25% is greater than 50% after the time of the positive half of the modulator bias cycle and t = 8 To 11, i. E., With an overlap of 1 to 3 ms of holding time just prior to the drop of the data voltage. The longer duration of the pulses causes an unacceptable drop in SNR due to the light reduced TFT leakage. For comparison, in FIG. 11B, the SNR value 1210 corresponding to the detection of a front lightless defect has already been shown.

Finally, the processes and techniques described herein are not directed to any particular device and may be implemented by any suitable combination of components. Various types of general purpose devices may also be used in accordance with the techniques described herein. It may also improve the advantages of building specialized devices that perform the method steps described herein. The present invention has been described with reference to specific examples, which are all related to the description and not of limitation. Those skilled in the art will appreciate that many different combinations of hardware, software, and firmware will be suitable for practicing the invention.

In addition, other implementations of the invention will be apparent to those skilled in the art from the detailed description and understanding of the invention set forth herein. The various aspects and / or components of the described embodiments may be used alone or in any combination in this inventive defect detection system. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the invention being indicated by the following claims and their equivalents.

204: gate insulator 206: data line
208: passivation 212: amorphous silicon residue
214: Data line overlap 216: Data-pixel overlap capacitance
501: Red illuminator 506: Beam splitter
507: lens assembly 509: modulator
510: Low-pass filter 511: CCD device
512: Color selection mirror 701: LCD panel
702: VIOS 704: lens
705: Modulator 706: Stage assembly (X / Y / Z)
707: Stage / IO 708: Control computer
709: Image acquisition / processing PC 710: Pattern generator
711: CCD camera

Claims (30)

A front side illumination subsystem configured to transmit a front side illumination light beam that changes the electrical characteristics of the defect on the panel under test to facilitate detection of defects; And
And a detection subsystem configured to detect the defect based on the altered electrical characteristics of the defect,
In order to maximize the detection of the defect and minimize the detection of false defects, at least one of the wavelength, the pulse duration and the intensity of the front side illumination light beam is determined according to the characteristic of the defect,
Wherein the front side illumination light beam has a wavelength that matches the maximum absorption optical characteristic of the defect. The method according to claim 1,
Further comprising a voltage source configured to apply a voltage signal to the panel under test, the applied voltage signal causing a spatial voltage distribution across the panel under test,
Wherein the detection subsystem includes a voltage imaging optical device configured to generate an image representative of a spatial voltage distribution across the panel under test, wherein the defect is detected based on the generated image, . 3. The method of claim 2,
Wherein the front side illumination subsystem is integrated in the optical path of the voltage imaging optical device. The method of claim 3,
Wherein the optical path of the voltage imaging optical device comprises a dichroic mirror configured to combine the voltage imaging light beam and the front side illumination light beam. The method of claim 3,
The voltage imaging optical device comprising:
An imaging device configured to generate an image representative of a spatial voltage distribution across the panel under test; And
A low pass filter configured to prevent the front side illumination light beam from reaching the imaging device. The method of claim 3,
The voltage imaging optical device comprising:
And a modulator configured to modulate the voltage imaging light beam according to a spatial voltage distribution across the panel under test, the modulator having a pellicle configured to reflect the voltage imaging light beam and deliver the front side illumination light beam, Fault detection system for panel under test. The method according to claim 1,
Wherein the front side illumination light beam is in the blue wavelength range and the voltage imaging light beam producing an image by the voltage imaging device has a different wavelength than the front side illumination light beam. A front side illumination subsystem configured to transmit a front side illumination light beam that changes the electrical characteristics of the defect on the panel under test to facilitate detection of defects; And
And a detection subsystem configured to detect the defect based on the altered electrical characteristics of the defect,
Wherein the detection subsystem comprises a voltage imaging optical device configured to generate an image representative of a spatial voltage distribution across the panel under test,
The defects are detected based on the generated image, the front side illumination light beam has a wavelength that matches the maximum absorption optical characteristic of the defect, and the front side illumination subsystem detects an optical path of the voltage imaging optical device A defect detection system for a panel under test, 9. The method of claim 8,
Wherein the optical path of the voltage imaging optical device comprises a dichroic mirror configured to couple the voltage imaging light beam and the front side illumination light beam. 9. The method of claim 8,
The voltage imaging optical device comprising:
An imaging device configured to generate an image representative of a spatial voltage distribution across the panel under test; And
A low pass filter configured to prevent the front side illumination light beam from reaching the imaging device. 9. The method of claim 8,
The voltage imaging optical device comprising:
And a modulator configured to modulate a voltage imaging light beam according to a spatial voltage distribution across the panel under test, the modulator having a pellicle configured to reflect the voltage imaging light beam and to transmit the front side illumination light beam Fault detection system in the panel. 9. The method of claim 8,
Wherein the front side illumination light beam is in the blue wavelength range and the voltage imaging light beam producing an image by the voltage imaging device has a different wavelength than the front side illumination light beam. A front side illumination subsystem configured to transmit a front side illumination light beam that changes the electrical characteristics of the defect on the panel under test to facilitate detection of defects; And
And a detection subsystem configured to detect the defect based on the altered electrical characteristics of the defect,
Wherein the detection subsystem comprises a voltage imaging optical device configured to generate an image representative of a spatial voltage distribution across the panel under test,
The defects are detected based on the generated image, the front side illumination light beam has a wavelength that matches the maximum absorption optical characteristic of the defect, and the front side illumination subsystem detects the optical path of the voltage imaging optical device A defect detection system for a panel under test, disposed externally. 14. The method of claim 13,
Wherein the front side illumination subsystem includes a plurality of specific direction light emitting diodes disposed on a mounting ring to optimize uniformity of the front side illumination light beam. 14. The method of claim 13,
Wherein the front side illumination subsystem includes a plurality of light emitting diodes, at least one of the plurality of light emitting diodes being optically coupled to a collimation lens and disposed in a mounting ring to optimize uniformity of the front side illumination light beam Fault detection system in the panel. 14. The method of claim 13,
The front side illumination sub-
And a plurality of light emitting diodes optically coupled to the directional attenuation module to optimize the uniformity of the front side illumination light beam. 17. The method of claim 16,
Wherein the directional attenuation module comprises a neutral density filter. 14. The method of claim 13,
The voltage imaging optical device comprising:
An imaging device configured to generate an image representative of a spatial voltage distribution across the panel under test; And
A low pass filter configured to prevent the front side illumination light beam from reaching the imaging device. 14. The method of claim 13,
The voltage imaging optical device comprising:
And a modulator configured to modulate a voltage imaging light beam according to a spatial voltage distribution across the panel under test, the modulator having a pellicle configured to reflect the voltage imaging light beam and deliver the front side illumination light beam, The front side illumination subsystem is disposed spatially close to the modulator. 14. The method of claim 13,
Wherein the voltage imaging optical device and the front side illumination subsystem are mounted on a movable stage assembly configured to scan across a panel under test under the control of a stage control module. 21. The method of claim 20,
Further comprising at least a second front side illumination subsystem and at least a second voltage imaging optical device mounted on the movable stage assembly. 14. The method of claim 13,
Wherein the front side illumination light beam is in the blue wavelength range and the voltage imaging light beam producing an image by the voltage imaging device has a different wavelength than the front side illumination light beam. 14. The method of claim 13,
Wherein the front side illumination subsystem includes a plurality of light emitting diodes, each of the plurality of light emitting diodes being provided with a diffuser optically connected to each of the plurality of light emitting diodes, And configured to remove spatial imbalance and improve overall illumination uniformity of the front side illumination light beam. Transmitting a front side illumination light beam that changes the electrical characteristics of the defect to facilitate testing of the defect on a panel under test using a front side illumination subsystem; And
And detecting the defect based on the altered electrical characteristics of the defect using a detection subsystem,
In order to maximize the detection of the defect and minimize the detection of false defects, at least one of the wavelength, the pulse duration and the intensity of the front side illumination light beam is determined according to the characteristic of the defect,
Wherein the front side illumination light beam has a wavelength that matches the maximum absorption optical characteristic of the defect. 25. The method of claim 24,
Further comprising the step of applying a voltage signal to the panel under test,
Wherein the applied voltage causes a signal to cause a spatial voltage distribution across the panel under test and to generate an image representative of the spatial voltage distribution across the panel under test and wherein the defect is detected based on the generated image, A method of detecting defects in a panel under test. 26. The method of claim 25,
Wherein an image representative of the spatial voltage distribution across the panel under test is generated using a voltage imaging light beam and the front side illumination light beam is located in an optical path of the voltage imaging light beam, . 26. The method of claim 25,
An image representative of the spatial voltage distribution across the panel under test,
A low-pass filter configured to prevent an image device and the front-side illuminating light beam from reaching the image device. 26. The method of claim 25,
Wherein the front side illumination light beam is in the blue wavelength range and a voltage imaging light beam producing an image representative of a spatial voltage distribution across the panel under test has a wavelength different from the front side illumination light beam, Detection method. Transmitting a front side illumination light beam that changes the electrical characteristics of the defect to facilitate testing of the defect on a panel under test using a front side illumination subsystem; And
And detecting the defect based on the altered electrical characteristics of the defect using a detection subsystem,
Wherein the detection subsystem comprises a voltage imaging optical device configured to generate an image representative of a spatial voltage distribution across the panel under test,
Wherein the defect is detected based on the generated image, wherein the front side illumination light beam has a wavelength that matches the maximum absorption optical characteristic of the defect, and wherein the front side illumination subsystem comprises an optical path Wherein the defect is detected in the panel under test. Transmitting a front side illumination light beam that changes the electrical characteristics of the defect to facilitate testing of the defect on a panel under test using a front side illumination subsystem; And
And detecting the defect based on the altered electrical characteristics of the defect using a detection subsystem,
Wherein the detection subsystem comprises a voltage imaging optical device configured to generate an image representative of a spatial voltage distribution across the panel under test,
Wherein the defect is detected based on the generated image, wherein the front side illumination light beam has a wavelength that matches the maximum absorption optical characteristic of the defect, and wherein the front side illumination subsystem comprises an optical path A method of detecting defects in a panel under test, disposed outside.

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