TW200945048A - Multi-core processing system - Google Patents

Multi-core processing system Download PDF

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Publication number
TW200945048A
TW200945048A TW098106572A TW98106572A TW200945048A TW 200945048 A TW200945048 A TW 200945048A TW 098106572 A TW098106572 A TW 098106572A TW 98106572 A TW98106572 A TW 98106572A TW 200945048 A TW200945048 A TW 200945048A
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TW
Taiwan
Prior art keywords
core
group
coherency
processor
packet
Prior art date
Application number
TW098106572A
Other languages
English (en)
Chinese (zh)
Inventor
Perry H Pelley Iii
George P Hoekstra
Lucio F C Pessoa
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200945048A publication Critical patent/TW200945048A/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW098106572A 2008-04-15 2009-02-27 Multi-core processing system TW200945048A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/103,250 US7941637B2 (en) 2008-04-15 2008-04-15 Groups of serially coupled processor cores propagating memory write packet while maintaining coherency within each group towards a switch coupled to memory partitions

Publications (1)

Publication Number Publication Date
TW200945048A true TW200945048A (en) 2009-11-01

Family

ID=41164943

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098106572A TW200945048A (en) 2008-04-15 2009-02-27 Multi-core processing system

Country Status (6)

Country Link
US (2) US7941637B2 (https=)
JP (1) JP5419107B2 (https=)
KR (1) KR20110000741A (https=)
CN (1) CN101999115B (https=)
TW (1) TW200945048A (https=)
WO (1) WO2009128981A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI474175B (zh) * 2010-12-22 2015-02-21 Via Tech Inc 核心處理器之內部旁路匯流排

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US8547971B1 (en) 2009-01-07 2013-10-01 Marvell Israel (M.I.S.L) Ltd. Multi-stage switching system
US8358651B1 (en) 2009-09-21 2013-01-22 Marvell International Ltd. Switch device having a plurality of processing cores
US9172659B1 (en) 2011-07-12 2015-10-27 Marvell Israel (M.I.S.L.) Ltd. Network traffic routing in a modular switching device
US9372724B2 (en) * 2014-04-01 2016-06-21 Freescale Semiconductor, Inc. System and method for conditional task switching during ordering scope transitions
US9372723B2 (en) * 2014-04-01 2016-06-21 Freescale Semiconductor, Inc. System and method for conditional task switching during ordering scope transitions
US9733981B2 (en) 2014-06-10 2017-08-15 Nxp Usa, Inc. System and method for conditional task switching during ordering scope transitions
US9448741B2 (en) 2014-09-24 2016-09-20 Freescale Semiconductor, Inc. Piggy-back snoops for non-coherent memory transactions within distributed processing systems
US11449452B2 (en) * 2015-05-21 2022-09-20 Goldman Sachs & Co. LLC General-purpose parallel computing architecture
ES2929626T3 (es) * 2015-05-21 2022-11-30 Goldman Sachs & Co Llc Arquitectura de computación paralela de propósito general
US10904150B1 (en) 2016-02-02 2021-01-26 Marvell Israel (M.I.S.L) Ltd. Distributed dynamic load balancing in network systems
US10866753B2 (en) * 2018-04-03 2020-12-15 Xilinx, Inc. Data processing engine arrangement in a device
CN112948282A (zh) * 2019-12-31 2021-06-11 北京忆芯科技有限公司 用于数据快速查找的计算加速系统
CN115668125A (zh) * 2020-08-31 2023-01-31 麦姆瑞克斯公司 存储器处理单元架构映射技术
US12086066B1 (en) * 2023-03-15 2024-09-10 Cornami, Inc. Cache architecture for a massively parallel processing array

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US4710868A (en) * 1984-06-29 1987-12-01 International Business Machines Corporation Interconnect scheme for shared memory local networks
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US6754752B2 (en) 2000-01-13 2004-06-22 Freescale Semiconductor, Inc. Multiple memory coherence groups in a single system and method therefor
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US6862283B2 (en) 2000-01-13 2005-03-01 Freescale Semiconductor, Inc. Method and apparatus for maintaining packet ordering with error recovery among multiple outstanding packets between two devices
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI474175B (zh) * 2010-12-22 2015-02-21 Via Tech Inc 核心處理器之內部旁路匯流排
TWI514155B (zh) * 2010-12-22 2015-12-21 Via Tech Inc 微處理器以及多核心晶片之核心間通訊方法

Also Published As

Publication number Publication date
JP5419107B2 (ja) 2014-02-19
CN101999115B (zh) 2014-04-02
KR20110000741A (ko) 2011-01-05
US20110093660A1 (en) 2011-04-21
WO2009128981A1 (en) 2009-10-22
US7941637B2 (en) 2011-05-10
US20090259825A1 (en) 2009-10-15
US8090913B2 (en) 2012-01-03
JP2011517003A (ja) 2011-05-26
CN101999115A (zh) 2011-03-30

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