KR20110000741A - 멀티코어 처리 시스템 - Google Patents

멀티코어 처리 시스템 Download PDF

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Publication number
KR20110000741A
KR20110000741A KR1020107023111A KR20107023111A KR20110000741A KR 20110000741 A KR20110000741 A KR 20110000741A KR 1020107023111 A KR1020107023111 A KR 1020107023111A KR 20107023111 A KR20107023111 A KR 20107023111A KR 20110000741 A KR20110000741 A KR 20110000741A
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South Korea
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consistency group
core
processor
information
consistency
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KR1020107023111A
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English (en)
Korean (ko)
Inventor
3세 페리 에이치. 펠리
조지 피. 호크스트라
루시오 에프.씨. 페소아
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프리스케일 세미컨덕터, 인크.
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Publication of KR20110000741A publication Critical patent/KR20110000741A/ko
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020107023111A 2008-04-15 2009-02-16 멀티코어 처리 시스템 Ceased KR20110000741A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/103,250 US7941637B2 (en) 2008-04-15 2008-04-15 Groups of serially coupled processor cores propagating memory write packet while maintaining coherency within each group towards a switch coupled to memory partitions
US12/103,250 2008-04-15

Publications (1)

Publication Number Publication Date
KR20110000741A true KR20110000741A (ko) 2011-01-05

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ID=41164943

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KR1020107023111A Ceased KR20110000741A (ko) 2008-04-15 2009-02-16 멀티코어 처리 시스템

Country Status (6)

Country Link
US (2) US7941637B2 (https=)
JP (1) JP5419107B2 (https=)
KR (1) KR20110000741A (https=)
CN (1) CN101999115B (https=)
TW (1) TW200945048A (https=)
WO (1) WO2009128981A1 (https=)

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US8547971B1 (en) 2009-01-07 2013-10-01 Marvell Israel (M.I.S.L) Ltd. Multi-stage switching system
US8358651B1 (en) 2009-09-21 2013-01-22 Marvell International Ltd. Switch device having a plurality of processing cores
US9460038B2 (en) * 2010-12-22 2016-10-04 Via Technologies, Inc. Multi-core microprocessor internal bypass bus
US9172659B1 (en) 2011-07-12 2015-10-27 Marvell Israel (M.I.S.L.) Ltd. Network traffic routing in a modular switching device
US9372724B2 (en) * 2014-04-01 2016-06-21 Freescale Semiconductor, Inc. System and method for conditional task switching during ordering scope transitions
US9372723B2 (en) * 2014-04-01 2016-06-21 Freescale Semiconductor, Inc. System and method for conditional task switching during ordering scope transitions
US9733981B2 (en) 2014-06-10 2017-08-15 Nxp Usa, Inc. System and method for conditional task switching during ordering scope transitions
US9448741B2 (en) 2014-09-24 2016-09-20 Freescale Semiconductor, Inc. Piggy-back snoops for non-coherent memory transactions within distributed processing systems
US11449452B2 (en) * 2015-05-21 2022-09-20 Goldman Sachs & Co. LLC General-purpose parallel computing architecture
ES2929626T3 (es) * 2015-05-21 2022-11-30 Goldman Sachs & Co Llc Arquitectura de computación paralela de propósito general
US10904150B1 (en) 2016-02-02 2021-01-26 Marvell Israel (M.I.S.L) Ltd. Distributed dynamic load balancing in network systems
US10866753B2 (en) * 2018-04-03 2020-12-15 Xilinx, Inc. Data processing engine arrangement in a device
CN112948282A (zh) * 2019-12-31 2021-06-11 北京忆芯科技有限公司 用于数据快速查找的计算加速系统
CN115668125A (zh) * 2020-08-31 2023-01-31 麦姆瑞克斯公司 存储器处理单元架构映射技术
US12086066B1 (en) * 2023-03-15 2024-09-10 Cornami, Inc. Cache architecture for a massively parallel processing array

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JPH07104923B2 (ja) * 1988-12-28 1995-11-13 工業技術院長 並列画像表示処理方法
US7106742B1 (en) 2000-01-13 2006-09-12 Mercury Computer Systems, Inc. Method and system for link fabric error detection and message flow control
US6754752B2 (en) 2000-01-13 2004-06-22 Freescale Semiconductor, Inc. Multiple memory coherence groups in a single system and method therefor
US7031258B1 (en) 2000-01-13 2006-04-18 Mercury Computer Systems, Inc. Digital data system with link level message flow control
US6862283B2 (en) 2000-01-13 2005-03-01 Freescale Semiconductor, Inc. Method and apparatus for maintaining packet ordering with error recovery among multiple outstanding packets between two devices
US6678773B2 (en) 2000-01-13 2004-01-13 Motorola, Inc. Bus protocol independent method and structure for managing transaction priority, ordering and deadlocks in a multi-processing system
US6996651B2 (en) 2002-07-29 2006-02-07 Freescale Semiconductor, Inc. On chip network with memory device address decoding
CN1320464C (zh) * 2003-10-23 2007-06-06 英特尔公司 用于维持共享高速缓存一致性的方法和设备
JP2005135359A (ja) * 2003-10-31 2005-05-26 Hitachi Hybrid Network Co Ltd データ処理装置
US7243205B2 (en) 2003-11-13 2007-07-10 Intel Corporation Buffered memory module with implicit to explicit memory command expansion
US7590797B2 (en) 2004-04-08 2009-09-15 Micron Technology, Inc. System and method for optimizing interconnections of components in a multichip memory module
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US7412353B2 (en) * 2005-09-28 2008-08-12 Intel Corporation Reliable computing with a many-core processor
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US20070168620A1 (en) * 2006-01-19 2007-07-19 Sicortex, Inc. System and method of multi-core cache coherency

Also Published As

Publication number Publication date
JP5419107B2 (ja) 2014-02-19
TW200945048A (en) 2009-11-01
CN101999115B (zh) 2014-04-02
US20110093660A1 (en) 2011-04-21
WO2009128981A1 (en) 2009-10-22
US7941637B2 (en) 2011-05-10
US20090259825A1 (en) 2009-10-15
US8090913B2 (en) 2012-01-03
JP2011517003A (ja) 2011-05-26
CN101999115A (zh) 2011-03-30

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