CN106815176A - 用于经由柔性寄存器访问总线传输访问请求的系统和方法 - Google Patents
用于经由柔性寄存器访问总线传输访问请求的系统和方法 Download PDFInfo
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- CN106815176A CN106815176A CN201611091645.6A CN201611091645A CN106815176A CN 106815176 A CN106815176 A CN 106815176A CN 201611091645 A CN201611091645 A CN 201611091645A CN 106815176 A CN106815176 A CN 106815176A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17306—Intercommunication techniques
- G06F15/17312—Routing techniques specific to parallel machines, e.g. wormhole, store and forward, shortest path problem congestion
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201562261640P | 2015-12-01 | 2015-12-01 | |
US62/261,640 | 2015-12-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106815176A true CN106815176A (zh) | 2017-06-09 |
CN106815176B CN106815176B (zh) | 2022-09-16 |
Family
ID=57708276
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201611091645.6A Active CN106815176B (zh) | 2015-12-01 | 2016-12-01 | 用于经由柔性寄存器访问总线传输访问请求的系统和方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10628373B2 (zh) |
EP (1) | EP3176701B1 (zh) |
CN (1) | CN106815176B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113014606A (zh) * | 2021-05-25 | 2021-06-22 | 中国人民解放军国防科技大学 | 一种网络芯片中硬件模块的访问装置及方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9654645B1 (en) * | 2014-09-04 | 2017-05-16 | Google Inc. | Selection of networks for voice call transmission |
CN108256209A (zh) * | 2018-01-15 | 2018-07-06 | 郑州云海信息技术有限公司 | 一种菊花链布线时钟信号传输路径电路 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1543618A (zh) * | 2000-10-20 | 2004-11-03 | 快速转动设计系统公司 | 使用综合用于有效数据加载和下载的基于分组的协议的逻辑的硬件辅助的设计验证系统 |
CN1758208A (zh) * | 2005-10-28 | 2006-04-12 | 中国人民解放军国防科学技术大学 | 对挂接在片外单总线上的多种存储器进行访问的方法 |
CN101933005A (zh) * | 2008-02-15 | 2010-12-29 | 飞思卡尔半导体公司 | 外围模块寄存器访问方法和装置 |
US20140082238A1 (en) * | 2012-09-14 | 2014-03-20 | Nvidia Corporation | Method and system for implementing a control register access bus |
US8719517B2 (en) * | 2009-02-27 | 2014-05-06 | Hangzhou Synochip Technologies Co. Ltd | Method and apparatus for executing a program by an SPI interface memory |
CN104834621A (zh) * | 2014-02-10 | 2015-08-12 | 英特尔公司 | 嵌入式通用串行总线解决方案 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6073233A (en) | 1997-10-08 | 2000-06-06 | Cisco Technology, Inc. | Method and apparatus for distributing and accessing configuration registers |
US8407451B2 (en) * | 2007-02-06 | 2013-03-26 | International Business Machines Corporation | Method and apparatus for enabling resource allocation identification at the instruction level in a processor system |
US8789170B2 (en) * | 2010-09-24 | 2014-07-22 | Intel Corporation | Method for enforcing resource access control in computer systems |
WO2012167396A1 (en) | 2011-06-07 | 2012-12-13 | Telefonaktiebolaget L M Ericsson (Publ) | An innovative structure for the register group |
US9183147B2 (en) * | 2012-08-20 | 2015-11-10 | Apple Inc. | Programmable resources to track multiple buses |
US9858222B2 (en) * | 2014-11-13 | 2018-01-02 | Cavium, Inc. | Register access control among multiple devices |
-
2016
- 2016-11-30 US US15/364,503 patent/US10628373B2/en active Active
- 2016-12-01 EP EP16201663.8A patent/EP3176701B1/en active Active
- 2016-12-01 CN CN201611091645.6A patent/CN106815176B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1543618A (zh) * | 2000-10-20 | 2004-11-03 | 快速转动设计系统公司 | 使用综合用于有效数据加载和下载的基于分组的协议的逻辑的硬件辅助的设计验证系统 |
CN1758208A (zh) * | 2005-10-28 | 2006-04-12 | 中国人民解放军国防科学技术大学 | 对挂接在片外单总线上的多种存储器进行访问的方法 |
CN101933005A (zh) * | 2008-02-15 | 2010-12-29 | 飞思卡尔半导体公司 | 外围模块寄存器访问方法和装置 |
US8719517B2 (en) * | 2009-02-27 | 2014-05-06 | Hangzhou Synochip Technologies Co. Ltd | Method and apparatus for executing a program by an SPI interface memory |
US20140082238A1 (en) * | 2012-09-14 | 2014-03-20 | Nvidia Corporation | Method and system for implementing a control register access bus |
CN104834621A (zh) * | 2014-02-10 | 2015-08-12 | 英特尔公司 | 嵌入式通用串行总线解决方案 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113014606A (zh) * | 2021-05-25 | 2021-06-22 | 中国人民解放军国防科技大学 | 一种网络芯片中硬件模块的访问装置及方法 |
CN113014606B (zh) * | 2021-05-25 | 2021-07-23 | 中国人民解放军国防科技大学 | 一种网络芯片中硬件模块的访问装置及方法 |
Also Published As
Publication number | Publication date |
---|---|
EP3176701A1 (en) | 2017-06-07 |
CN106815176B (zh) | 2022-09-16 |
US10628373B2 (en) | 2020-04-21 |
US20170154010A1 (en) | 2017-06-01 |
EP3176701B1 (en) | 2020-04-29 |
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