TW200943113A - Improved uniformity for semiconductor patterning operations - Google Patents

Improved uniformity for semiconductor patterning operations

Info

Publication number
TW200943113A
TW200943113A TW098101710A TW98101710A TW200943113A TW 200943113 A TW200943113 A TW 200943113A TW 098101710 A TW098101710 A TW 098101710A TW 98101710 A TW98101710 A TW 98101710A TW 200943113 A TW200943113 A TW 200943113A
Authority
TW
Taiwan
Prior art keywords
semiconductor device
layer
sacrificial material
dataset
improved uniformity
Prior art date
Application number
TW098101710A
Other languages
English (en)
Inventor
Christophe Pierrat
Original Assignee
Cadence Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cadence Design Systems Inc filed Critical Cadence Design Systems Inc
Publication of TW200943113A publication Critical patent/TW200943113A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW098101710A 2008-01-16 2009-01-16 Improved uniformity for semiconductor patterning operations TW200943113A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/014,958 US7926001B2 (en) 2008-01-16 2008-01-16 Uniformity for semiconductor patterning operations

Publications (1)

Publication Number Publication Date
TW200943113A true TW200943113A (en) 2009-10-16

Family

ID=40885617

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098101710A TW200943113A (en) 2008-01-16 2009-01-16 Improved uniformity for semiconductor patterning operations

Country Status (5)

Country Link
US (1) US7926001B2 (zh)
JP (1) JP2011514654A (zh)
CN (1) CN101918948B (zh)
TW (1) TW200943113A (zh)
WO (1) WO2009091664A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI677011B (zh) * 2015-01-29 2019-11-11 南韓商三星電子股份有限公司 製造半導體裝置的方法

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US7908578B2 (en) 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
MY152456A (en) 2008-07-16 2014-09-30 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9122832B2 (en) * 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8327301B2 (en) * 2009-02-03 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Routing method for double patterning design
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US8739095B2 (en) * 2010-03-08 2014-05-27 Cadence Design Systems, Inc. Method, system, and program product for interactive checking for double pattern lithography violations
KR101828492B1 (ko) * 2010-10-13 2018-03-29 삼성전자 주식회사 패턴 형성 방법, 레티클, 및 패턴 형성 프로그램이 기록된 기록 매체
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8586478B2 (en) * 2011-03-28 2013-11-19 Renesas Electronics Corporation Method of making a semiconductor device
US8799834B1 (en) * 2013-01-30 2014-08-05 Taiwan Semiconductor Manufacturing Company Limited Self-aligned multiple patterning layout design
US8966412B1 (en) * 2013-09-24 2015-02-24 Globalfoundries Inc. Methods of generating circuit layouts that are to be manufactured using SADP techniques
JP2017067442A (ja) 2013-12-27 2017-04-06 株式会社日立ハイテクノロジーズ パターン測定装置、及びパターン測定のためのコンピュータープログラム
KR102185281B1 (ko) * 2014-01-09 2020-12-01 삼성전자 주식회사 자기 정렬 더블 패터닝 공정을 이용하여 반도체 소자의 패턴을 형성하는 방법
TWI638385B (zh) * 2015-03-31 2018-10-11 聯華電子股份有限公司 半導體裝置的圖案化結構及其製作方法
KR20220085622A (ko) 2020-12-15 2022-06-22 삼성전자주식회사 반도체 메모리 소자

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JP2002148779A (ja) 2000-11-07 2002-05-22 Toshiba Corp マスクパターン補正方法、フォトマスク及びマスクパターン補正方法プログラムを格納したコンピュータ読み取り可能な記録媒体
JP3479052B2 (ja) * 2001-04-23 2003-12-15 沖電気工業株式会社 半導体装置のダミー配置判定方法
JP3565268B2 (ja) * 2001-06-22 2004-09-15 株式会社東芝 磁気抵抗効果素子、磁気ヘッド及び磁気再生装置
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KR100476924B1 (ko) 2002-06-14 2005-03-17 삼성전자주식회사 반도체 장치의 미세 패턴 형성 방법
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US7234128B2 (en) * 2003-10-03 2007-06-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method for improving the critical dimension uniformity of patterned features on wafers
KR100732753B1 (ko) * 2004-12-23 2007-06-27 주식회사 하이닉스반도체 반도체 장치 제조방법
US7390746B2 (en) 2005-03-15 2008-06-24 Micron Technology, Inc. Multiple deposition for integration of spacers in pitch multiplication process
US7600212B2 (en) 2005-10-03 2009-10-06 Cadence Design Systems, Inc. Method of compensating photomask data for the effects of etch and lithography processes
US7316872B2 (en) * 2005-10-17 2008-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Etching bias reduction
US7741221B2 (en) * 2005-12-14 2010-06-22 Freescale Semiconductor, Inc. Method of forming a semiconductor device having dummy features
JP4171032B2 (ja) * 2006-06-16 2008-10-22 株式会社東芝 半導体装置及びその製造方法
US7669176B2 (en) * 2007-09-14 2010-02-23 Infineon Technologies Ag System and method for semiconductor device fabrication using modeling
US8440569B2 (en) * 2007-12-07 2013-05-14 Cadence Design Systems, Inc. Method of eliminating a lithography operation
JP5193582B2 (ja) * 2007-12-12 2013-05-08 株式会社東芝 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI677011B (zh) * 2015-01-29 2019-11-11 南韓商三星電子股份有限公司 製造半導體裝置的方法

Also Published As

Publication number Publication date
US20100299646A1 (en) 2010-11-25
CN101918948B (zh) 2013-07-24
US7926001B2 (en) 2011-04-12
WO2009091664A1 (en) 2009-07-23
CN101918948A (zh) 2010-12-15
JP2011514654A (ja) 2011-05-06

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