TW200939353A - Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method - Google Patents

Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method Download PDF

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TW200939353A
TW200939353A TW097136610A TW97136610A TW200939353A TW 200939353 A TW200939353 A TW 200939353A TW 097136610 A TW097136610 A TW 097136610A TW 97136610 A TW97136610 A TW 97136610A TW 200939353 A TW200939353 A TW 200939353A
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layer
substrate
germanium
gate
well
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TW097136610A
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Jin Cai
Amlan Majumdar
Tak H Ning
Zhibin Ren
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Ibm
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200939353 九、發明說明： 【發明所屬之技術領域】 本發明的示範具體實施例一般有關互補金氧半導 體（CMOS)場效電晶體(FET)，尤其有關在絕緣層上矽 (SOI)基板或塊狀Si基板上形成具有氮氧化物/多晶矽 或高K/金屬閘極堆疊之超陡峭退型井（SSRW)FET的方 法。 © 【先前技術】 CMOS FET廣泛用於電子電路應用，諸如信號處 理、計算、及無線通信等非限制性範例。由於縮小成比 較小的尺寸，CMOS電路中N通道FET(NFET)及P通 道FET(PFET)二者的閘極長度因而可增加CMOS電路 的速度。然而，有害的短通道效應造成CMOS裝置中 的高關閉狀態漏電流’因而增加功率消耗。在極大的短 通道效應情況下，CMOS電路將無法操作。 @ 光暈換雜是業界常用來減小短通道效應 (short-channel effect; SCE)的技術。圖 1八及 分別顯 系SOI晶圓及塊狀Si上之習用光軍推雜fet的橫截 面。然而’光暈摻雜導致以下幾個大家所熟知的問題： 1. 光暈摻雜在通道區域中引進離子化雜質，结果 造成MOSFET反轉層中的載子移動率降低。 2. 光軍換雜物原子數目在統計上的波動一般稱為 6 200939353 「隨機摻雜物波動」，其隨著光暈摻雜密度增加而辦 加，因而造成臨限電壓很大的變化。這個問題對於靜^ 隨機存取記憶體(SRAM)電晶體尤其麻煩，而且很= 導致SRAM故障。 犯 3.光暈摻雜引起對源極/汲極延伸區域的部分補 償’因而增加FET外部串聯電阻。 SSRW FET是具有未摻雜通道及重摻雜橫向均勻 霤 接地平面的裝置幾何形態，預期其比起SOI或塊狀Si 基板上的習用光暈摻雜裝置，將呈現較佳的短通道控 制、較佳的載子傳輸特性、較佳的臨限電壓變化、及較 低的寄生串聯電阻。對於SSRWFET，重摻雜接地平面 的存在將導致比習用光暈摻雜裝置顯著改良的SCE。在 SSRWFET中，並不需要光暈摻雜，因為接地平面可實 現控制SCE的功能及避免上文所提出的光暈摻雜問題。 ❹ 先前技術之製造SSRW FET的方法遭遇各種問 題，因而所形成的電晶體也無法展現SSRWFET預期應 有的優點。現已明確制定SSRW結構的特性如下。 1. 對於未摻雜通道厚度及接地平面摻雜具有正確 選擇的SSRW FET比起SOI或塊狀Si基板上的習用光 暈換雜裝置呈現更優異的短通道效應。 2. SSRW FET不應遭遇M〇SFET反轉層中載子移 動率的降低，因為通道區域未經摻雜或為輕摻雜（<1〇i6 7 200939353 cm 質， 表面摻雜濃度）’因此，通道實質上々有離 -, 3. SSRW FET不應遭遇隨機摻 臨!電壓變化’因為通道區域未經捧雜且重 面退離表面區域❶ ’ 平 4· SSRW FET不應遭遇fEt认* 加，因為其中並沒有補償源極/没極延= = 2 入0
另外，MOSFET所需要的一些其他特性如下所述。 5. CMOS裝置應具有低的接面漏電流，以降低電晶 體的淨關閉狀態電流，因而降低CM〇S電路功率消耗。 6. CMOS裝置應具有低的深源極/汲極至井接面電 容’以降低寄生電容’因而増加CMOS電路速度。 美國專利6,423,601 Bl(Ishida等人)教導使用氮及 〇 硼的共同植入來形成NFET的p型井區域，其掺雜物濃 度輪廓為拋物線形狀。雖然拋物線形狀的摻雜物輪廓對 於塊狀Si基板上的CMOS可提供貫穿停止器的優點， 但其輪廓不夠鮮明，無法降低閘極長度低於30 nm之 CMOS電晶體的短通道效應，因此，無法滿足上述特性 ⑴。 美國專利7,199,430 B2(Babcock等人）教導使用橫 8 200939353 向均勻含碳層或碳光暈的共同植入，以防止井植入擴散 至通道區域中。如其申請專利範圍中所述’含碳層必須 含有裏少〇· 1原子百分比的碳，也就是說’碳漢度必須 大於5 X 1019cm·、大家都知道在深源極/汲極區域附近 的高劑量雜質濃度會導致大的接面漏電流，因而增加 CMOS裝置的淨關閉狀態漏電流，因此無法滿足上述特 性(5)。 美國專利申請案2007/0128820 Al(Majumdar等人) 說明一種使用可移除閘極製程形成自我對準退型井以 降低接面電容及接面漏電流的方法。此方法涉及建立退 型井的高能量離子植入。大家都知道高能量植入具有大 的垂直分散’因此’無法導致超陡峭退型井植入輪廓。 因此’此方法無法滿足上述特性（1”此外，閘極長度 低於30nm的可移除閘極製程還因間隙大小低於3〇11111 之間隙填充的問題，導致低的裝置及電路良率。 美國專利6,881，987 B2(Sohn)說明塊狀Si晶圓上的 退型井PFET結構，及提供製成表面摻雜濃度Cpi X 10 cni之3亥結構的方法，如本文中圖1 c(其重現兮直 利的圖5)所示。 美國專利 6,927,137 B2(Chakravarthi 等人） 7,061，058 B2(Chakravarthi等人）說明製造退型井卿^ 9 200939353 的方法。該方法涉及形成習用的硼P井，及在閘極介電 層中使用氫植入，以在後續源極/汲極活化退火期間， 將在表面附近的硼吸引至閘極介電層中。此方法造成表 面摻雜濃度Cs〜1 X 1018 cm-3，如本文圖1D所示（其重 現該專利的圖2)。 使用美國專利 6,881，987 B2(Sohn)、6,927，137 B2(Chakravarthi 等人）、及 7,061，058 B2(Chakravarthi © 等人）中的方法所達成的表面摻雜濃度Cs〜1017-1018 cm3低於習用光暈摻雜裝置中所達成的表面摻雜濃 度，但因為至少顯者的離子化雜質散布而未低到足以實 現實質的移動率優點。因此’以上方法無法滿足上述特 性(2)。 美國專利6,881，641 B2(Wieczorek等人)說明塊狀 Si晶圓上的退型井FET結構，其中「在離子植入步驟 〇 之後在井結構上提供磊晶生長通道層，及執行熱處理步 驟以在井結構中建立所要的摻雜物輪廓」。此專利說明 在STI形成之後形成井區域：「在形成淺溝渠隔離3〇2 之後’藉由離子植入定義P井結構310及η井結構 320」。這表示在STI形成之後磊晶生長通道區域。 美國專利7,002,214 Bl(Boyd等人)說明超薄S0I 基板上的退型井FET結構，其中在退型井離子植入及 200939353
STI形成之後，形成未摻雜的磊晶Si覆蓋層。如本文圖 1E(其重現該專利的圖4)所示的製程不適合維持圖1F 所示退型井植入輪廓的陡峭，圖1F重現在以下著作中 所見的圖 6: Z· Ren、M. Ieong、J. Cai、J. Holt、D. Boyd、 R. Mo、H. Yin、O. Dokumaci、S. Kawanaka、Τ· Sato、 P. Ronsheim、J. Wang、C. Y· Sung、及 W. Haensch 的「選 擇性磊晶通道接地平面薄SOI CMOS裝置（Selective epitaxial channel ground plane thin SOI CMOS e devices)」，IEDM Technical Digest，2005 年 12 月。 美國專利 6,881,641 B2(Wieczorek 等人）及 7,002,214 Bl(Boyd等人)均提供製造退型井FET的方 法，其中在STI形成之後執行Si覆蓋層磊晶成長。然 而，在STI形成之後執行Si覆蓋層磊晶成長導致si覆 蓋層厚度的不均勻，其進而作用有如另一個變化來源， 結果造成電晶體大的臨限電壓變化。因此，以上方法無 ❿ 法滿足上述特性(3)。此外，諸如SRAM所使用的窄寬 度裝置上的Si磊晶，將因不同晶向上有所差別的生長 速率造成小面生長’如圖1G所圖示。這將導致STI邊 緣附近閘極電極下的高電場及大的漏電流，因而增加 CMOS裝置的淨關閉狀態漏電流。 θ 以上美國專利及出版物所說明的退型井妗構 及其形成方法’均無法滿足一般對於SSRW結構所有所 11 200939353 定優點（上述特性1-4)且亦無法滿足CM〇s電路中 CMOS電晶體所要的基本特性(上述特性5及6)。因此 極需要提供一種製造SSRW CMOS裝置的方法可以滿
足上述SSRWFET及CMOSFET的所有所需特性(上 特性 1-6)。 ,L 【發明内容】 根據本發明之示範具體實施例，克服了上述及其 _並實現其㈣點。 根據本發明之一方面，係提供一種製造半導體裝置 的方法，其中該方法包括：提供由結晶矽所構成的一基 板，在結晶矽中植入一接地平面以與基板之一表面相 鄰該接地平面係植入以呈現一所要的超陡ώ肖退型井植 入摻雜輪廓；使用一實質上無擴散熱退火使植入損壞退 火，以在結晶矽中維持所要的超陡峭退型植入摻雜輪 © 廓；及在執行一淺溝渠隔離製程之前，在基板之表面 沈積一矽覆蓋層。 在本發明的示範性及非限制性具體實施例中，基板 ，塊狀Si基板或絕緣層上矽基板，該方法適於使用氮 兔化物閘極堆疊結構或高介電常數氧化物/金屬（高 金屬）閘極堆疊結構，及選擇/控制在製造期間所使用的 各種熱製程，以在結晶石夕中維持所要的超陡峭退型井植 12 200939353 入摻雜輪廓。 ❹
根據本發明之另一方面，一種半導體結構包含：由 結晶矽所構成的一基板；在結晶矽中與基板之一表面相 鄰的一接地平面，該接地平面呈現一超陡峭退型井摻= 輪廓；在基板之表面上的一矽覆蓋層，該矽覆蓋層^質 上，有小面形成；及圍繞一主動裝置區且經形成穿過矽 覆蓋層及至底下結晶石夕基板的一溝渠隔離區域。" 較佳是以矽磊晶製程於約7〇〇〇c或以下的溫 持所要的超_退型井摻雜輪廓： :::==:離區域之前執行，溝渠 ^發明之又另一方面，互 電晶體另外包括：在該基板之面^摻雜輪廓。場效 其中石夕覆蓋層實質上沒有小 面上的―石夕覆蓋層， 域，其圍繞一主動梦 /，及一溝渠隔離區 板的底下結晶♦中I;、=成f過❸覆蓋層及至基 r ~政電晶體另冰、， 區内設置在矽覆蓋層上的-閘極氧化2:在主動裝置 閘極結構之-，❻置在_結構上 13 200939353 中多晶矽層摻雜有適於形成η型或p型場效電晶體之一 的一摻雜物種。 【實施方式】 本發明示範具體實施例提供在SOI或塊狀Si基板 上製造具有例如多晶石夕/氮氧化物或高κ/金屬閘極堆叠 之SSRW FET結構的方法，其中所形成的FET結構呈 現超陡峭退型井。 e 圖3至11所描繪之本發明示範具體實施例的以下 說明預計均配合圖2所示總製程來參閱。 參考圖3A及3B’起始基板可以是SOI晶圓i〇A(圖 3A)或塊狀Si晶圓10B(圖3B)。s〇l晶圓1〇A可以是 30-90 nm範圍之s〇I厚度的厚s〇I晶圓，或可以是 15-30 nm範圍之SOI厚度的薄SOI晶圓。對於厚S0I ❹ 起始晶圓10A的情況，可使用例如氧化及氫氟酸(HF) 濕式蝕刻，執行SOI薄化以降低SOI厚度至15_3〇 nm 範圍，如大家所熟知的。換言之，晶圓類型（SC)I或塊 狀）的初始選擇對於本發明的實行並非限制。
在任一情況中，使晶圓1〇氧化，以建立標稱2-10 _—的氧化物遮蔽層12。此氧化物層12係用於對準標 記定義及作為植入遮蔽層，其說明如下。圖3A及3B 200939353 分別顯示在此步驟之後的SOI晶圓10A及塊狀Si晶圓 10B的橫截面。 如圖4所示，接著使用光微影及反應性離子蝕刻 (RIE)以在毯狀晶圓（blanket wafer) 1 〇a、10B的頂面上 建立對準標記14。對準標記係用於後續建立NFET及 PFET之SSRW井的光微影步驟。晶圓1〇A、1〇B在對 準建立之後的俯視圖如圖4所示。 ❹ 接著使用光微影、離子植入、及光阻(PR)剝離製 程，執行CMOS SSRW井植入。光微影係用於選擇性定 義井植入的NFET或PFET區。NFET井離子植入涉及 P型植入物種，諸如B、Β]ρ2、或In ;而pFET井離子植 入涉及η型植入物種，諸如As、p、或％。所有ssRw 井植入的典型劑量介於1〇13至1014 cm·2。典型的植入 能量範圍對B約0.2至1 keV，對BF2約1至5 keV， ® f In 約 5-30 keV ’ 及對 As、P、及 Sb 約 5-25 keV。注 =二對於塊狀Si晶圓i0B的情況，還使用額外較高的 月b量井植入以提供井隔離。對於井隔離植入，典型劑量 介於1012至1013cm-2。典型植入能量範圍對As、p、及 BF2 約 100-300 keV 及對 b 約 2〇_6〇 keV。 離子植入對使用熱退火固化的Si造成損壞。習用 CMOS處理涉及使用快速熱退火(RTA”其rta溫度通 15 200939353 ❹
常高於900°C，及RTA時間通常大於1秒。然而，已 知此類型的熱預算將造成顯著的井植入擴散，導致既寬 又淺的井植入輪廓，而非所要的超陡峭退型井輪靡。因 此，本發明的示範具體實施例改採實質上無擴散的熱退 火技術，諸如毫秒雷射退火或急速退火，以解決植入損 壞並維持SSRW井植入輪廓的陡峭。合適的雷射退火或 急速退火溫度介於1100°C至1350°C，且退火時間少於 〜10毫秒。圖5A及5B分別顯示SOI晶圓1〇A及塊狀 Si晶圓10B在此步驟之後的橫截面，及分別圖解掺雜 SOI接地平面（GP)16a及Gp井16B的出現。另外注意， 分別在晶圓10A及10B中的未摻雜SOI 18A及未推雜 塊狀Si 18B的區域，其由植入步驟期間所使用的光阻 現參考圖6A及6B，在摻雜晶圓l〇A、1〇B上分別 沈積未摻雜Si覆蓋層2G，以建立未摻雜(特意未^雜) 通道區域。執行以沈積si覆蓋層2〇的Si磊晶 佳是在低溫下（諸如約·。c或以下），以避免ssrw 植入在磊晶期間移動（擴散）。在Si覆蓋 前，諸如藉由❹氫氟酸，移除遮蔽氧化物層^長之 根據本發料範具财關之—Μ 成之前在毯狀晶圓、議上執行= 層20初晶成長將使si覆蓋層2〇的厚度非常均勻及 200939353 亦可避免*窄主動區裝置（諸如靜態RAM(SRAM)電晶體) 之s'覆蓋層2〇的小面形成，小面形成是在sti形成之 後執行Si覆蓋層2〇蠢晶成長時可能發生的問題。 作為非限制性範例，已處理裝置（即，在生產線末 端）之短閘極長度裝置的覆蓋層厚度通常約 5-10nm。依 據此點，覆蓋層沈積目標約12-17nm,因為預期在各種 製程期間（如，在襯墊氧化、厚閘極氧化、及薄閘極氧 ® 化期間）通常會損失約7nm的Si覆蓋層。 接著使用襯墊膜沈積、光微影、及反應性離子蝕刻 (RIE) ’執行主動區定義。在此方面可參考只顯示s〇i 晶圓10A具體實施例的圖11A及11B，已知塊狀Si晶 圓10B具體實施例的處理實質上相同。襯墊膜較佳是 襯塾氧化物層21A(如，2-10 nm)及概墊氮化物層 21B(如，30-150 nm)。對襯墊氧化物及襯墊氮化物製程 ❿ 均加以控制，可呈現低熱預算以維持SSRW井植入輪廓 的陡峭。可使用例如電漿輔助氧化或低溫氧化物沈積， 形成襯墊氧化物層21A。可使用例如快速熱化學氣相沈 積(RTCVD)或電漿增強化學氣相沈積(PECVD)，形成襯 墊氮化物層21B。接著執行光微影，用光阻定義主動 區。接著執行氮化物/氧化物/Si RIE及其後的光阻剝 離，以建立主動區。 17 200939353 接著執行淺溝渠隔離（STI)製程，以建立裝置隔 離。STI製程包括STI氧化物沈積及STI氧化物CMP(化 學機械抛光）’其止於底下形成STI區域22的槪塾氮化 物層21B。接著分別使用例如HF及熱磷酸濕式蝕刻， 移除襯塾氮化物上任何剩餘的STI氧化物（由於在CMP 製程期間未完全移除氧化物）及襯墊氮化物21B。最 後，使用HF移除襯墊氧化物層21A，產生如圖7入所 示結構。 圖7A及7B分別顯示SOI ι〇Α及塊狀別晶圓ι〇Β 在STI 22形成製程之後的晶圓橫截面。 由於大多數的微電子晶片在晶片上具有以高於其 他電路(如’高速電路）的電壓操作的輸人/輸出剛裝 置，因此需要對UO裝置提供厚_氧化物。因此，較 ❹ 佳是先在整個晶圓、_上執行厚閘極氧化。須控 極氧化製程以呈現低熱預算’以維持SSRW井 植入輪廊的陡Λ肖。 傲電子晶片中的高速裝置 物。因此’使用光微影對厚氧化物裴置施以遮用匕 化^置區移除厚氧化物，接著執行PR剝 離接者執仃薄閘極氧化製程。例如 _…魏切(S讀）、^κ(高介 18 200939353 作為薄閘極氧化物^ Si02或SiON可使用習用快速熱氧 化工具开> 成’两K氧化物則可使用有機金屬化學氣相 沈積(MOCVD)或原子層沈積(Ald)工具沈積。須控制所 選之建立薄閘極氡化物的方法以具有低熱預算，以維持 SSRW井植入輪廓的陡峭。 所形成的閘極氧化物層24如圖8A及8B所示，所 形成的高K氧化物/金屬閘極結構30、32則如圖8c及 ® 8D所示。 更明確地說，接著執行FET閘極多晶矽沈積或金 屬閘極沈積及其後的多晶矽覆蓋層沈積，以形成多晶矽 /氮氧化物閘極24(圖8A、8B)或高K/金屬閘極堆疊30、 32(圖8C及8D)。高K氧化物30的非限制性範例為 Hf〇2、Zr〇2、及Ti2〇5 ’及相關聯金屬閘極32的非限制 性範例為TiN及TaN。金屬閘極層32可使用物理氣相 φ 沈積(PVD)工具、或MOCVD或ALD工具來沈積。閘 極多晶矽層26的Si可在低壓化學氣相沈積(lpcvd)工 具或濺鍍si工具中沈積。接著可用遮蔽氧化物層28(多 晶石夕遮蔽氧化物）覆蓋所形成的閘極多晶石夕層26。多晶 矽遮蔽氧化物層28經建立以對閘極植入提供遮蔽。多 晶矽遮蔽氧化物層28可在PECVD或RTCVD工具中沈 積0 19 200939353 圖8A、8B、8C、及8D分別顯示以下項目在此步 驟之後的橫戴面：具有多晶矽/氮氧化物閘極堆疊結構 24的SOI晶圓l〇A ;具有多晶矽/氮氧化物閘極堆疊結 構24的塊狀Si晶圓10B;具有高K/金屬閘極堆疊結構 30、32的SOI晶圓10A ;及具有高K/金屬閘極堆疊結 構30、32的塊狀Si晶圓10B。 接著摻雜閘極多晶矽26,以建立具有低電阻的低 閘極線路。需要低閘極線路電阻以達到FET的高速切 換。用η型閘極植入對NFET的選擇性摻雜及用p型閘 極植入對PFET的選擇性摻雜係使用光微影來達成。 NFET閘極植入涉及使用p型物種，諸如As、p、或Sb， PFET閘極植入則涉及使用型物種，諸如b、bf2、或 In。 —接著使用光微影、閘極RIE、PR剝離、及濕式清 洗定義電晶體閘極26A，以移除在閘極rie步驟期間形 fσ物。濕式清洗步驟可用移除多晶石夕遮蔽氧化物 層28的HF濕式蝕刻。 圓，多晶矽/氮氧化物閘極堆疊24、26Α的晶 極堆疊。所形化(如’ 2·5啲厚度）以覆蓋閘 所干。斜a日再氣(Γ6〇Χ)覆蓋層34如圖9八及犯 、有鬲κ/金屬閘極堆疊3〇、32、26A的晶 20 200939353 圓’沈積薄氮化物概層（如’ 2-5 nm厚度）以覆蓋閘極堆 疊。所形成的氮化物襯層36如圖9C及9D所示。氮化 物襯層36可用作氧的擴散障壁，及可防止在高κ氧化 物層30下形成不想要的Si〇2底層。此氧化物底層（又 稱為「下方氧化物」）的出現將降低閘極電容，及因而 降低電晶體導通電流。 接著執行快速熱退火以在多晶矽閘極26A中擴散 ® 閘極摻雜，同時不會在結晶Si GP中大幅擴散沾^植 入。在退火製程中使用RTA是可行的，因為在多晶別 中的摻雜物擴散速率顯著比在結晶Si中快。對於圖9C 及9D的具體實施例，此退火步驟亦可用作一般為提高 具有高K/金屬閘極堆疊30、32之晶圓之載子移動率所 需要的rfjK退火步驟。 ，參考圖10A至10D，接下來藉由沈積氧化物層 0 及接著執行氧化物RIE，以形成偏移間隙壁36A。接著 執行CMOS延伸植入38。此涉及光微影、離子植入、 及PR剝離。光微影係用於選擇性定義延伸植入的 或PFET區。NFET延伸植入為n型物種，諸如As、p、 或Sb ’·及PFET延伸植入為p型物種諸如B、Bp〗、或 In。注意並未執行光暈植入。 接著形成深源極/汲極（SD)植入42所需的最終間隙 21 200939353 壁40及自我對準矽化物44、46。此涉及氧化物襯層及 間隙壁氮化物沈積及其後的氮化物RIE。可使用RTCVD 或PECVD工具沈積氧化物及氮化物層。 在形成最終間隙壁40之後，執行CMOS深SD植 入42。此涉及光微影、離子植入、及阻劑剝離。光微 影係用於選擇性定義深SD植入的NFET或PFET區。 NFET深SD離子植入涉及n型物種，諸如As、P、或 ❹ Sb，而PFET深SD離子植入涉及p型物種，諸如B、 BF2、或In。對於S0I晶圓（圖10A、i〇c)，深SD植入 經設計以建立鄰接埋藏氧化物(BOX)的深SD接面，因 而消除深SD至井接面的電容。對於塊狀Si晶圓（圖 10B、10D) ’深SD植入經設計以在深SD區域底部建 立漸變接面’使深SD至井接面電容損失減到最小。深 SD至井接面電容是降低cmos電路切換速度的寄生電 容。 ❹ 接著使晶圓10A、10B經受毫秒雷射退火或急速退 火’以活化延伸38及深SD 42植入，同時維持SSRW 井植入輪廓的陡峭。注意，在此階段使用習用的RTA， 由於深SD植入所造成的損壞，對於深sd 42邊緣附近 之SSRW植入的陡峭尤其有害。大家都知道此種損壞在 RTA期間將導致摻雜物的擴散速率提高。 22 200939353 裝置製造的前端部分結束於石夕化物44、46形成。 此涉及移除氧化物的HF濕式蝕刻、金屬沈積、矽化物 形成退火、及移除使矽化物保持未受影響之未反應金屬 的選擇性濕式蝕刻。合適的金屬包括但不限於Ni、Co、 及Pt。 圖10A-10D分別顯示以下項目在此步驟之後的橫 截面：具有多晶石夕/氮氧化物閘極堆疊的SOI晶圓10A ; ❹ 具有多晶矽/氮氧化物閘極堆疊的塊狀Si晶圓10B ;具 有高K/金屬閘極堆疊的SOI晶圓l〇A ;及具有高K/金 屬閘極堆疊的塊狀Si晶圓10B。 始於應力氮化物沈積之製造的其餘部分可根據習 用的電晶體處理來完成，在此將不詳細說明。 應明白’使用本發明示範具體實施例，可在SOI ❹ 或塊狀Si基板上製造具有例如多晶矽/氮氧化物或高κ/ 金屬閘極堆4的SSRW FET結構，其中所形成的FET 結構呈現超陡峭退型井。 熟習相關技術者參考以上說明並結合附圖及隨附 申請專利範圍，即可瞭解各種修改及改變。僅作為一些 範例’熟習本技術者可嘗試使用其他相似或同等材料及 /或處理設備。然而’對於本發明教示的所有此類及相 23 200939353 似修改仍屬於本發明的範疇。 此外，各種所揭示的層厚度及厚度範圍、處理溫 度、清洗及餘刻組成物及其類似物係用於按照示範性意 義來參閱非料加諸於本發料範具體實施例之實 施的限制。 此外，本發明範例的一些特色可在未使用其他特色 © 的情況下用來獲得好處。因此’應將上述說明視為只是 本發明之原理、教示、範例及示範具體實施例的舉例說 明，而非其限制。 【圖式簡單說明】 當結合附圖參閱時，本發明具體實施例之上述其他 方面在「實施方式」中將變得更顯而易見，其中： 圖1A至1G圖解上述各種先前技術的方法。 ❾圖2是以如圖3及5至11所示半導體晶圓的橫截 面放大圖及如圖4所示俯視圖所示之本發明各種具體 實施例的總製程圖。 【主要元件符號說明】 10 晶圓 10A SOI晶圓 10B 塊狀Si晶 24 200939353
12 氧化物遮蔽層 14 對準標記 16A 摻雜SOI接地平面 16B GP井 18A 未掺雜SOI 18B 未掺雜塊狀Si 20 未摻雜Si覆蓋層 21A、21B 襯塾氧化物層 22 STI區域 24 閘極氧化物層 26 問極多晶碎層 26A 閘極 28 多晶矽遮蔽氧化物層 30 高K氧化物 32 金屬閘極 34 再氧化覆蓋層 36 氮化物襯層 36A 偏移間隙壁 38 CMOS延伸植入 40 最終間隙壁 42 深源極/汲極植入 44、46 矽化物 25

Claims (1)

  1. 200939353 十、申請4利範圍： 1· 一種製造一半導體裝置的方法，包含·· 提供由結晶矽所構成的一基板； 在該結晶矽中植入一接地平面以與該基板之一表 相鄰該接地平面係植人以呈現—所要的超陡崎退型 井植入摻雜輪廓； 實質上無擴散熱退火使植人損稿火，以在 ❹ 該、、了f中維持該所要的超_退型植人摻雜輪摩；及 =執打-歸雜離製程之前，在該基板之 上沈積一矽覆蓋層。 w 所才Γγ求項1之方法，其中财覆蓋層係*未摻雜梦 所構成，以為該半導體裝置提供一未摻雜通道區域。 1之方法，其中沈積财覆蓋層係以一梦 ❹戶斤要的超_退型井植入=輪廓皿度來執订，以維持該 制步，行該淺 2雜輪廓的襯墊膜沈積製程，在财覆= 置區主，裝置區；光微影定義在該襯墊膜上的該主動裝 渠ρ離-?主動區上保持該襯墊膜的-部分;沈積淺溝 一乳化物;及利用止於該底下襯塾膜的一製= 26 200939353 擇性移除該淺溝渠隔離氧化物，以形成圍繞該主動裝置 區及延伸穿過該矽覆蓋層及至該底下結晶矽基板中的 一溝渠隔離區域。 5. 如請求項4之方法，更包含：移除在該主動區内的 該襯墊膜，以暴露該底下矽覆蓋層；在該暴露矽覆蓋層 上形成一閘極氧化物結構；及在該閘極氧化物結構上沈 積一多晶石夕層。 6. 如請求項5之方法，更包含：用無論在該主動區内 之該裝置為一 η型或一 p型場效電晶體皆適用的一摻雜 物種摻雜該多晶矽層；光微影定義包括該閘極氧化物結 構及該摻雜多晶矽層之一覆蓋部分的一直立閘極堆疊 結構；形成一再氧化閘極堆疊結構覆蓋層；及執行一快 速熱退火以在該多晶矽層之該覆蓋部分中擴散該摻 雜，同時不會顯著影響該底下結晶矽中該所要的超陡峭 退型井植入摻雜輪廓。 7. 如請求項6之方法，更包含：在該再氧化閘極堆疊 結構覆蓋層上形成一偏移間隙壁；植入延伸；在該偏移 間隙壁上形成一最終間隙壁；植入深源極及汲極區域； 用經選擇不會顯著影響該底下結晶矽中該所要超陡峭 退型井植入摻雜輪廓的一熱製程退火，以活化該等植入 延伸及源極 >及極區域，及在該植入源極及〉及極區域上及 27 200939353 在該閘極堆疊結構上形成矽化物區域。 8. 如請求項7之方法，其中該基板係一絕緣層上矽基 板，其中該接地平面係形成於覆蓋一埋藏氡化物層的一 結晶矽層中，及其中該等深源極及汲極植入建立鄰接該 埋藏氧化物層的深源極汲極接面。 9. 如請求項7之方法，其中基板係一塊狀結晶矽基板， 其中植入一接地平面更包含植入一較高能量井以提供 井隔離’及其中該等深源極及汲極植入於該深源極及汲 極植入區域之一底部建立一漸變接面。 j〇.如凊求項4之方法，更包含：移除在該主動區内的 該襯墊膜，以暴露該底下矽覆蓋層；在該暴露矽覆蓋層 土形^一高介電常數氧化物/金屬閘極結構；及在該高 ^丨電常數氧化物/金屬閘極結構上沈積一多晶矽層。 u•如4求項1〇之方法，更包含：用無論在該主動區内 之該裝置為一η型或一p型場效電晶體皆適用的一摻雜 物種摻雜該多晶矽層；光微影定義包括該高介電常數氧 ，物/金屬閘極結構及該摻雜多晶矽層之一覆蓋部分的 直立閘極堆疊結構；形成—氮化物閘極堆疊結構覆蓋 層，1執行—快速熱退火以在該多晶矽層之該覆蓋部分 中擴散該摻雜，同時不會顯著影響該底下結晶矽中該所 28 200939353 要的超陡崎退型井植入摻雜輪摩。- 12.如清求項11之方法，更包含：在該氮化物閘極堆疊 結構覆蓋層上形成一偏移間隙壁；植入延伸；在該偏移 間隙壁上形成一最終間隙壁；植入深源極及汲極區域； 用經選擇不會顯著影響該底下結晶矽中該所要超陡峭 退i井植入摻雜輪廓的一熱製程退火以活化該等植入 延伸及源極汲極區域；及在該植入源極及汲極區域上及 在該閘極堆疊結構上形成矽化物區域。 3.如明求項12之方法，其中該基板係一塊狀結晶矽基 板，其中植入-接地平面更包含植入一較高能量井以提 供井隔離，及其”等賴極及祕植人於該賴極及 汲極植入區域之一底部建立一漸變接面。 14.一種半導體結構，包含： 〇 由結晶矽所構成的一基板； 在該結晶梦中與該基板之一表面相鄰的—接地平 面，該接地平面呈現一超陡峭退型井摻雜輪廓. 在該基板之該表面上的-韻蓋層，該’ 質上沒有小面形成；及 復蛊θ貫 ®繞-主動裝置區且經形成穿過該矽覆蓋 底下結晶矽基板的一溝渠隔離區域。 曰 29 200939353 15. 如請求項14之半導體結構，其中該基板係一絕緣層 上矽基板，及其中該接地平面係設置於覆蓋一埋藏氧化 物層的一結晶矽層中。 16. 如請求項14之半導體結構，其中該基板係一塊狀結 晶矽基板，及更包含一井植入以提供井隔離。 17. 如請求項14之半導體結構，其中以一矽磊晶製程於 © 約700°C或以下的一溫度形成該矽覆蓋層，以維持該所 要的超陡峭退型井摻雜輪廓，及該矽磊晶製程係在形成 該溝渠隔離區域之前執行，以將該溝渠隔離區域形成穿 過該碎覆蓋層。 18. 如請求項14之半導體結構，更包含設置在該矽覆蓋 層上的一閘極氧化物，及設置在該閘極氧化物結構上的 一多晶石夕層。 ❿ 19. 如請求項18之半導體結構，其中用無論在該主動區 内將成為一 η型或一 p型場效電晶體的一裝置皆適用的 一摻雜物種摻雜該多晶矽層，其中該閘極氧化物結構及 該摻雜多晶矽層之一覆蓋部分係設置在至少局部覆蓋 有一再氧化閘極堆疊結構覆蓋層的一閘極堆疊結構 内，及更包含設置在該再氧化閘極堆疊結構覆蓋層上的 一偏移間隙壁及設置在該偏移間隙壁上的一最終間隙 30 200939353 壁Ο 20·如明求項14之半導體結構，更包含設置在該石夕覆蓋 層一高介電常數氧化物7金屬閘極結構，及設置在 * 5丨電㊉數氧化物/金屬閘極結構上的一多晶碎層。 21.如請求項2〇之半導體結構，其中用無論在該主動區 二將成為一η型或一Ρ型場效電晶體的一裝置皆適用的 一摻雜物種摻雜該多晶矽層，其中該高介電常數氧化物 /金屬閘極結構及該摻雜多晶矽層之一覆蓋部分係設置 在至少局部覆蓋有一氮化物閘極堆疊結構覆蓋層的一 閘極，疊結構内’及更包含設置在該氮化物閘極堆疊結 構覆蓋層上的一偏移間隙壁及設置在該偏移間隙壁上 的一最終間隙壁。 22..種互補金氧半導體超陡峭退型井場效電晶體包 ® ί Λ絕緣層上絲板或—塊狀♦基板之一；在結晶石夕 中形成與該基板之—表面相鄰的—接地平面，該接地平 =具有形朗超㈣退型相—摻雜輪廓；在該基板之 一表面上的—♦覆蓋層’該碎覆蓋層實質上沒有小面形 f，圍繞—主動裝置區及其形成穿過該矽覆蓋層及至該 土板之該底下結晶碎中的—溝渠隔離區域；設置在該主 動裝置區内該石夕覆蓋層上的—閘極氧化物或-高K/金 屬閘極結構之—；及設置在該閘極結構上的-多晶石夕 31 200939353 層，該多晶石夕層摻雜有適於 晶體之一的一摻雜物種。 形成一 n型或一 p型場效電 :之;二生/:=所要的 ❹ ’ 5"溝仏離區域形成穿過财覆蓋層。 2曰4二1=22之互補金氧半導體超陡Λ肖退型井場效電 極氧化物及該摻雜多Μ層之-覆蓋部 二：椹在至少局部覆蓋有一再氧化覆蓋層的一閘極 隹疊二構内’及更包含設置在該再氧化覆蓋層上的一偏 移間隙壁及設置在該偏移間隙壁上的一最終間隙壁。 25.如请求項22之互補金氧半導體超陡峭退型井場效電 ❹ β曰體，其中該尚Κ/金屬閘極結構及該摻雜多晶石夕層之 一覆蓋部分係設置在至少局部覆蓋有一氮化物覆蓋層 的一閘極堆疊結構内，及更包含設置在該氮化物覆蓋層 上的一偏移間隙壁及設置在該偏移間隙壁上的一最欲 間隙壁。 ' 32
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