CN105826203A - 形成FinFET晶体管器件的方法和FinFET晶体管器件 - Google Patents

形成FinFET晶体管器件的方法和FinFET晶体管器件 Download PDF

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CN105826203A
CN105826203A CN201610059028.1A CN201610059028A CN105826203A CN 105826203 A CN105826203 A CN 105826203A CN 201610059028 A CN201610059028 A CN 201610059028A CN 105826203 A CN105826203 A CN 105826203A
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layer
csige
rsige
fin structure
tensile
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B·B·多里斯
何虹
王俊利
N·J·卢贝
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ST MICROELECTRONICS Inc
International Business Machines Corp
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ST MICROELECTRONICS Inc
International Business Machines Corp
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Abstract

本发明涉及形成FinFET晶体管器件的方法和FinFET晶体管器件。一种形成finFET晶体管器件的方法包括：在衬底之上形成结晶的压缩应变硅锗(cSiGe)层；掩蔽所述cSiGe层的第一区域，以暴露所述cSiGe层的第二区域；对所述cSiGe层的暴露的第二区域执行注入处理，以使其底部非晶化并将所述第二区域中的所述cSiGe层转变为弛豫SiGe(rSiGe)层；执行退火处理，以使所述rSiGe层再结晶；在所述rSiGe层上外延生长拉伸应变硅层；以及在所述拉伸应变硅层中和所述cSiGe层的所述第一区域中图案化鳍结构。

Description

形成FinFET晶体管器件的方法和FinFET晶体管器件
技术领域
本发明一般地涉及半导体器件制造，更具体地说，涉及在FinFET结构中集成应变硅锗(SiGe)和应变硅(Si)鳍(fin)。
背景技术
场效应晶体管(FET)广泛地用于电子工业以执行与模拟和数字电子信号相关的切换、放大、滤波及其它任务。其中最为常见的是金属氧化物半导体场效应晶体管(MOSFET或MOS)，在此类晶体管中，栅极结构被通电以在半导体体的下伏(underlying)沟道区域中产生电场，借此允许电子行进通过半导体体的源区与漏区之间的沟道。互补MOS(CMOS)器件已经广泛地用于半导体工业中，其中同时使用n型和p型(NMOS和PMOS)晶体管制造逻辑电路及其它电路。
FET的源区和漏区典型地通过将掺杂剂添加到位于沟道两侧的半导体体的目标区域中而形成。在沟道上方形成栅极结构，该栅极结构包括位于沟道之上的栅极电介质和位于栅极电介质上方的栅极导体。栅极电介质是绝缘体材料，其防止在对栅极导体施加电压时大的泄漏电流流入沟道中，同时允许所施加的栅极电压以可控的方式在沟道区域中建立横电场。常规的MOS晶体管典型地包括通过在硅晶片表面之上沉积或生长二氧化硅(SiO2)或氧氮化硅(SiON)而形成的栅极电介质，其中在SiO2之上形成掺杂的多晶硅以充当栅极导体。
针对与超大规模集成(ULSI)电路器件关联的高密度、高性能的日益增长的需求已经要求特定的设计特征，例如收缩的栅极长度、高可靠性和增加的生产量。设计特征的持续减小已经对常规制造技术的限制提出挑战。
例如，当常规的平面金属氧化物半导体场效应晶体管(MOSFET)的栅极长度按比例缩小到100nm以下时，与短沟道效应关联的问题(例如，源区与漏区之间的过度泄漏)变得日益难以克服。此外，迁移率降低和大量工艺问题也导致难以将常规的MOSFET按比例缩小为包括日益减小的器件特征。因此正在开发新的器件结构来提高FET性能并允许进一步的器件按比例缩小。
双栅极MOSFET表示这样一种结构：该结构已被认为是接替现有的平面MOSFET的候选。在双栅极MOSFET中，可使用两个栅极控制短沟道效应。FinFET是呈现出良好的短沟道行为的双栅极结构，其包括在垂直鳍中形成的沟道。FinFET结构可使用与用于常规平面MOSFET的布局和工艺技术类似的布局和工艺技术制造。
发明内容
在一方面，一种形成finFET晶体管器件的方法包括：在衬底之上形成结晶的(crystalline)压缩应变硅锗(cSiGe)层；掩蔽所述cSiGe层的第一区域，以暴露所述cSiGe层的第二区域；对所述cSiGe层的暴露的第二区域执行注入处理，以使其底部非晶化并将所述第二区域中的所述cSiGe层转变为弛豫SiGe(rSiGe)层；执行退火处理，以使所述rSiGe层再结晶；在所述rSiGe层上外延生长拉伸应变硅层；以及在所述拉伸应变硅层中和所述cSiGe层的所述第一区域中图案化鳍结构。
在另一方面，一种形成finFET晶体管器件的方法包括：减薄在掩埋氧化物(BOX)层之上形成的绝缘体上硅(SOI)层；在减薄的SOI层上外延生长结晶的压缩应变硅锗(cSiGe)层；执行热处理，以将锗从所述cSiGe层驱入所述减薄的SOI层中；掩蔽所述cSiGe层的第一区域，以暴露所述cSiGe层的第二区域；对所述cSiGe层的暴露的第二区域执行注入处理，以使其底部非晶化并将所述第二区域中的所述cSiGe层转变为弛豫SiGe(rSiGe)层；执行退火处理，以使所述rSiGe层再结晶；在所述rSiGe层上外延生长拉伸应变硅层；以及在所述拉伸应变硅层中和所述cSiGe层的所述第一区域中图案化鳍结构。
在又一方面，一种finFET晶体管器件包括：衬底；在所述衬底之上形成的第一多个鳍结构，所述第一多个鳍结构包括压缩应变硅锗SiGe材料；以及在所述衬底之上形成的第二多个鳍结构，所述第二多个鳍结构包括拉伸应变硅材料。
附图说明
参考示例性附图，其中在多个图中，相同的要素由相同的参考标号表示：
图1到15、17和18是根据示例性实施例的形成finFET晶体管器件的方法的示例性实施例的一系列截面图，图16是俯视图，其中；
图1示例出包括在掩埋氧化物(BOX)层上形成的减薄的绝缘体上硅层的起始半导体结构；
图2示例出在图1的结构上形成外延生长的结晶的SiGe层；
图3示例出将锗从SiGe层驱入SOI层的硅中的热处理；
图4示例出从图3中的结构去除氧化物层；
图5示例出对图4中的结构的光刻图案化以暴露器件的“n”区域且同时保护器件的“p”区域；
图6示例出在“n”区域中的压缩应变SiGe层的暴露部分中注入使SiGe层的底部非晶化的注入物类(species)的注入处理；
图7示例出遮蔽掩膜的抗蚀层部分的去除以及使“n”区域中的弛豫SiGe层完全结晶的再结晶退火；
图8示例出结晶的弛豫SiGe层的开槽以准备用作籽晶层(seedlayer)来执行进一步的外延生长；
图9示例出在“n”区域中形成拉伸应变硅层的外延硅生长处理；
图10示例出“p”区域之上的剩余硬掩膜层的去除；
图11示例出从图10的结构图案化出一组压缩应变SiGe鳍和一组拉伸应变Si鳍；
图12示例出包括虚栅极氧化物层和位于虚栅极氧化物层之上的虚非晶或多晶硅栅极层的虚栅极叠层的形成；
图13是虚栅极层从图12的结构中的去除；
图14示例出遮蔽“p”区域且暴露“n”区域的一部分以从“n”区域的暴露部分中去除虚栅极氧化物层的掩蔽；
图15示例出掩膜的去除；
图16是示例出去除弛豫SiGe层的位于拉伸应变SiNFET鳍下方的部分的蚀刻处理的俯视图；
图17是沿着图16的箭头的截面图；以及
图18示例出剩余的虚栅极氧化物层从“p”区域的去除，以及最终的高k层和栅极叠层的形成。
具体实施方式
对于平面FET和finFET器件，晶体管增益与晶体管沟道中多数载流子的迁移率(μ)成比例。载流能力以及因此导致的MOS晶体管的性能与沟道中多数载流子的迁移率成比例。作为P沟道场效应晶体管(PFET)中多数载流子的空穴的迁移率和作为N沟道场效应晶体管(NFET)中多数载流子的电子的迁移率可通过向沟道施加适当的应力来增大。现有的应力工程方法通过在不增加器件尺寸和器件电容的情况下增大器件驱动电流，极大增强了电路性能。例如，被施加于平面NFET晶体管的拉伸应力衬里(liner)在沟道中诱导纵向应力并增大电子迁移率，而被施加于平面PFET晶体管的压缩应力衬里在沟道中诱导压缩应力并增大空穴迁移率。
诸如finFET(或三栅极)3D晶体管结构的下一代CMOS技术继续依赖于增大的沟道迁移率来提高器件性能。因此，本文中的实施例提供一种形成具有增大的沟道迁移率的finFET晶体管器件的新集成方法。在一个示例性实施例中，集成方法以及所形成的器件提供包含finFET或三栅极结构的拉伸应变硅(Si)NFET和压缩应变沟道硅锗(SiGe)PFET。
现在一般地参考图1到19，其中示出根据示例性实施例的形成finFET晶体管器件的方法的一系列截面图以及俯视图(图16)。如图1所示，起始半导体结构100包括在掩埋绝缘体层(或更具体地，掩埋氧化物(BOX)层)104上形成的绝缘体上半导体层(或更具体地，绝缘体上硅(SOI)层)102。尽管图1未具体示出，但是本领域的技术人员将理解，BOX层形成在体半导体衬底上，所述体半导体衬底例如为硅、锗、硅锗合金、硅碳合金、硅锗碳合金、砷化镓、砷化铟、磷化铟、III-V化合物半导体材料、II-VI化合物半导体材料、有机半导体材料以及其它化合物半导体材料。
图1所示的SOI层102被用作用于后续外延SiGe生长处理的引晶层(seedinglayer)。因此，最初通过将SOI层102向下减薄到适当的厚度，例如约10纳米(nm)或更小的厚度，更具体地约5nm或更小的厚度，来针对此引晶制备SOI层102。图2示例出具有约35nm或更大的厚度的外延生长的结晶的SiGe层106的形成。SiGe层106的厚度取决于Ge浓度。例如，如果Ge浓度为20-25％，则SiGe层厚度小于50nm。Ge浓度越低，SiGe层就可生长得越厚，反之亦然。然后，如图3所示，执行热氧化或热扩散处理以将锗从SiGe层106驱入SOI籽晶层102的硅中。结果，SiGe层106有效地延伸到BOX层104的顶部，并且可形成位于SiGe层106层顶部的氧化物层107。然而，之后可通过诸如稀氟化氢(DHF)和水蚀刻之类的适当处理去除氧化物层107，如图4所示。位于BOX层104顶部的SiGe层106在处理中的此时完全发生(压缩)应变，因此在下文中被称为压缩SiGe(cSiGe)层106。
现在参考图5，利用遮蔽掩膜108对所形成的结构进行光刻图案化，所述遮蔽掩膜108可包括氮化物(例如，SiN)或氧化物硬掩膜层110和光致抗蚀剂层112。掩膜108以暴露器件的“n”区域(即，将形成NFET器件的区域)且同时保护器件的“p”区域(即，将形成PFET器件的区域)的方式进行图案化。然后如图6所示，“n”区域中cSiGe层106的暴露部被注入使“n”区域中cSiGe层106的底部114非晶化的注入物类(如箭头所示)。底部114的该非晶化具有使“n”区域中的cSiGe层106弛豫的效果；因此，cSiGe层106的现在弛豫的部分在下文中在图中被标记为弛豫SiGe(rSiGe)层106’。
图6中由箭头表示的注入物类可以是任何适当的物类，例如导致下部114被损害或非晶化的Si、Ge或其它中性注入物。然而，应注意到，注入能量和其它条件应被选择为使rSiGe层106’的上部保持在结晶状态，因为该上部充当用于整个层的后续再结晶的籽晶层。例如，在使用Si作为注入物类的情况下，可使用约10-30KeV的范围内的注入能量，其中注入剂量约为1x1014原子/cm2。
在非晶化注入物之后，在使“n”区域中的弛豫(rSiGe)层106’完全结晶的再结晶退火之前，去除遮蔽掩膜108的抗蚀剂层部分112，如图7所示。在此，使用粗虚线区分rSiGe层106’和“p”区域中的压缩(cSiGe)层106。再结晶退火例如可在N2氛围中，在从约400到1050℃范围内的温度下进行，持续时长从数秒到数小时。
现在参考图8，结晶的rSiGe层106’然后被开槽以准备用作进一步外延生长的籽晶层。开槽例如可通过反应离子蚀刻(RIE)执行，直到rSiGe层106’的剩余厚度为约10纳米或更小的量级，更具体地约5nm或更小。在执行本领域公知的一种或多种清洗处理(例如，标准清洗(SC1)、原位HC1等)之后，执行外延硅生长处理以在“n”区域中形成拉伸应变硅层116，如图9所示。
一旦形成拉伸应变硅层116，便去除“p”区域之上的剩余掩膜层110以准备鳍形成，如图10所示。鳍的图案化和形成在图11中示出，该图示例出一组压缩应变SiGe鳍118和一组拉伸应变Si鳍120。之后，根据FET器件技术执行额外的处理，例如包括：在替代栅极FET器件的情况下的虚栅极叠层形成(例如，栅极氧化物沉积、非晶或多晶硅沉积、硬掩膜沉积、光刻和栅极图案化)、间隔物(spacer)形成(例如，硅氮化物、氧化物)、外延源/漏鳍合并、源/漏形成(注入/退火)、ILD形成、以及虚栅极去除。由于这些处理操作对于本领域的技术人员而言是公知的，因此在此省略其细节。
为了连续性和完整性，现在可以参考图12的截面图，该图示例出在上述虚栅极叠层形成、间隔物形成、鳍合并以及源/漏形成处理之后，虚栅极叠层去除之前的图11的图案化鳍结构。更具体地说，图12示例出这样的虚栅极叠层结构的形成：该结构包括位于BOX层104之上的虚栅极氧化物层122、压缩应变SiGe鳍118、拉伸应变Si鳍120，以及位于虚栅极氧化物层122之上的虚非晶或多晶硅栅极层124。
然后，如图13所示，去除虚栅极层。在图14中，使用图案化的掩膜126(例如，光致抗蚀剂)遮蔽“p”区域并暴露“n”区域的部分，以从“n”区域的暴露部分去除虚栅极氧化物层122。虚栅极氧化物层122的蚀刻可以是缓冲氧化物蚀刻，也被称为缓冲HF或BHF，相对于更浓缩的HF蚀刻而言，该蚀刻提供更可控的蚀刻速率。
一旦将虚栅极氧化物层122从“n”区域的暴露部分去除，便可去除掩膜126，如图15所示，然后采用另一蚀刻处理去除rSiGe层106’的位于拉伸应变SiNFET鳍120下方的部分。例如，可通过HCl蚀刻来实现。此方面的示例性俯视图在图16中示出，另外还有沿图16的箭头截取的图17的截面图。在图16中，俯视图(除了压缩应变SiGe鳍118和拉伸应变Si鳍120之外)还示例出外延合并的源/漏区124和虚栅极间隔物126。在图17中，截面图示出已经从对应于栅极位置的该区域中的拉伸应变SiNFET鳍120下方去除的rSiGe层106’。
一旦去除rSiGe层106’，便可从“p”区域去除剩余的虚栅极氧化物层122以准备形成最终的高k层和栅极叠层，如图18所示。如图所示，高k层128在“n”区域和“p”区域之上形成。高k电介质材料的具体实例包括但不限于：HfO2、ZrO2、La2O3、Al2O3、TiO2、SrTiO3、LaAlO3、Y2O3、HfOxNy、ZrOxNy、La2OxNy、Al2OxNy、TiOxNy、SrTiOxNy、LaAlOxNy、Y2OxNy，它们的硅酸盐以及它们的合金。x的每个值独立地从0.5到3，y的每个值独立地从0到2。高k电介质层118的厚度可以从约1nm到约10nm，更具体地从约1.5nm到约3nm。
将注意到，高k层128可保形地附着到拉伸应变SiNFET鳍120的下面。在这种情况下，NFET器件可被视为具有“全环栅极”结构(即，栅极环绕鳍结构的顶面、底面和侧面)，而PFET器件可被视为具有“三栅极”结构(即，栅极环绕鳍结构的顶面和侧面)。然后在结构之上形成一个或多个功函数金属层130，接着形成一个或多个栅极金属层132。一个或多个栅极金属层132可包括例如润湿氮化钛沉积层，以及铝、掺钛铝、钨或铜中的一种或多种。
从这点，本领域中公知的常规处理可继续，所述常规处理包括例如对栅极金属层132的化学机械抛光(CMP)、栅极、源极和漏极端子的硅化物接触形成、上层布线形成等。
因此将理解，本文中描述的实施例使用新颖的工艺集成体系提供了这样的finFET结构：该结构具有用于NFET器件的拉伸应变Si沟道和用于PFET器件的压缩应变SiGe沟道，所述工艺集成体系通过使用注入和再结晶技术将压缩SiGe转变为弛豫SiGe。这转而提供了如下优点：即，由拉伸应变引起的NFET器件的优越电子迁移率，以及通过使用压缩SiGe沟道材料实现的PFET器件的优越空穴迁移率。
尽管已经参考一个或多个优选实施例描述了本发明，但是本领域的技术人员将理解，在不偏离本发明范围的情况下，可以做出多种更改，并且等同物可代替其要素。此外，在不偏离本发明的实质范围的情况下，可以做出许多修改以使具体的情况或材料适应本发明的教导。因此，本发明并非旨在限于作为被预期用于执行本发明的最佳模式而公开的特定实施例，而是包括落在所附权利要求的范围内的所有实施例。

Claims (20)

1.一种形成finFET晶体管器件的方法，所述方法包括：
在衬底之上形成结晶的压缩应变硅锗(cSiGe)层；
掩蔽所述cSiGe层的第一区域，以暴露所述cSiGe层的第二区域；
对所述cSiGe层的暴露的第二区域执行注入处理，以使其底部非晶化并将所述第二区域中的所述cSiGe层转变为弛豫SiGe(rSiGe)层；
执行退火处理，以使所述rSiGe层再结晶；
在所述rSiGe层上外延生长拉伸应变硅层；以及
在所述拉伸应变硅层中和所述cSiGe层的所述第一区域中图案化鳍结构。
2.根据权利要求1所述的方法，进一步包括执行所述注入处理，以使得被转变为所述rSiGe层的所述cSiGe层的顶部保持在结晶状态。
3.根据权利要求2所述的方法，其中，所述注入处理包括选自硅和锗的掺杂剂材料。
4.根据权利要求2所述的方法，其中，所述注入处理在约10-30KeV范围内的注入能量下，以约1x1014原子/cm2的注入剂量使用硅作为注入物类。
5.根据权利要求2所述的方法，进一步包括在所述rSiGe层上外延生长所述拉伸应变硅层之前，对所述再结晶的rSiGe层进行开槽。
6.根据权利要求1所述的方法，进一步包括去除所述rSiGe层的位于由所述拉伸应变硅层形成的图案化鳍结构下方的部分。
7.一种形成finFET晶体管器件的方法，所述方法包括：
减薄在掩埋氧化物(BOX)层之上形成的绝缘体上硅(SOI)层；
在减薄的SOI层上外延生长结晶的压缩应变硅锗(cSiGe)层；
执行热处理，以将锗从所述cSiGe层驱入所述减薄的SOI层中；
掩蔽所述cSiGe层的第一区域，以暴露所述cSiGe层的第二区域；
对所述cSiGe层的暴露的第二区域执行注入处理，以使其底部非晶化并将所述第二区域中的所述cSiGe层转变为弛豫SiGe(rSiGe)层；
执行退火处理，以使所述rSiGe层再结晶；
在所述rSiGe层上外延生长拉伸应变硅层；以及
在所述拉伸应变硅层中和所述cSiGe层的所述第一区域中图案化鳍结构。
8.根据权利要求7所述的方法，其中，在所述SOI层上外延生长所述结晶的cSiGe层之前，所述SOI层被减薄为约10纳米(nm)或更小的厚度。
9.根据权利要求7所述的方法，进一步包括去除由所述热处理导致的所述cSiGe层上的氧化物层。
10.根据权利要求7所述的方法，进一步包括执行所述注入处理，以使得被转变为所述rSiGe层的所述cSiGe层的顶部保持在结晶状态。
11.根据权利要求10所述的方法，其中，所述注入处理包括选自硅和锗的掺杂剂材料。
12.根据权利要求10所述的方法，其中，所述注入处理在约10-30KeV范围内的注入能量下，以约1x1014原子/cm2的注入剂量使用硅作为注入物类。
13.根据权利要求10所述的方法，进一步包括在所述rSiGe层上外延生长所述拉伸应变硅层之前，对所述再结晶的rSiGe层进行开槽。
14.根据权利要求10所述的方法，其中，所述再结晶的rSiGe层凹陷约10纳米(nm)或更小的厚度。
15.根据权利要求7所述的方法，进一步包括在图案化的鳍结构之上形成虚栅极叠层结构，所述虚栅极叠层结构包括非晶或多晶硅栅极层中的一者以及虚栅极氧化物层。
16.根据权利要求15所述的方法，进一步包括去除所述虚栅极叠层结构的与由所述拉伸应变硅层形成的所述图案化鳍结构的位置对应的部分。
17.根据权利要求16所述的方法，进一步包括去除所述rSiGe层的位于由所述拉伸应变硅层形成的所述图案化鳍结构下方的部分。
18.根据权利要求17所述的方法，进一步包括去除剩余的虚栅极叠层结构，并且形成高k层和栅极叠层。
19.一种finFET晶体管器件，包括：
衬底；
在所述衬底之上形成的第一多个鳍结构，所述第一多个鳍结构包括压缩应变硅锗SiGe材料；以及
在所述衬底之上形成的第二多个鳍结构，所述第二多个鳍结构包括拉伸应变硅材料。
20.根据权利要求19所述的器件，其中，所述第二多个鳍结构包括具有全环栅极结构的NFET器件，以使得NFET栅极环绕所述第二多个鳍结构的顶面、底面和侧面，并且所述第一多个鳍结构包括具有三栅极结构的PFET器件，以使得PFET栅极环绕所述第一多个鳍结构的顶面和侧面。
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