200921115 九、發明說明 【發明所屬之技術領域】 本發明係關於一種用以檢測電源電壓之 壓降低檢測電路。 【先前技術】 一般而言，半導體裝置係裝載有用以檢 降低的電源電壓降低檢測電路。當該電源電 路檢測出電源電壓未達最低動作電壓時，半 由截斷（shutdown)進行錯誤動作的電路或 檢測電路以外的所有電路，而使錯誤動作消 在此說明半導體裝置的最低動作電壓。 第5圖係顯示半導體裝置之要素電路之 第5圖的電路係藉由NM0S電晶體31至 NMOS疊接式（cascode type)的電流鏡電 最低動作電壓係NM0S電晶體3 1之臨限値 及過驅動電壓的合計、與NMOS電晶體32 的絕對値及過驅動電壓的合計的和電壓。 第6圖係顯示半導體裝置之其他要素電 圖。第6圖的電路係藉由PM0S電晶體413 PMOS疊接式的電流鏡電路。該電路的最/ PMOS電晶體4 1之臨限値電壓的絕對値及 合計、與PMOS電晶體42之臨限値電壓的 動電壓的合計的和電壓。 降低的電源電 測電源電壓之 壓降低檢測電 導體裝置係藉 電源電壓降低 例的電路圖。 3 4所構成的 洛。該電路的 電壓的絕對値 之臨限値電壓 路之例的電路 i 4 4所構成的 氏動作電壓係 過驅動電壓的 絕對値及過驅 -4- 200921115 第7圖係顯示半導體裝置之其他要素電路之例的電路 圖。第7圖的電路係藉由PMOS電晶體51、PMOS電晶體 55至56、NMOS電晶體52、NMOS電晶體54及電阻53 所構成的定電流電路。使該電路進行動作的訊號係輸入至 PMOS電晶體55的閘極，當PMOS電晶體55導通（ON ) 時，該電路即進行動作。該電路的最低動作電壓係NMOS 電晶體52之臨限値電壓的絕對値及過驅動電壓的合計、 與NMOS電晶體54之臨限値電壓的絕對値及過驅動電壓 的合計的和電壓、以及PMOS電晶體55之臨限値電壓的 絕對値及過驅動電壓的合計、與PMOS電晶體56之臨限 値電壓的絕對値及過驅動電壓的合計的和電壓中較高者的 電壓。 半導體裝置一般而言係大部分使用上述要素電路，因 此半導體裝置的最低動作電壓係半導體裝置內和電壓爲最 高的2個NMOS電晶體中之一個NMOS電晶體之臨限値 電壓的絕對値及過驅動電壓的合計、與另一 NMOS電晶體 之臨限値電壓的絕對値及過驅動電壓的合計的和電壓、以 及半導體裝置內和電壓爲最高的2個PMOS電晶體中之一 個PMOS電晶體之臨限値電壓的絕對値及過驅動電壓的合 計、與另一 PMOS電晶體之臨限値電壓的絕對値及過驅動 電壓的合計的和電壓中較高者的電壓。 就習知之電源電壓降低檢測電路加以說明。第8圖係 顯示習知之電源電壓降低檢測電路之示意圖。 習知之電源電壓降低檢測電路係具備有：用以輸出基 -5- 200921115 準電壓的基準電壓電路72 ;以電阻75與電阻76將電源 71的電源電壓分壓而將分壓電壓予以輸出的分壓電路73 ;將基準電壓與分壓電壓作比較而檢測電源電壓之降低的 差動放大電路74 ;以及將差動放大電路74的輸出端子上 拉（pull up )的上拉電阻77 (例如參照專利文獻1 )。 (專利文獻1 )日本特開200 5 -27 8 05 6號公報（第4 圖） 【發明內容】 (發明所欲解決之課題） 但是，在藉由專利文獻1所揭示的電路中，係必須設 置基準電壓電路、分壓電路及差動放大電路，而使電路規 模變大。因而，由此使消耗電流變多。 本發明係鑑於上述課題而硏創者，提供一種電路規模 較小的電源電壓降低檢測電路。 (解決課題之手段） 本發明爲了解決上述課題，提供一種電源電壓降低檢 測電路，係用以檢測電源電壓之降低的電源電壓降低檢測 電路，其特徵爲具備有：第一電晶體，爲第一導電型，根 據前述電源電壓，輸出根據由前述電源電壓減算臨限値電 壓的絕對値及過驅動電壓而得之電壓的源極電壓；第二電 晶體，爲前述第一導電型，根據前述第一電晶體的源極電 壓進行導通/關斷；第三電晶體，爲第二導電型，根據接 -6- 200921115 地電壓，輸出根據在前述接地電壓加算臨限値電壓的絕對 値及過驅動電壓而得之電壓的源極電壓；第四電晶體，爲 前述第二導電型，根據前述第三電晶體的源極電壓進行導 通/關斷；第一定電流電路，對前述第一電晶體供給電流 ;第二定電流電路，對前述第二電晶體及前述第三電晶體 供給電流；以及第三定電流電路，對前述第四電晶體供給 電流。 (發明之效果） 本發明之電源電壓降低檢測電路係不需要設置基準電 壓電路、分壓電路及差動放大電路，電路規模變得較小。 因而，由此使消耗電流變少。 【實施方式】 以下參照圖示，說明本發明之電源電壓降低檢測電路 之實施形態。 第1圖係顯示本發明之電源電壓降低檢測電路的電路 圖。 本發明之電源電壓降低檢測電路係具備有：電源端子 1、接地端子2及輸出端子3。此外，電源電壓降低檢測 電路係具備有定電流電路4至6。此外，電源電壓降低檢 測電路係具備有：Ν Μ Ο S電晶體1 2、Ν Μ Ο S電晶體17、 PMOS電晶體15及PMOS電晶體19。 定電流電路4被設在NMO S電晶體1 2的源極與接地 200921115 端子2之間。定電流電路5被設在電源端子1與PMOS電 晶體1 5的源極之間。定電流電路6被設在輸出端子3與 接地端子2之間。NMOS電晶體1 2的閘極及汲極係連接 於電源端子1，背閘極（back-gate )係連接於接地端子2 。NMOS電晶體17的閘極係連接於NMOS電晶體12的源 極，源極及背閘極係連接於接地端子2，汲極係連接於 PMOS電晶體15的汲極。PMOS電晶體15的閘極係連接 於接地端子2，背閘極係連接於電源端子1。PMOS電晶 體1 9的閘極係連接於PMOS電晶體1 5的源極，源極及背 閘極係連接於電源端子1，汲極係連接於輸出端子3。 關於NMOS電晶體12及NMOS電晶體17，NMOS電 晶體1 2之臨限値電壓的絕對値及過驅動電壓的合計、與 NMO S電晶體1 7之臨限値電壓的絕對値及過驅動電壓的 合計的和電壓係高於半導體裝置內之預定2個NMO S電晶 體中之一個NMOS電晶體之臨限値電壓的絕對値及過驅動 電壓的合計與另一 NMOS電晶體之臨限値電壓的絕對値及 過驅動電壓的合計的和電壓。關於PMOS電晶體15及 PMOS電晶體19亦爲相同。 此外，定電流電路4係對NMOS電晶體12供給電流 。定電流電路5係對NMOS電晶體17及PMOS電晶體15 供給電流。定電流電路6係對PMOS電晶體1 9供給電流 。NMOS電晶體12係根據電源電壓，輸出根據由電源電 壓減算臨限値電壓的絕對値及過驅動電壓而得之電壓的源 極電壓。根據該源極電壓，NMOS電晶體17進行導通（ 200921115 ON ) /關斷（OFF ) 。PMOS電晶體15係根據接地電壓 ，輸出根據在接地電壓加算臨限値電壓的絕對値及過驅動 電壓而得之電壓的源極電壓。根據該源極電壓，PMOS電 晶體19進行導通/關斷。 接著說明本發明之電源電壓降低檢測電路的動作。 在此，將NMOS電晶體之臨限値電壓的絕對値設爲 Vtn，將PMOS電晶體之臨限値電壓的絕對値設爲Vtp。 [Vtp> Vtn時（NMOS電晶體比PMOS電晶體更難以關斷 時）之電源電壓的降低檢測動作] 若電源電壓變低，NMOS電晶體12的閘極電壓即變 低，NMOS電晶體12呈關斷，NMOS電晶體17的閘極電 壓亦變低，NMOS電晶體17亦呈關斷。因此，PMOS電晶 體19的閘極電壓變高，PMOS電晶體19係呈關斷。若電 源電壓未達2Vtp，NMOS電晶體12及NMOS電晶體17 尙呈導通，但是藉由PMOS電晶體15，PMOS電晶體19 的閘極電壓未完全成爲低位準，PMOS電晶體1 9係呈關 斷。因此，若電源電壓未達2Vtp，亦即，若電源電壓成 爲未達半導體裝置之最低動作電壓，電源電壓降低檢測電 路係將低位準訊號作爲檢測訊號而由輸出端子3輸出至外 部。 [Vtp < Vtn時（PMOS電晶體比NMOS電晶體更難以關斷 時）之電源電壓的降低檢測動作] -9- 200921115 當電源電壓變低，電源電壓未達2Vtn 晶體1 2尙呈導通，但是藉由定電流電路4， 17的閘極電壓未完全成爲高位準，NMOS電 關斷，PMOS電晶體19的閘極電壓成爲高位 晶體1 9亦呈關斷。因此，若電源電壓未達 電源電壓未達半導體裝置的最低動作電壓， 檢測電路係將低位準訊號作爲檢測訊號而由 出至外部。 [Vtp > Vtn時（NMOS電晶體比PMOS電晶 時）之電源電壓的降低檢測解除動作] 電源電壓比2Vtp及2Vtn之雙方更低， 電壓變高，Ν Μ Ο S電晶體1 2的閘極電壓會 電晶體12進行導通，NMOS電晶體17的閘 ，NMOS電晶體17亦呈導通。因此，PMOS 閘極電壓變低，PMOS電晶體1 9亦呈導通 爲2Vtn以上時，NMOS電晶體1 2及NMOS 呈導通，但是藉由PMOS電晶體15，PMOS 閘極電壓未完全成爲低位準，PMOS電晶體 。當電源電壓爲2Vtp以上時，NMOS電晶體 電晶體17係已呈導通，PMOS電晶體19的 低位準，PMOS電晶體19亦呈導通。因此 爲2 Vtp以上時，亦即，電源電壓爲半導體 作電壓以上時，電源電壓降低檢測電路係將 時，NMOS電 Ν Μ Ο S電晶體 :晶體1 7係呈 準，PMOS電 2 V t η，亦良卩， 電源電壓降低 輸出端子3輸 體更容易導通 之後，若電源 變高，NMOS 極電壓亦變高 電晶體1 9的 。當電源電壓 電晶體1 7係 電晶體19的 1 9尙呈關斷 I 12 及 NMOS 閘極電壓成爲 ，當電源電壓 裝置之最低動 高位準訊號作 -10- 200921115 爲檢測訊號而由輸出端子3輸出至外部。 [Vtp< Vtn時（PMOS電晶體比NMOS電晶體更容易導通 時）之電源電壓的降低檢測解除動作] 電源電壓比2Vtp及2Vtn之雙方更低，之後，電源電 壓變高，當電源電壓爲2Vtn以上時，NMOS電晶體12及 NMOS電晶體17係導通，PMOS電晶體19的閘極電壓成 爲低位準，PMOS電晶體19亦導通。因此，當電源電壓 爲2Vtn以上時，亦即，電源電壓爲半導體裝置之最低動 作電壓以上時，電源電壓降低檢測電路係將高位準訊號作 爲檢測訊號而由輸出端子3輸出至外部。 接著說明本發明之電源電壓降低檢測電路的定電流電 路。第2圖係顯示本發明之電源電壓降低檢測電路之定電 流電路之一具體例的電路圖。 定電流電路4係藉由例如空乏型（depletion type) NMOS電晶體1 1予以實現。空乏型NMOS電晶體1 1的閘 極、源極及背閘極係連接於接地端子2，汲極係連接於 NMOS電晶體1 1的源極。空乏型NMOS電晶體1 1的汲極 係由NMOS電晶體12的源極抽出電流。 定電流電路5係藉由例如空乏型Ν Μ Ο S電晶體11及 PMOS電晶體13至14予以實現。PMOS電晶體13的閘極 及汲極係連接於NMO S電晶體1 2的汲極，源極及背閘極 係連接於電源端子1。PMOS電晶體14的閘極係連接於 PMO S電晶體1 3的閘極，源極及背閘極係連接於電源端 -11 - 200921115 子1，汲極係連接於Ρ Μ 0 S電晶體1 5的源極。Ρ Μ ◦ S電晶 體1 4的汲極係將根據定電流電路4之電流的電流流至 PMOS電晶體15的源極。 定電流電路6係藉由例如空乏型NMO S電晶體1 1、 PMOS電晶體1 3至14、NMOS電晶體16及NMOS電晶體 1 8予以實現。NMOS電晶體1 6的閘極及汲極係連接於 PMOS電晶體1 5的汲極，源極係連接於NMOS電晶體1 7 的汲極，背閘極係連接於接地端子2。NMO S電晶體1 8的 閘極係連接於Ν Μ Ο S電晶體1 6的閘極，源極及背閘極係 連接於接地端子2，汲極係連接於Ρ Μ Ο S電晶體1 9的汲 極。Ν Μ Ο S電晶體1 8的汲極係由Ρ Μ Ο S電晶體1 9的汲極 抽出根據定電流電路4之電流的電流。 如以上說明所示，本發明之電源電壓降低檢測電路並 不需要設置基準電壓電路、分壓電路及差動放大電路，電 路規模變得較小。因此，消耗電流亦變得較少。 此外，爲了補償基準電壓的偏差，必須進行分壓電路 的電阻調製（trimming )，但是調製變得不需要。因此， 由於減少製造步驟，因此製造成本變低。 此外，即使PMOS電晶體與NMOS電晶體的動作關係 爲任一者，當電源電壓成爲未達半導體裝置的最低動作電 壓時，電源電壓降低檢測電路係將低位準訊號作爲檢測訊 號而由輸出端子3輸出至外部，因此半導體裝置並不會進 行錯誤動作。 其中，亦可將第1圖及第2圖中的NMOS電晶體變更 -12- 200921115 爲PMOS電晶體，將PMOS電晶體變更爲NMOS電晶體。 接著參照圖示，說明本發明之其他實施例之電源電壓 降低檢測電路。 第3圖係顯示本發明之其他實施例之電源電壓降低檢 測電路的電路圖。在與第1圖的電源電壓降低檢測電路的 差異中，定電流電路4係被變更爲定電流電路7，定電流 電路5係被變更爲定電流電路8，定電流電路6係被變更 爲定電流電路9。 第4圖係顯示本發明之其他實施例之電源電壓降低檢 測電路之定電流電路之一具體例的電路圖。在與第2圖之 電源電壓降低檢測電路的差異中，NMO S電晶體1 2係被 變更爲PMOS電晶體22，NMOS電晶體17係被變更爲 PMOS電晶體27，PMOS電晶體15係被變更爲NMOS電 晶體25，PMOS電晶體19係被變更爲NMOS電晶體29。 在此，空乏型NMOS電晶體1 1係被變更爲空乏型NMOS 電晶體21，PMOS電晶體13係被變更爲NMOS電晶體23 ，PMOS電晶體14係被變更爲NMOS電晶體24，NMOS 電晶體16係被變更爲PMOS電晶體26，NMOS電晶體18 係被變更爲PMOS電晶體28。 可知即使如第3圖及第4圖所示構成電源電壓降低檢 測電路，亦可獲得與第1圖及第2圖所示之電源電壓降低 檢測電路相同的效果。 【圖式簡單說明】 -13- 200921115 第1圖係顯示本發明之電源電壓降低檢測電路的電路 圖。 第2圖係顯示本發明之電源電壓降低檢測電路之定電 流電路之一具體例的電路圖。 第3圖係顯示本發明之其他實施例之電源電壓降低檢 測電路的電路圖。 第4圖係顯示本發明之其他實施例之電源電壓降低檢 測電路之定電流電路之一具體例的電路圖。 第5圖係顯示半導體裝置之要素電路之例的電路圖。 第6圖係顯示半導體裝置之要素電路之其他例的電路 圖。 第7圖係顯示半導體裝置之要素電路之其他例的電路 圖。 第8圖係顯示習知之電源電壓降低檢測電路的電路圖 【主要元件符號說明】 1 :電源端子 2 :接地端子 3 :輸出端子 4至6 :定電流電路 12、 16 至 18、 23 至 25、 29、 31 至 34、 52、 54: NMOS電晶體 ll、21:空乏型NMOS電晶體 -14 - 200921115 13 至 15、 19、 22、 26 至 28、 41 至 44、 51、 55 至 56 :Ρ Μ Ο S電晶體 53、 75、 76:電阻 7 1 :電源 72:基準電壓電路 73 :分壓電路 7 4 :差動放大電路 77 :上拉電阻 -15-BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage drop detecting circuit for detecting a power supply voltage. [Prior Art] In general, a semiconductor device is loaded with a power supply voltage drop detecting circuit which is useful for detection. When the power supply circuit detects that the power supply voltage has not reached the minimum operating voltage, half of the circuit that is erroneously operated by the shutdown or all circuits other than the detection circuit causes the erroneous operation to eliminate the minimum operating voltage of the semiconductor device. Fig. 5 is a diagram showing the circuit of Fig. 5 showing the element circuit of the semiconductor device by the NM0S transistor 31 to the NMOS cascode type current mirror electric minimum operating voltage system NM0S transistor 3 1 and The sum of the overdrive voltages and the sum of the absolute 値 and overdrive voltages of the NMOS transistor 32. Fig. 6 is a view showing other elements of the semiconductor device. The circuit of Fig. 6 is a PMOS-stacked current mirror circuit by a PMOS transistor 413. The sum of the absolute 値 voltage of the most PMOS transistor 4 1 of the circuit and the sum of the total voltages of the PMOS transistor 42 and the threshold voltage of the PMOS transistor 42. The reduced power supply voltage is measured by the voltage drop detection power conductor device by the power supply voltage reduction example circuit diagram. 3 4 constitutes Luo. The absolute voltage of the circuit is limited to the absolute voltage of the circuit. The circuit i 4 4 is an example of the absolute operating voltage of the overdrive voltage and the overdrive -4-200921115. Figure 7 shows the other elements of the semiconductor device. A circuit diagram of an example of a circuit. The circuit of Fig. 7 is a constant current circuit composed of a PMOS transistor 51, PMOS transistors 55 to 56, an NMOS transistor 52, an NMOS transistor 54, and a resistor 53. The signal for operating the circuit is input to the gate of the PMOS transistor 55, and the circuit operates when the PMOS transistor 55 is turned "ON". The minimum operating voltage of the circuit is the sum of the absolute 値 and overdrive voltages of the threshold voltage of the NMOS transistor 52, the sum of the absolute 値 and the overdrive voltage of the threshold voltage of the NMOS transistor 54, and The PMOS transistor 55 has the absolute 値 and the overdrive voltage of the threshold voltage, and the voltage of the sum of the sum of the absolute 値 and the overdrive voltage of the PMOS transistor 56. In general, semiconductor devices generally use the above-described element circuits. Therefore, the minimum operating voltage of the semiconductor device is the absolute threshold of the threshold voltage of one of the two NMOS transistors in the semiconductor device and the highest voltage. The sum of the driving voltages, the sum of the absolute 値 and the overdrive voltages of the threshold voltage of the other NMOS transistor, and the PMOS transistor of the two PMOS transistors having the highest voltage and the highest voltage in the semiconductor device. The sum of the absolute 値 and overdrive voltages of the threshold voltage, and the higher of the sum of the absolute 値 and overdrive voltages of the threshold voltage of the other PMOS transistor. A description will be given of a conventional power supply voltage drop detecting circuit. Fig. 8 is a view showing a conventional power supply voltage drop detecting circuit. The conventional power supply voltage drop detecting circuit is provided with a reference voltage circuit 72 for outputting a base voltage of -5 to 200921115, and dividing the power supply voltage of the power source 71 by a resistor 75 and a resistor 76 to output a divided voltage. a voltage circuit 73; a differential amplifier circuit 74 that detects a decrease in the power source voltage by comparing the reference voltage with the divided voltage; and a pull-up resistor 77 that pulls up the output terminal of the differential amplifier circuit 74 (for example Refer to Patent Document 1). (Patent Document 1) Japanese Patent Laid-Open Publication No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. The reference voltage circuit, the voltage dividing circuit, and the differential amplifying circuit are set to increase the circuit scale. Thus, the current consumption is thereby increased. The present invention has been made in view of the above problems, and provides a power supply voltage drop detecting circuit having a small circuit scale. Means for Solving the Problems In order to solve the above problems, the present invention provides a power supply voltage reduction detecting circuit for detecting a power supply voltage drop detecting circuit, which is characterized in that: a first transistor is provided The conductive type outputs a source voltage of a voltage obtained by subtracting an absolute 値 and an overdrive voltage of the threshold voltage from the power supply voltage according to the power supply voltage; and the second transistor is the first conductivity type, according to the foregoing The source voltage of a transistor is turned on/off; the third transistor is a second conductivity type, and according to the ground voltage of -6-200921115, the output is based on the absolute 値 and overdrive of the threshold voltage added to the ground voltage. a source voltage of a voltage obtained by the voltage; a fourth transistor being the second conductivity type, being turned on/off according to a source voltage of the third transistor; and a first constant current circuit for the first transistor Supplying a current; a second constant current circuit supplying current to said second transistor and said third transistor; and a third constant current circuit for said fourth The transistor supplies current. (Effect of the Invention) The power supply voltage drop detecting circuit of the present invention does not require a reference voltage circuit, a voltage dividing circuit, and a differential amplifying circuit, and the circuit scale becomes small. Thus, the current consumption is thereby reduced. [Embodiment] Hereinafter, an embodiment of a power supply voltage drop detecting circuit of the present invention will be described with reference to the drawings. Fig. 1 is a circuit diagram showing a power supply voltage drop detecting circuit of the present invention. The power supply voltage drop detecting circuit of the present invention includes a power supply terminal 1, a ground terminal 2, and an output terminal 3. Further, the power supply voltage drop detecting circuit is provided with constant current circuits 4 to 6. Further, the power supply voltage drop detecting circuit is provided with: Ν Μ S transistor 1, 2 Μ Ο S transistor 17, PMOS transistor 15 and PMOS transistor 19. The constant current circuit 4 is provided between the source of the NMO S transistor 12 and the ground 2, 200921115 terminal 2. The constant current circuit 5 is provided between the power supply terminal 1 and the source of the PMOS transistor 15. The constant current circuit 6 is provided between the output terminal 3 and the ground terminal 2. The gate and the drain of the NMOS transistor 12 are connected to the power supply terminal 1, and the back-gate is connected to the ground terminal 2. The gate of the NMOS transistor 17 is connected to the source of the NMOS transistor 12, the source and the back gate are connected to the ground terminal 2, and the drain is connected to the drain of the PMOS transistor 15. The gate of the PMOS transistor 15 is connected to the ground terminal 2, and the back gate is connected to the power supply terminal 1. The gate of the PMOS transistor 1 is connected to the source of the PMOS transistor 15, the source and the back gate are connected to the power supply terminal 1, and the drain is connected to the output terminal 3. Regarding the NMOS transistor 12 and the NMOS transistor 17, the total 値 and overdrive voltages of the threshold voltage of the NMOS transistor 12, and the absolute 値 and overdrive voltage of the threshold voltage of the NMO S transistor 17 The sum of the sum and voltage is higher than the sum of the absolute and overdrive voltages of the threshold voltage of one of the predetermined two NMO S transistors in the semiconductor device and the threshold voltage of the other NMOS transistor Absolutely 値 and the sum of the overdrive voltage and the voltage. The PMOS transistor 15 and the PMOS transistor 19 are also the same. Further, the constant current circuit 4 supplies a current to the NMOS transistor 12. The constant current circuit 5 supplies current to the NMOS transistor 17 and the PMOS transistor 15. The constant current circuit 6 supplies current to the PMOS transistor 19. The NMOS transistor 12 outputs a source voltage of a voltage obtained by subtracting the absolute 値 and overdrive voltage of the threshold voltage from the power source voltage in accordance with the power source voltage. According to the source voltage, the NMOS transistor 17 is turned on (200921115 ON) / turned off (OFF). The PMOS transistor 15 outputs a source voltage of a voltage obtained by adding the absolute 値 and overdrive voltage of the threshold voltage to the ground voltage in accordance with the ground voltage. According to the source voltage, the PMOS transistor 19 is turned on/off. Next, the operation of the power supply voltage decrease detecting circuit of the present invention will be described. Here, the absolute value of the threshold voltage of the NMOS transistor is Vtn, and the absolute value of the threshold voltage of the PMOS transistor is Vtp. [Vtp> Vtn (when the NMOS transistor is more difficult to turn off than the PMOS transistor), the power supply voltage is lowered.] When the power supply voltage is low, the gate voltage of the NMOS transistor 12 becomes low, and the NMOS transistor 12 is When turned off, the gate voltage of the NMOS transistor 17 also becomes low, and the NMOS transistor 17 is also turned off. Therefore, the gate voltage of the PMOS transistor 19 becomes high, and the PMOS transistor 19 is turned off. If the power supply voltage is less than 2Vtp, the NMOS transistor 12 and the NMOS transistor 17 are turned on, but with the PMOS transistor 15, the gate voltage of the PMOS transistor 19 is not completely low, and the PMOS transistor is closed. Broken. Therefore, if the power supply voltage is less than 2Vtp, that is, if the power supply voltage becomes the lowest operating voltage of the semiconductor device, the power supply voltage lowering detection circuit outputs the low level signal as the detection signal and is output from the output terminal 3 to the outside. [Vtp < Vtn (when the PMOS transistor is more difficult to turn off than the NMOS transistor), the detection of the power supply voltage is reduced] -9- 200921115 When the power supply voltage becomes lower, the power supply voltage is less than 2Vtn, and the crystal is turned on. However, since the gate voltage of the constant current circuits 4, 17 is not completely high, the NMOS is turned off, and the gate voltage of the PMOS transistor 19 becomes high, and the crystal 19 is also turned off. Therefore, if the power supply voltage is less than the minimum operating voltage of the semiconductor device, the detection circuit sends the low level signal as a detection signal to the outside. [Vtp > Vtn (when NMOS transistor is higher than PMOS transistor), the power supply voltage is reduced.] The power supply voltage is lower than both of 2Vtp and 2Vtn, and the voltage becomes high. Ν Μ Ο S transistor 1 2 The pole voltage causes the transistor 12 to conduct, the gate of the NMOS transistor 17, and the NMOS transistor 17 also conducts. Therefore, when the PMOS gate voltage is low and the PMOS transistor 19 is turned on to be 2Vtn or more, the NMOS transistor 12 and the NMOS are turned on, but with the PMOS transistor 15, the PMOS gate voltage is not completely low. PMOS transistor. When the power supply voltage is 2 Vtp or more, the NMOS transistor transistor 17 is turned on, the PMOS transistor 19 is low, and the PMOS transistor 19 is also turned on. Therefore, when the voltage is greater than or equal to 2 Vtp, that is, when the power supply voltage is greater than or equal to the semiconductor voltage, the power supply voltage drop detection circuit is applied, and the NMOS transistor Μ 电 S transistor: the crystal 1 7 system is accurate, and the PMOS battery is 2 V t η However, after the power supply voltage is lowered, the output terminal 3 is more easily turned on. If the power supply becomes higher, the NMOS voltage also becomes higher. When the voltage of the power supply voltage transistor 17 is 19, the turn-off I 12 and the NMOS gate voltage become, when the lowest dynamic high level signal of the power supply voltage device is -10-200921115 as the detection signal and the output terminal 3 Output to the outside. [Vtp<Vtn (When the PMOS transistor is easier to turn on than the NMOS transistor), the power supply voltage is reduced.] The power supply voltage is lower than both of 2Vtp and 2Vtn. After that, the power supply voltage becomes high. When the power supply voltage is 2Vtn In the above case, the NMOS transistor 12 and the NMOS transistor 17 are turned on, the gate voltage of the PMOS transistor 19 is at a low level, and the PMOS transistor 19 is also turned on. Therefore, when the power supply voltage is 2 Vtn or more, that is, when the power supply voltage is equal to or higher than the minimum operating voltage of the semiconductor device, the power supply voltage drop detecting circuit outputs the high level signal as a detection signal and outputs it to the outside through the output terminal 3. Next, the constant current circuit of the power supply voltage decrease detecting circuit of the present invention will be described. Fig. 2 is a circuit diagram showing a specific example of a constant current circuit of the power supply voltage drop detecting circuit of the present invention. The constant current circuit 4 is realized by, for example, a depletion type NMOS transistor 11. The gate, the source and the back gate of the depletion NMOS transistor 1 are connected to the ground terminal 2, and the drain is connected to the source of the NMOS transistor 11. The drain of the depletion NMOS transistor 1 1 draws current from the source of the NMOS transistor 12. The constant current circuit 5 is realized by, for example, a depletion type 电 电 S transistor 11 and PMOS transistors 13 to 14. The gate and the drain of the PMOS transistor 13 are connected to the drain of the NMO S transistor 12, and the source and the back gate are connected to the power supply terminal 1. The gate of the PMOS transistor 14 is connected to the gate of the PMO S transistor 13, the source and the back gate are connected to the power terminal -11 - 200921115, the drain gate is connected to the Ρ Μ 0 S transistor 1 The source of 5. The drain of the 电 电 S electromorph 1 14 flows to the source of the PMOS transistor 15 in accordance with the current of the current of the constant current circuit 4. The constant current circuit 6 is realized by, for example, a depletion type NMO S transistor 11 , PMOS transistors 13 to 14, an NMOS transistor 16, and an NMOS transistor 18. The gate and the drain of the NMOS transistor 16 are connected to the drain of the PMOS transistor 15, the source is connected to the drain of the NMOS transistor 17, and the back gate is connected to the ground terminal 2. The gate of the NMO S transistor 18 is connected to the gate of the 电 Ο S transistor 16. The source and back gates are connected to the ground terminal 2, and the drain is connected to the Ρ 电 S transistor. Bungee jumping.汲 Μ Ο S The gate of the transistor 1 8 draws current from the drain of the constant current circuit 4 from the drain of the 电 Ο S transistor. As described above, the power supply voltage drop detecting circuit of the present invention does not require a reference voltage circuit, a voltage dividing circuit, and a differential amplifying circuit, and the circuit scale becomes small. Therefore, the current consumption also becomes less. Further, in order to compensate for variations in the reference voltage, it is necessary to perform resistance trimming of the voltage dividing circuit, but modulation becomes unnecessary. Therefore, since the manufacturing steps are reduced, the manufacturing cost becomes low. In addition, even if the operational relationship between the PMOS transistor and the NMOS transistor is any, when the power supply voltage becomes the lowest operating voltage of the semiconductor device, the power supply voltage reduction detecting circuit uses the low level signal as the detection signal and is output terminal 3 The output is external, so the semiconductor device does not perform an erroneous operation. However, the NMOS transistors in FIGS. 1 and 2 can be changed to PMOS transistors -12-200921115, and the PMOS transistors can be changed to NMOS transistors. Next, a power supply voltage drop detecting circuit according to another embodiment of the present invention will be described with reference to the drawings. Fig. 3 is a circuit diagram showing a power supply voltage drop detecting circuit of another embodiment of the present invention. In the difference from the power supply voltage decrease detecting circuit of Fig. 1, the constant current circuit 4 is changed to the constant current circuit 7, the constant current circuit 5 is changed to the constant current circuit 8, and the constant current circuit 6 is changed to Current circuit 9. Fig. 4 is a circuit diagram showing a specific example of a constant current circuit of a power supply voltage decrease detecting circuit of another embodiment of the present invention. In the difference from the power supply voltage drop detecting circuit of Fig. 2, the NMO S transistor 12 is changed to the PMOS transistor 22, the NMOS transistor 17 is changed to the PMOS transistor 27, and the PMOS transistor 15 is changed. The PMOS transistor 25 is changed to the NMOS transistor 29 by the NMOS transistor 25. Here, the depletion NMOS transistor 11 is changed to the depletion NMOS transistor 21, the PMOS transistor 13 is changed to the NMOS transistor 23, and the PMOS transistor 14 is changed to the NMOS transistor 24, and the NMOS transistor is used. The 16-series is changed to the PMOS transistor 26, and the NMOS transistor 18 is changed to the PMOS transistor 28. It is understood that even if the power supply voltage decrease detecting circuit is constructed as shown in Figs. 3 and 4, the same effects as those of the power supply voltage lowering detecting circuit shown in Figs. 1 and 2 can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS -13- 200921115 Fig. 1 is a circuit diagram showing a power supply voltage drop detecting circuit of the present invention. Fig. 2 is a circuit diagram showing a specific example of a constant current circuit of the power supply voltage drop detecting circuit of the present invention. Fig. 3 is a circuit diagram showing a power supply voltage drop detecting circuit of another embodiment of the present invention. Fig. 4 is a circuit diagram showing a specific example of a constant current circuit of a power supply voltage decrease detecting circuit of another embodiment of the present invention. Fig. 5 is a circuit diagram showing an example of an element circuit of a semiconductor device. Fig. 6 is a circuit diagram showing another example of the element circuit of the semiconductor device. Fig. 7 is a circuit diagram showing another example of the element circuit of the semiconductor device. Fig. 8 is a circuit diagram showing a conventional power supply voltage drop detecting circuit. [Main component symbol description] 1 : Power supply terminal 2 : Ground terminal 3 : Output terminals 4 to 6 : Constant current circuits 12 , 16 to 18 , 23 to 25 , 29 , 31 to 34, 52, 54: NMOS transistor ll, 21: depleted NMOS transistor-14 - 200921115 13 to 15, 19, 22, 26 to 28, 41 to 44, 51, 55 to 56: Ρ Μ Ο S transistor 53, 75, 76: resistor 7 1 : power supply 72: reference voltage circuit 73: voltage dividing circuit 7 4 : differential amplifying circuit 77: pull-up resistor -15-