JP2009065649A - Circuit for detecting power supply voltage drop - Google Patents

Circuit for detecting power supply voltage drop Download PDF

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JP2009065649A
JP2009065649A JP2008201662A JP2008201662A JP2009065649A JP 2009065649 A JP2009065649 A JP 2009065649A JP 2008201662 A JP2008201662 A JP 2008201662A JP 2008201662 A JP2008201662 A JP 2008201662A JP 2009065649 A JP2009065649 A JP 2009065649A
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voltage
power supply
circuit
transistor
supply voltage
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JP5203086B2 (en
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Fumiyasu Utsunomiya
文靖 宇都宮
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Seiko Instruments Inc
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Seiko Instruments Inc
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Priority to KR1020080077490A priority patent/KR101444465B1/en
Priority to CN2008101350007A priority patent/CN101363878B/en
Priority to US12/188,766 priority patent/US7868622B2/en
Priority to TW097130437A priority patent/TWI421508B/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0084—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring voltage only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Electronic Switches (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit for detecting power supply voltage drop, which has a small circuit scale. <P>SOLUTION: An NMOS transistor 12 generates a source voltage based on a voltage obtained by subtracting an absolute value of a threshold voltage and an overdrive voltage from a power supply voltage with reference to the power supply voltage. An NMOS transistor 17 is turned on/off on the basis of the source voltage of the NMOS transistor 12. A PMOS transistor 15 generates a source voltage based on a voltage obtained by adding an absolute value of a threshold voltage and an overdrive voltage to a ground voltage with reference to the ground voltage. A PMOS transistor 19 is turned on/off on the basis of the source voltage of the PMOS transistor 15. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、電源電圧の低下を検出する電源電圧低下検出回路に関する。   The present invention relates to a power supply voltage drop detection circuit that detects a drop in power supply voltage.

一般的に、半導体装置は、電源電圧の低下を検出する電源電圧低下検出回路を搭載している。この電源電圧低下検出回路が、電源電圧が最低動作電圧未満になったこと検出すると、半導体装置は、誤動作する回路または電源電圧低下検出回路以外の全ての回路をシャットダウンすることにより、誤動作しなくなる。   Generally, a semiconductor device has a power supply voltage drop detection circuit that detects a drop in power supply voltage. When this power supply voltage drop detection circuit detects that the power supply voltage has become lower than the minimum operating voltage, the semiconductor device does not malfunction by shutting down all the circuits other than the malfunctioning circuit or the power supply voltage drop detection circuit.

ここで、半導体装置の最低動作電圧について説明する。   Here, the minimum operating voltage of the semiconductor device will be described.

図５は、半導体装置の要素回路の例を示す回路図である。図５の回路は、ＮＭＯＳトランジスタ３１〜３４によって構成されるＮＭＯＳカスコードタイプのカレントミラー回路である。この回路の最低動作電圧は、ＮＭＯＳトランジスタ３１の閾値電圧の絶対値及びオーバードライブ電圧の合計とＮＭＯＳトランジスタ３２の閾値電圧の絶対値及びオーバードライブ電圧の合計との和電圧である。   FIG. 5 is a circuit diagram illustrating an example of an element circuit of a semiconductor device. The circuit shown in FIG. 5 is an NMOS cascode type current mirror circuit composed of NMOS transistors 31-34. The minimum operating voltage of this circuit is the sum voltage of the sum of the absolute value and overdrive voltage of the threshold voltage of the NMOS transistor 31 and the sum of the absolute value and overdrive voltage of the threshold voltage of the NMOS transistor 32.

図６は、半導体装置の他の要素回路の例を示す回路図である。図６の回路は、ＰＭＯＳトランジスタ４１〜４４によって構成されるＰＭＯＳカスコードタイプのカレントミラー回路である。この回路の最低動作電圧は、ＰＭＯＳトランジスタ４１の閾値電圧の絶対値及びオーバードライブ電圧の合計とＰＭＯＳトランジスタ４２の閾値電圧の絶対値及びオーバードライブ電圧の合計との和電圧である。   FIG. 6 is a circuit diagram illustrating an example of another element circuit of the semiconductor device. The circuit shown in FIG. 6 is a PMOS cascode type current mirror circuit composed of PMOS transistors 41 to 44. The minimum operating voltage of this circuit is the sum voltage of the sum of the absolute value and overdrive voltage of the threshold voltage of the PMOS transistor 41 and the sum of the absolute value and overdrive voltage of the threshold voltage of the PMOS transistor 42.

図７は、半導体装置の他の要素回路の例を示す回路図である。図７の回路は、ＰＭＯＳトランジスタ５１、ＰＭＯＳトランジスタ５５〜５６、ＮＭＯＳトランジスタ５２、ＮＭＯＳトランジスタ５４及び抵抗５３によって構成される定電流回路である。この回路を動作させる信号がＰＭＯＳトランジスタ５５のゲートに入力し、ＰＭＯＳトランジスタ５５がオンすると、この回路は動作する。この回路の最低動作電圧は、ＮＭＯＳトランジスタ５２の閾値電圧の絶対値及びオーバードライブ電圧の合計とＮＭＯＳトランジスタ５４の閾値電圧の絶対値及びオーバードライブ電圧の合計との和電圧、及び、ＰＭＯＳトランジスタ５５の閾値電圧の絶対値及びオーバードライブ電圧の合計とＰＭＯＳトランジスタ５６の閾値電圧の絶対値及びオーバードライブ電圧の合計との和電圧における高い方の電圧である。   FIG. 7 is a circuit diagram illustrating an example of another element circuit of the semiconductor device. The circuit in FIG. 7 is a constant current circuit including a PMOS transistor 51, PMOS transistors 55 to 56, an NMOS transistor 52, an NMOS transistor 54, and a resistor 53. When a signal for operating this circuit is input to the gate of the PMOS transistor 55 and the PMOS transistor 55 is turned on, this circuit operates. The minimum operating voltage of this circuit is the sum of the absolute value of the threshold voltage and the overdrive voltage of the NMOS transistor 52 and the sum of the absolute value and overdrive voltage of the NMOS transistor 54, and the PMOS transistor 55. The sum of the absolute value of the threshold voltage and the overdrive voltage and the sum of the absolute value of the threshold voltage and the sum of the overdrive voltage of the PMOS transistor 56 is the higher voltage.

半導体装置は、一般的に、上記の要素回路を用いることが多いので、半導体装置の最低動作電圧は、半導体装置内の最も和電圧が高い２個のＮＭＯＳトランジスタにおける、一のＮＭＯＳトランジスタの閾値電圧の絶対値及びオーバードライブ電圧の合計と他のＮＭＯＳトランジスタの閾値電圧の絶対値及びオーバードライブ電圧の合計との和電圧、及び、半導体装置内の最も和電圧が高い２個のＰＭＯＳトランジスタにおける、一のＰＭＯＳトランジスタの閾値電圧の絶対値及びオーバードライブ電圧の合計と他のＰＭＯＳトランジスタの閾値電圧の絶対値及びオーバードライブ電圧の合計との和電圧における高い方の電圧である。   Since a semiconductor device generally uses the above element circuit in many cases, the minimum operating voltage of the semiconductor device is the threshold voltage of one NMOS transistor in two NMOS transistors having the highest sum voltage in the semiconductor device. And the sum of the absolute value and overdrive voltage of the other NMOS transistor and the sum of the absolute value and overdrive voltage of the threshold voltages of the other NMOS transistors, and the two PMOS transistors having the highest sum voltage in the semiconductor device. This is the higher voltage in the sum voltage of the sum of the absolute value and overdrive voltage of the threshold voltage of the PMOS transistor and the sum of the absolute value and overdrive voltage of the threshold voltage of the other PMOS transistors.

従来の電源電圧低下検出回路について説明する。図８は、従来の電源電圧低下検出回路を示す図である。   A conventional power supply voltage drop detection circuit will be described. FIG. 8 is a diagram showing a conventional power supply voltage drop detection circuit.

従来の電源電圧低下検出回路は、基準電圧を出力する基準電圧回路７２と、電源７１の電源電圧を抵抗７５と抵抗７６とで分圧して分圧電圧を出力する分圧回路７３と、基準電圧と分圧電圧とを比較して電源電圧の低下を検出する差動増幅回路７４と、差動増幅回路７４の出力端子をプルアップするプルアップ抵抗７７と、を備えている（例えば、特許文献１参照）。
特開２００５−２７８０５６号公報（図４） A conventional power supply voltage drop detection circuit includes a reference voltage circuit 72 that outputs a reference voltage, a voltage dividing circuit 73 that outputs a divided voltage by dividing the power supply voltage of the power supply 71 by a resistor 75 and a resistor 76, and a reference voltage. And a divided voltage and a differential amplifier circuit 74 that detects a drop in power supply voltage, and a pull-up resistor 77 that pulls up the output terminal of the differential amplifier circuit 74 (see, for example, Patent Documents). 1).
Japanese Patent Laying-Open No. 2005-278056 (FIG. 4)

しかし、特許文献１によって開示された回路では、基準電圧回路、分圧回路及び差動増幅回路が必要になり、回路規模が大きくなってしまう。よって、その分、消費電流が多くなってしまう。   However, the circuit disclosed in Patent Document 1 requires a reference voltage circuit, a voltage dividing circuit, and a differential amplifier circuit, which increases the circuit scale. Therefore, current consumption increases accordingly.

本発明は、上記課題に鑑みてなされ、回路規模が小さい電源電圧低下検出回路を提供する。   The present invention has been made in view of the above problems, and provides a power supply voltage drop detection circuit having a small circuit scale.

本発明は、上記課題を解決するため、電源電圧の低下を検出する電源電圧低下検出回路において、第一導電型であり、前記電源電圧に基づき、前記電源電圧から閾値電圧の絶対値及びオーバードライブ電圧を減算した電圧に基づいたソース電圧を出力する第一トランジスタと、前記第一導電型であり、前記第一トランジスタのソース電圧に基づき、オンオフする第二トランジスタと、第二導電型であり、接地電圧に基づき、前記接地電圧に閾値電圧の絶対値及びオーバードライブ電圧を加算した電圧に基づいたソース電圧を出力する第三トランジスタと、前記第二導電型であり、前記第三トランジスタのソース電圧に基づき、オンオフする第四トランジスタと、前記第一トランジスタに電流を供給する第一定電流回路と、前記第二トランジスタ及び前記第三トランジスタに電流を供給する第二定電流回路と、前記第四トランジスタに電流を供給する第三定電流回路と、を備えていることを特徴とする電源電圧低下検出回路を提供する。   In order to solve the above-mentioned problem, the present invention provides a power supply voltage drop detection circuit for detecting a drop in power supply voltage, which is of the first conductivity type, and based on the power supply voltage, an absolute value of threshold voltage and an overdrive from the power supply voltage. A first transistor that outputs a source voltage based on a voltage obtained by subtracting a voltage; the first conductivity type; a second transistor that turns on and off based on a source voltage of the first transistor; and a second conductivity type. A third transistor that outputs a source voltage based on a ground voltage based on a voltage obtained by adding an absolute value of a threshold voltage and an overdrive voltage to the ground voltage; and a source voltage of the third transistor that is of the second conductivity type. A fourth transistor that is turned on and off, a first constant current circuit that supplies current to the first transistor, and the second transistor. And a second constant current circuit for supplying current to the third transistor, and a third constant current circuit for supplying current to the fourth transistor. .

本発明の電源電圧低下検出回路は、基準電圧回路、分圧回路及び差動増幅回路が不必要になり、回路規模が小さくなる。よって、その分、消費電流が少なくなる。   In the power supply voltage drop detection circuit of the present invention, the reference voltage circuit, the voltage dividing circuit, and the differential amplifier circuit are unnecessary, and the circuit scale is reduced. Therefore, the current consumption is reduced accordingly.

以下、本発明の電源電圧低下検出回路の実施形態を、図面を参照して説明する。   Embodiments of a power supply voltage drop detection circuit according to the present invention will be described below with reference to the drawings.

図１は、本発明の電源電圧低下検出回路を示す回路図である。   FIG. 1 is a circuit diagram showing a power supply voltage drop detection circuit according to the present invention.

本発明の電源電圧低下検出回路は、電源端子１、接地端子２及び出力端子３を備えている。また、電源電圧低下検出回路は、定電流回路４〜６を備えている。また、電源電圧低下検出回路は、ＮＭＯＳトランジスタ１２、ＮＭＯＳトランジスタ１７、ＰＭＯＳトランジスタ１５及びＰＭＯＳトランジスタ１９を備えている。   The power supply voltage drop detection circuit of the present invention includes a power supply terminal 1, a ground terminal 2, and an output terminal 3. The power supply voltage drop detection circuit includes constant current circuits 4 to 6. The power supply voltage drop detection circuit includes an NMOS transistor 12, an NMOS transistor 17, a PMOS transistor 15, and a PMOS transistor 19.

定電流回路４がＮＭＯＳトランジスタ１２のソースと接地端子２との間に設けられている。定電流回路５が電源端子１とＰＭＯＳトランジスタ１５のソースとの間に設けられている。定電流回路６が出力端子３と接地端子２との間に設けられている。ＮＭＯＳトランジスタ１２のゲート及びドレインは電源端子１に接続され、バックゲートは接地端子２に接続されている。ＮＭＯＳトランジスタ１７のゲートはＮＭＯＳトランジスタ１２のソースに接続され、ソース及びバックゲートは接地端子２に接続され、ドレインはＰＭＯＳトランジスタ１５のドレインに接続されている。ＰＭＯＳトランジスタ１５のゲートは接地端子２に接続され、バックゲートは電源端子１に接続されている。ＰＭＯＳトランジスタ１９のゲートはＰＭＯＳトランジスタ１５のソースに接続され、ソース及びバックゲートは電源端子１に接続され、ドレインは出力端子３に接続されている。   A constant current circuit 4 is provided between the source of the NMOS transistor 12 and the ground terminal 2. A constant current circuit 5 is provided between the power supply terminal 1 and the source of the PMOS transistor 15. A constant current circuit 6 is provided between the output terminal 3 and the ground terminal 2. The gate and drain of the NMOS transistor 12 are connected to the power supply terminal 1, and the back gate is connected to the ground terminal 2. The gate of the NMOS transistor 17 is connected to the source of the NMOS transistor 12, the source and back gate are connected to the ground terminal 2, and the drain is connected to the drain of the PMOS transistor 15. The PMOS transistor 15 has a gate connected to the ground terminal 2 and a back gate connected to the power supply terminal 1. The gate of the PMOS transistor 19 is connected to the source of the PMOS transistor 15, the source and back gate are connected to the power supply terminal 1, and the drain is connected to the output terminal 3.

ＮＭＯＳトランジスタ１２及びＮＭＯＳトランジスタ１７について、ＮＭＯＳトランジスタ１２の閾値電圧の絶対値及びオーバードライブ電圧の合計とＮＭＯＳトランジスタ１７の閾値電圧の絶対値及びオーバードライブ電圧の合計との和電圧は、半導体装置内の所定の２個のＮＭＯＳトランジスタにおける一のＮＭＯＳトランジスタの閾値電圧の絶対値及びオーバードライブ電圧の合計と他のＮＭＯＳトランジスタの閾値電圧の絶対値及びオーバードライブ電圧の合計との和電圧よりも、高くなっている。ＰＭＯＳトランジスタ１５及びＰＭＯＳトランジスタ１９についても、同様である。   Regarding the NMOS transistor 12 and the NMOS transistor 17, the sum of the absolute value of the threshold voltage and the overdrive voltage of the NMOS transistor 12 and the sum of the absolute value of the threshold voltage and the overdrive voltage of the NMOS transistor 17 is The sum of the absolute value and overdrive voltage of the threshold voltage of one NMOS transistor and the sum of the absolute value and overdrive voltage of the threshold voltages of the other NMOS transistors in a given two NMOS transistors is higher. ing. The same applies to the PMOS transistor 15 and the PMOS transistor 19.

また、定電流回路４は、ＮＭＯＳトランジスタ１２に電流を供給する。定電流回路５は、ＮＭＯＳトランジスタ１７及びＰＭＯＳトランジスタ１５に電流を供給する。定電流回路６は、ＰＭＯＳトランジスタ１９に電流を供給する。ＮＭＯＳトランジスタ１２は、電源電圧に基づき、電源電圧から閾値電圧の絶対値及びオーバードライブ電圧を減算した電圧に基づいたソース電圧を出力する。このソース電圧に基づき、ＮＭＯＳトランジスタ１７は、オンオフする。ＰＭＯＳトランジスタ１５は、接地電圧に基づき、接地電圧に閾値電圧の絶対値及びオーバードライブ電圧を加算した電圧に基づいたソース電圧を出力する。このソース電圧に基づき、ＰＭＯＳトランジスタ１９は、オンオフする。   The constant current circuit 4 supplies current to the NMOS transistor 12. The constant current circuit 5 supplies current to the NMOS transistor 17 and the PMOS transistor 15. The constant current circuit 6 supplies a current to the PMOS transistor 19. The NMOS transistor 12 outputs a source voltage based on a voltage obtained by subtracting the absolute value of the threshold voltage and the overdrive voltage from the power supply voltage based on the power supply voltage. Based on this source voltage, the NMOS transistor 17 is turned on and off. The PMOS transistor 15 outputs a source voltage based on a voltage obtained by adding the absolute value of the threshold voltage and the overdrive voltage to the ground voltage based on the ground voltage. Based on this source voltage, the PMOS transistor 19 is turned on and off.

次に、本発明の電源電圧低下検出回路の動作について説明する。   Next, the operation of the power supply voltage drop detection circuit of the present invention will be described.

ここで、ＮＭＯＳトランジスタの閾値電圧の絶対値をＶｔｎとし、ＰＭＯＳトランジスタの閾値電圧の絶対値をＶｔｐとする。   Here, the absolute value of the threshold voltage of the NMOS transistor is Vtn, and the absolute value of the threshold voltage of the PMOS transistor is Vtp.

［Ｖｔｐ＞Ｖｔｎの時（ＮＭＯＳトランジスタがＰＭＯＳトランジスタよりもオフしにくい時）における電源電圧の低下検出動作］
電源電圧が低くなっていくと、ＮＭＯＳトランジスタ１２のゲート電圧が低くなっていき、ＮＭＯＳトランジスタ１２がオフしていき、ＮＭＯＳトランジスタ１７のゲート電圧も低くなっていき、ＮＭＯＳトランジスタ１７もオフしていく。よって、ＰＭＯＳトランジスタ１９のゲート電圧が高くなっていき、ＰＭＯＳトランジスタ１９はオフしていく。電源電圧が２Ｖｔｐ未満になってしまうと、ＮＭＯＳトランジスタ１２及びＮＭＯＳトランジスタ１７はまだオンしているが、ＰＭＯＳトランジスタ１５によってＰＭＯＳトランジスタ１９のゲート電圧が完全にロウにならず、ＰＭＯＳトランジスタ１９はオフする。よって、電源電圧が２Ｖｔｐ未満になってしまうと、つまり、電源電圧が半導体装置の最低動作電圧未満になると、電源電圧低下検出回路はロウ信号を検出信号として出力端子３から外部に出力する。 [Operation for detecting a drop in power supply voltage when Vtp> Vtn (when the NMOS transistor is more difficult to turn off than the PMOS transistor)]
As the power supply voltage is lowered, the gate voltage of the NMOS transistor 12 is lowered, the NMOS transistor 12 is turned off, the gate voltage of the NMOS transistor 17 is lowered, and the NMOS transistor 17 is also turned off. . Therefore, the gate voltage of the PMOS transistor 19 increases and the PMOS transistor 19 turns off. When the power supply voltage becomes less than 2 Vtp, the NMOS transistor 12 and the NMOS transistor 17 are still on, but the gate voltage of the PMOS transistor 19 is not completely lowered by the PMOS transistor 15 and the PMOS transistor 19 is turned off. . Therefore, when the power supply voltage becomes lower than 2 Vtp, that is, when the power supply voltage becomes lower than the lowest operating voltage of the semiconductor device, the power supply voltage drop detection circuit outputs a low signal from the output terminal 3 to the outside as a detection signal.

［Ｖｔｐ＜Ｖｔｎの時（ＰＭＯＳトランジスタがＮＭＯＳトランジスタよりもオフしにくい時）における電源電圧の低下検出動作］
電源電圧が低くなっていき、電源電圧が２Ｖｔｎ未満になってしまうと、ＮＭＯＳトランジスタ１２はまだオンしているが、定電流回路４によってＮＭＯＳトランジスタ１７のゲート電圧が完全にハイにならず、ＮＭＯＳトランジスタ１７はオフし、ＰＭＯＳトランジスタ１９のゲート電圧がハイになり、ＰＭＯＳトランジスタ１９もオフする。よって、電源電圧が２Ｖｔｎ未満になってしまうと、つまり、電源電圧が半導体装置の最低動作電圧未満になると、電源電圧低下検出回路はロウ信号を検出信号として出力端子３から外部に出力する。 [Operation for detecting a drop in power supply voltage when Vtp <Vtn (when the PMOS transistor is less likely to be turned off than the NMOS transistor)]
When the power supply voltage is lowered and the power supply voltage becomes less than 2 Vtn, the NMOS transistor 12 is still turned on, but the gate voltage of the NMOS transistor 17 is not completely raised by the constant current circuit 4, and the NMOS transistor The transistor 17 is turned off, the gate voltage of the PMOS transistor 19 becomes high, and the PMOS transistor 19 is also turned off. Therefore, when the power supply voltage becomes lower than 2 Vtn, that is, when the power supply voltage becomes lower than the lowest operating voltage of the semiconductor device, the power supply voltage drop detection circuit outputs a low signal from the output terminal 3 to the outside as a detection signal.

［Ｖｔｐ＞Ｖｔｎ（ＮＭＯＳトランジスタがＰＭＯＳトランジスタよりもオンしやすい時）の時における電源電圧の低下検出解除動作］
電源電圧が２Ｖｔｐ及び２Ｖｔｎの両方よりも低くなっていて、その後、電源電圧が高くなっていくと、ＮＭＯＳトランジスタ１２のゲート電圧が高くなっていき、ＮＭＯＳトランジスタ１２がオンしていき、ＮＭＯＳトランジスタ１７のゲート電圧も高くなっていき、ＮＭＯＳトランジスタ１７もオンしていく。よって、ＰＭＯＳトランジスタ１９のゲート電圧が低くなっていき、ＰＭＯＳトランジスタ１９もオンしていく。電源電圧が２Ｖｔｎ以上になると、ＮＭＯＳトランジスタ１２及びＮＭＯＳトランジスタ１７はオンするが、ＰＭＯＳトランジスタ１５によってＰＭＯＳトランジスタ１９のゲート電圧が完全にロウにならず、ＰＭＯＳトランジスタ１９はまだオフしている。電源電圧が２Ｖｔｐ以上になると、ＮＭＯＳトランジスタ１２及びＮＭＯＳトランジスタ１７はすでにオンしていて、ＰＭＯＳトランジスタ１９のゲート電圧がロウになり、ＰＭＯＳトランジスタ１９もオンする。よって、電源電圧が２Ｖｔｐ以上になると、つまり、電源電圧が半導体装置の最低動作電圧以上になると、電源電圧低下検出回路はハイ信号を検出信号として出力端子３から外部に出力する。 [Operation of detecting a decrease in power supply voltage drop when Vtp> Vtn (when the NMOS transistor is easier to turn on than the PMOS transistor)]
When the power supply voltage is lower than both 2Vtp and 2Vtn, and then the power supply voltage increases, the gate voltage of the NMOS transistor 12 increases, the NMOS transistor 12 turns on, and the NMOS transistor 17 As the gate voltage increases, the NMOS transistor 17 also turns on. Therefore, the gate voltage of the PMOS transistor 19 is lowered and the PMOS transistor 19 is also turned on. When the power supply voltage becomes 2 Vtn or more, the NMOS transistor 12 and the NMOS transistor 17 are turned on, but the gate voltage of the PMOS transistor 19 is not completely lowered by the PMOS transistor 15 and the PMOS transistor 19 is still turned off. When the power supply voltage becomes 2 Vtp or more, the NMOS transistor 12 and the NMOS transistor 17 are already turned on, the gate voltage of the PMOS transistor 19 becomes low, and the PMOS transistor 19 is also turned on. Therefore, when the power supply voltage becomes 2 Vtp or higher, that is, when the power supply voltage becomes higher than the lowest operating voltage of the semiconductor device, the power supply voltage drop detection circuit outputs a high signal as a detection signal from the output terminal 3 to the outside.

［Ｖｔｐ＜Ｖｔｎの時（ＰＭＯＳトランジスタがＮＭＯＳトランジスタよりもオンしやすい時）における電源電圧の低下検出解除動作］
電源電圧が２Ｖｔｐ及び２Ｖｔｎの両方よりも低くなっていて、その後、電源電圧が高くなっていき、電源電圧が２Ｖｔｎ以上になると、ＮＭＯＳトランジスタ１２及びＮＭＯＳトランジスタ１７はオンし、ＰＭＯＳトランジスタ１９のゲート電圧がロウになり、ＰＭＯＳトランジスタ１９もオンする。よって、電源電圧が２Ｖｔｎ以上になると、つまり、電源電圧が半導体装置の最低動作電圧以上になると、電源電圧低下検出回路はハイ信号を検出信号として出力端子３から外部に出力する。 [When Vtp <Vtn (when the PMOS transistor is easier to turn on than the NMOS transistor), the power supply voltage drop detection canceling operation]
When the power supply voltage is lower than both 2Vtp and 2Vtn, and then the power supply voltage increases and the power supply voltage becomes 2Vtn or more, the NMOS transistor 12 and the NMOS transistor 17 are turned on, and the gate voltage of the PMOS transistor 19 Becomes low, and the PMOS transistor 19 is also turned on. Therefore, when the power supply voltage becomes 2 Vtn or higher, that is, when the power supply voltage becomes higher than the minimum operating voltage of the semiconductor device, the power supply voltage drop detection circuit outputs a high signal as a detection signal from the output terminal 3 to the outside.

次に、本発明の電源電圧低下検出回路の定電流回路について説明する。図２は、本発明の電源電圧低下検出回路の定電流回路の一具体例を示す回路図である。   Next, the constant current circuit of the power supply voltage drop detection circuit of the present invention will be described. FIG. 2 is a circuit diagram showing a specific example of the constant current circuit of the power supply voltage drop detection circuit of the present invention.

定電流回路４は、例えば、デプレッションＮＭＯＳトランジスタ１１によって実現される。デプレッションＮＭＯＳトランジスタ１１のゲート、ソース及びバックゲートは接地端子２に接続され、ドレインはＮＭＯＳトランジスタ１１のソースに接続されている。デプレッションＮＭＯＳトランジスタ１１のドレインは、電流をＮＭＯＳトランジスタ１２のソースから引き抜く。   The constant current circuit 4 is realized by a depletion NMOS transistor 11, for example. The gate, source, and back gate of the depletion NMOS transistor 11 are connected to the ground terminal 2, and the drain is connected to the source of the NMOS transistor 11. The drain of the depletion NMOS transistor 11 draws current from the source of the NMOS transistor 12.

定電流回路５は、例えば、デプレッションＮＭＯＳトランジスタ１１及びＰＭＯＳトランジスタ１３〜１４によって実現される。ＰＭＯＳトランジスタ１３のゲート及びドレインはＮＭＯＳトランジスタ１２のドレインに接続され、ソース及びバックゲートは電源端子１に接続されている。ＰＭＯＳトランジスタ１４のゲートはＰＭＯＳトランジスタ１３のゲートに接続され、ソース及びバックゲートは電源端子１に接続され、ドレインはＰＭＯＳトランジスタ１５のソースに接続されている。ＰＭＯＳトランジスタ１４のドレインは、定電流回路４の電流に基づいた電流をＰＭＯＳトランジスタ１５のソースに流す。   The constant current circuit 5 is realized by, for example, a depletion NMOS transistor 11 and PMOS transistors 13 to 14. The gate and drain of the PMOS transistor 13 are connected to the drain of the NMOS transistor 12, and the source and back gate are connected to the power supply terminal 1. The gate of the PMOS transistor 14 is connected to the gate of the PMOS transistor 13, the source and back gate are connected to the power supply terminal 1, and the drain is connected to the source of the PMOS transistor 15. The drain of the PMOS transistor 14 supplies a current based on the current of the constant current circuit 4 to the source of the PMOS transistor 15.

定電流回路６は、例えば、デプレッションＮＭＯＳトランジスタ１１、ＰＭＯＳトランジスタ１３〜１４、ＮＭＯＳトランジスタ１６及びＮＭＯＳトランジスタ１８によって実現される。ＮＭＯＳトランジスタ１６のゲート及びドレインはＰＭＯＳトランジスタ１５のドレインに接続され、ソースはＮＭＯＳトランジスタ１７のドレインに接続され、バックゲートは接地端子２に接続されている。ＮＭＯＳトランジスタ１８のゲートはＮＭＯＳトランジスタ１６のゲートに接続され、ソース及びバックゲートは接地端子２に接続され、ドレインはＰＭＯＳトランジスタ１９のドレインに接続されている。ＮＭＯＳトランジスタ１８のドレインは、定電流回路４の電流に基づいた電流をＰＭＯＳトランジスタ１９のドレインから引き抜く。   The constant current circuit 6 is realized by, for example, a depletion NMOS transistor 11, PMOS transistors 13 to 14, an NMOS transistor 16, and an NMOS transistor 18. The gate and drain of the NMOS transistor 16 are connected to the drain of the PMOS transistor 15, the source is connected to the drain of the NMOS transistor 17, and the back gate is connected to the ground terminal 2. The gate of the NMOS transistor 18 is connected to the gate of the NMOS transistor 16, the source and back gate are connected to the ground terminal 2, and the drain is connected to the drain of the PMOS transistor 19. The drain of the NMOS transistor 18 extracts a current based on the current of the constant current circuit 4 from the drain of the PMOS transistor 19.

以上説明したように、本発明の電源電圧低下検出回路は、基準電圧回路、分圧回路及び差動増幅回路が不必要になり、回路規模が小さくなる。従って、消費電流も少なくなる。   As described above, the power supply voltage drop detection circuit according to the present invention eliminates the need for the reference voltage circuit, the voltage dividing circuit, and the differential amplifier circuit, thereby reducing the circuit scale. Therefore, current consumption is reduced.

また、基準電圧のばらつきを補償するために、分圧回路の抵抗トリミングが必要であったが、トリミングが不必要になる。従って、製造工程が減るので、製造コストが安くなる。   Further, in order to compensate for variations in the reference voltage, resistance trimming of the voltage dividing circuit is necessary, but trimming is unnecessary. Therefore, the manufacturing cost is reduced because the manufacturing process is reduced.

また、ＰＭＯＳトランジスタとＮＭＯＳトランジスタの動作の関係がいずれであっても、電源電圧が半導体装置の最低動作電圧未満になると、電源電圧低下検出回路はロウ信号を検出信号として出力端子３から外部に出力するので、半導体装置は誤動作しなくなる。   In addition, regardless of the operation relationship between the PMOS transistor and the NMOS transistor, when the power supply voltage becomes lower than the minimum operating voltage of the semiconductor device, the power supply voltage drop detection circuit outputs a low signal as a detection signal from the output terminal 3 to the outside. Therefore, the semiconductor device does not malfunction.

なお、図１及び図２におけるＮＭＯＳトランジスタをＰＭＯＳトランジスタに変更してＰＭＯＳトランジスタをＮＭＯＳトランジスタに変更してもよい。   The NMOS transistor in FIGS. 1 and 2 may be changed to a PMOS transistor, and the PMOS transistor may be changed to an NMOS transistor.

次に、本発明の他の実施例の電源電圧低下検出回路を、図面を参照して説明する。   Next, a power supply voltage drop detection circuit according to another embodiment of the present invention will be described with reference to the drawings.

図３は、本発明の他の実施例の電源電圧低下検出回路を示す回路図である。図１の電源電圧低下検出回路との差において、定電流回路４は定電流回路７に変更され、定電流回路５は定電流回路８に変更され、定電流回路６は定電流回路９に変更されている。   FIG. 3 is a circuit diagram showing a power supply voltage drop detection circuit according to another embodiment of the present invention. 1, the constant current circuit 4 is changed to a constant current circuit 7, the constant current circuit 5 is changed to a constant current circuit 8, and the constant current circuit 6 is changed to a constant current circuit 9. Has been.

図４は、本発明の他の実施例の電源電圧低下検出回路の定電流回路の一具体例を示す回路図である。図２の電源電圧低下検出回路との差において、ＮＭＯＳトランジスタ１２はＰＭＯＳトランジスタ２２に変更され、ＮＭＯＳトランジスタ１７はＰＭＯＳトランジスタ２７に変更され、ＰＭＯＳトランジスタ１５はＮＭＯＳトランジスタ２５に変更され、ＰＭＯＳトランジスタ１９はＮＭＯＳトランジスタ２９に変更されている。ここで、デプレッションＮＭＯＳトランジスタ１１はデプレッションＮＭＯＳトランジスタ２１に変更され、ＰＭＯＳトランジスタ１３はＮＭＯＳトランジスタ２３に変更され、ＰＭＯＳトランジスタ１４はＮＭＯＳトランジスタ２４に変更され、ＮＭＯＳトランジスタ１６はＰＭＯＳトランジスタ２６に変更され、ＮＭＯＳトランジスタ１８はＰＭＯＳトランジスタ２８に変更されている。   FIG. 4 is a circuit diagram showing a specific example of a constant current circuit of a power supply voltage drop detection circuit according to another embodiment of the present invention. 2, the NMOS transistor 12 is changed to the PMOS transistor 22, the NMOS transistor 17 is changed to the PMOS transistor 27, the PMOS transistor 15 is changed to the NMOS transistor 25, and the PMOS transistor 19 is changed. The NMOS transistor 29 is changed. Here, the depletion NMOS transistor 11 is changed to a depletion NMOS transistor 21, the PMOS transistor 13 is changed to an NMOS transistor 23, the PMOS transistor 14 is changed to an NMOS transistor 24, the NMOS transistor 16 is changed to a PMOS transistor 26, and an NMOS transistor. The transistor 18 is changed to a PMOS transistor 28.

図３、及び図４のように電源電圧低下検出回路を構成しても、図１、及び図２のような電源電圧低下検出回路と同様な効果が得られることは明白である。   Even if the power supply voltage drop detection circuit is configured as shown in FIGS. 3 and 4, it is obvious that the same effect as the power supply voltage drop detection circuit as shown in FIGS. 1 and 2 can be obtained.

本発明の電源電圧低下検出回路を示す回路図である。It is a circuit diagram which shows the power supply voltage fall detection circuit of this invention. 本発明の電源電圧低下検出回路の定電流回路の一具体例を示す回路図である。It is a circuit diagram which shows one specific example of the constant current circuit of the power supply voltage drop detection circuit of this invention. 本発明の他の実施例の電源電圧低下検出回路を示す回路図である。It is a circuit diagram which shows the power supply voltage fall detection circuit of the other Example of this invention. 本発明の他の実施例の電源電圧低下検出回路の定電流回路の一具体例を示す回路図である。It is a circuit diagram which shows one specific example of the constant current circuit of the power supply voltage fall detection circuit of the other Example of this invention. 半導体装置の要素回路の例を示す回路図である。It is a circuit diagram which shows the example of the elemental circuit of a semiconductor device. 半導体装置の要素回路の他の例を示す回路図である。It is a circuit diagram which shows the other example of the element circuit of a semiconductor device. 半導体装置の要素回路の他の例を示す回路図である。It is a circuit diagram which shows the other example of the element circuit of a semiconductor device. 従来の電源電圧低下検出回路を示す回路図である。It is a circuit diagram which shows the conventional power supply voltage fall detection circuit.

符号の説明Explanation of symbols

１ 電源端子
２ 接地端子
３ 出力端子
４〜６ 定電流回路
１１ デプレッションＮＭＯＳトランジスタ
１３〜１５、１９ ＰＭＯＳトランジスタ
１２、１６〜１８ ＮＭＯＳトランジスタ DESCRIPTION OF SYMBOLS 1 Power supply terminal 2 Ground terminal 3 Output terminals 4-6 Constant current circuit 11 Depletion NMOS transistors 13-15, 19 PMOS transistors 12, 16-18 NMOS transistors

Claims (1)

電源電圧の低下を検出する電源電圧低下検出回路において、
第一導電型であり、前記電源電圧に基づき、前記電源電圧から閾値電圧の絶対値及びオーバードライブ電圧を減算した電圧に基づいたソース電圧を出力する第一トランジスタと、
前記第一導電型であり、前記第一トランジスタのソース電圧に基づき、オンオフする第二トランジスタと、
第二導電型であり、接地電圧に基づき、前記接地電圧に閾値電圧の絶対値及びオーバードライブ電圧を加算した電圧に基づいたソース電圧を出力する第三トランジスタと、
前記第二導電型であり、前記第三トランジスタのソース電圧に基づき、オンオフする第四トランジスタと、
前記第一トランジスタに電流を供給する第一定電流回路と、
前記第二トランジスタ及び前記第三トランジスタに電流を供給する第二定電流回路と、
前記第四トランジスタに電流を供給する第三定電流回路と、
を備えていることを特徴とする電源電圧低下検出回路。 In the power supply voltage drop detection circuit that detects the power supply voltage drop,
A first transistor that is a first conductivity type and outputs a source voltage based on a voltage obtained by subtracting an absolute value and an overdrive voltage of a threshold voltage from the power supply voltage based on the power supply voltage;
A second transistor of the first conductivity type that turns on and off based on a source voltage of the first transistor;
A third transistor that is a second conductivity type and outputs a source voltage based on a voltage obtained by adding an absolute value of a threshold voltage and an overdrive voltage to the ground voltage based on the ground voltage;
A fourth transistor of the second conductivity type, which is turned on and off based on a source voltage of the third transistor;
A first constant current circuit for supplying current to the first transistor;
A second constant current circuit for supplying current to the second transistor and the third transistor;
A third constant current circuit for supplying current to the fourth transistor;
A power supply voltage drop detection circuit comprising:
JP2008201662A 2007-08-10 2008-08-05 Power supply voltage drop detection circuit Active JP5203086B2 (en)

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KR1020080077490A KR101444465B1 (en) 2007-08-10 2008-08-07 Circuit for detecting source voltage lowering
CN2008101350007A CN101363878B (en) 2007-08-10 2008-08-08 Circuit for detecting power supply voltage drop
US12/188,766 US7868622B2 (en) 2007-08-10 2008-08-08 Circuit for detecting power supply voltage drop
TW097130437A TWI421508B (en) 2007-08-10 2008-08-08 Power supply voltage reduction detection circuit

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