TW200910540A - Package structure and manufacturing method thereof - Google Patents
Package structure and manufacturing method thereof Download PDFInfo
- Publication number
- TW200910540A TW200910540A TW096130959A TW96130959A TW200910540A TW 200910540 A TW200910540 A TW 200910540A TW 096130959 A TW096130959 A TW 096130959A TW 96130959 A TW96130959 A TW 96130959A TW 200910540 A TW200910540 A TW 200910540A
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- Prior art keywords
- carrier
- wafer
- connection
- package
- crystal structure
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- H01L2924/181—Encapsulation
Description
200910540 玖、發明說明: 【發明所屬之技術領域】 本發明係有關於-種封裝架構及·造方法,特默有_—種於 器 承載器上形成有—.結構,晶片可嵌設於其巾麟確配置於承载 上之新式封裝架構及其製造方法。 【先前技術】 由於晶片技術不斷朝高頻、高腳數的方向發展,單純依靠傳統的打 線封裝並無法滿足電性上的要求。覆晶封裝係獅触凸塊作爲晶片 細反間之連接的封裝技術,覆晶封裝除了可大幅度提高晶片接聊的 讀以外’更可降低雜訊谓、触紐效能、提高散熱性能及縮減 封裝體積等。惟’此種覆晶職财相#麵技術細f要克服。例 如爲確保晶片與基板之間的密合,須以點膠方式來填滿晶片與基板 間之空隙 '然而,在點膠作業時,膠體之流動方向很難控制,極易造 成充填膠體外溢,污_位於基板轉區料之表面,以致影響後續 之銲線或其他被動元件之裝設品質。 美國專利第MGM36號提出—種在基板上形成—阻溢堤的半導 體晶片結構體200,如第-圖所示,該阻溢謂係位於基板撤之晶 片接置區2021與外銲墊2022之間的區域中。惟,雖舰習知半導體 晶片結構體之阻溢堤測可以解決溢膝的問題,但由於基板2〇2 與晶片203之間的空隙报小,而晶片2〇3之接腳數又相當的多,因此 在封膠製程中’虽要利用封膠2〇4填滿基板2〇2與晶片2〇3之間的空 隙時’不但要花費很長-段時間,而且對封膠材料的減、溫度均有 200910540 相當1¾的要I ’甚至於封膠材料的熱膨脹係數亦要詳加考慮,否則會 嚴重景>響該半導體aaa片結構體測内部之電性連接的安全性。 f \ έ 爲解決上述問題,美國專利第6,138,348號提出一種在基板上形成 内連接導電聚合物300之方法,如第二圖所示,於第一基板3〇1之每 -第-接合墊3011上均形成有一導電塊3〇12,於第二基板3〇2之其中 一表面形成一有機保護層303,並且第二基板3〇2之每一第二接合墊 3021均分別暴露於該有機保護層3()3之通孔細中。當第一基板謝 认置於第一基板302上時’藉由第一接合塾謝卜導電塊綱2及第二 接σ墊3021之相互連接’可使得第一基板3〇1與第二基板观之間形 成電連接。惟,該習知方法雖可避免於第一基板謝與第二基板她 之間產生間隙’從而解決封膠困難的問題,但該方法必須要借助對位 接合器雜bonder),才能夠使得位於第—基板謝上的第一接 合墊3G11與導魏3G12賴目應通孔·丨及第二接合塾·。惟, 藉由對位接合器而使得第一基板謝配置於第二基板繼上的方法和 當複雜、操作極其錢,該習知結構設計存在有缺陷,故仍有進—步 改進之必要。 ’ 【發明内容】 本發明之主要目的在於提供__餘淑其製造方法,其可以簡 化封裝架翻製程,錄高難麵之紐連接效果。 依據本㈣之上述目的,本發日峨供—種封裝轉,叫含有.— 承載器、―㈣架構及H射承翻具有相對之—第一表面及 200910540 -第二表面,該第—表面上具有複數個第—連接墊;固晶架構係設置 於該承載器上,該固晶架構具有相對之—第—表面及—第二表面,且 該固晶架構之第二表面係輯於該承脑之第—表社,顧晶架構 β 複數轉塊’其中凹槽係形成 “爲B架構之第—表面上’堤壩係位於該凹槽周遭;該些通孔係位 於該凹槽之區翻並貫穿於觀晶架構之第_表面及第二表面 ;該些 銲鬼係合、膽通孔巾,其巾該魏孔及其崎應之職係位於該承載 器之該些第-連接塾上,並且該些第—連接塾與對應之銲塊形成電性 接觸’以及aa>j具有相狀—主動面及_背面,於該主動面上具有複 數個第-銲塾’該晶片係嵌置於該固晶架構之凹彻,且其主動面係 緊貼於顧晶_之第-表面上,而該些第—銲賴與對應之銲塊形 成電性接觸。 依據本發明之上述目的’本發賴供—觀餘狀製造方法,其 包含有以下步驟: 提供-承顧’該承顧具有⑽之—第—表面及—第二表面,該 第一表面上具有複數個第一連接墊; 形成-固晶架構於該承載II的第―表面,該固晶雜具有相對之_ 第-表面及-第二表面’且顧晶架構之第二表面緊貼於該承载器之 第-表面,該雜包含有—哺,係形成於朗晶架構之第一表 面上;-堤壩,餘於該凹槽周遭;以及複數個通孔,係位於該凹槽 之區域内並貫穿於顧晶架構之第—表面及第二表面,且該些通孔係 200910540 位於該承鑛之該些第—連跡上,並職些第—連接絲露於其中; 植入複數個銲塊於該些通孔中,該些銲塊係位於該承載器之該些第 一連接塾上,並且與該些第一連接墊形成電性接觸;以及 嵌入-晶片於該固晶架構之凹槽内,該晶片具有相對之一主動面及 於該主動©_L具有複數個第—銲墊,且該絲面係緊貼於該 固晶架構之第—表面上’而該些第—銲制與對應續塊形成電性接 觸。 *與先前技術相比較,本發明封裝架構之晶片絲設於固晶架構内並 藉此準確配置於承載紅,如料__程,還可錢得封裝架 構内之晶片與承載器之間形成穩定之電性連接效果。 、 【實施方式】 本貫施例將會結合圖示對本發明嶋構之製造方法作詳細介紹。 請參照第三A圖及第五圖之步驟a所示,首先須提供 該承載器1G具有崎之-第—表㈣及—第二表面12,且於第一表 成有咖 明π乐二β圃所示 q⑼"、吨小軾亞iU艾第一表面 上/在本實施例中,該塗覆層扣係-阻銲層(solder喊)。 請參照第三C圖所示,對該塗覆層2G進行侧以於該承載器1〇 的第一表面11形成—固晶架構加,該固晶架構30具有相對之—第 表面31及H面32,卿晶咖㈣二細係緊貼於承 200910540 載器1〇之第表面11上。該固晶架構30包含有一凹槽33、一堤域 &複數個通孔35°該凹槽犯係形成於固晶架構3()之第—表面^ 在本實此例中,该凹槽33係位於承載器1〇之晶片接置區Μ内; &疋壩34係位於凹槽33周遭,且位於承載器1〇之晶片接置區μ外。 z-通孔35係位於該凹槽33的區域内並貫穿於該固晶架構洲之第一 表面31及第一表面32之間’且該些通孔奶係位於該承載器ι〇之該 -第連接墊13上’並將該些第—連接墊η暴露於其中。 在本實施例中,該堤壩34之高度係小於該晶片50之背面52之高 \如第一 E圖中所不。當然,該堤壩34之高度亦可等於該晶片5〇 背面52之冋度’而只須確保晶片5〇係以後入之方式置於該凹槽% 中即可。 本發明可、料_或籽束侧
層20進行侧。需要說明的3 士欲 M &«Μ的疋,本發日細晶架構3G之形成可不限定 _塗覆㈣餅她軸,㈣_财恤,例如,藉由 ^該承載㈣的第—表面11形成――請,並且該該晶圓 之各個部分:凹槽33、一堤壩34及複數個通孔35,可以是一 是各卿分分飾成。本㈣之重點在於:於該承載 器10的第一表面11形成一固晶芊槿初& 難曰Μ 3賴3G,轉以賴賴層20進行蝕 刻爲目的,如第五圖之步驟b所示。 請參照第三D圖及第五圖之步驟 晶架構加之該些通孔35中,該此_塊=#複數個輝塊40於固 4塊40係位於該承载器10之該些 200910540 第連接塾13上’並與該些第一連接塾以形成電性接觸。 請參照第三請及第五圖之步驟_示,50於該固晶 架構3〇之凹槽33内,該晶片具有相對之-主動面51及-背面52, 於„亥主動面51上设有複數個第—輝墊53,且該主動面51係緊貼於該 固晶架構3〇之第一表面31上’而該些第—銲墊53則與對應之鐸塊4〇 形成電性接觸。 藉由乂上製xe方法而形成—新式封裳架構通,如第三e圖所示, 裳架構雇之晶片50係嵌人於固晶架構加内並藉此設置於承載 器10上。如此,不但可簡化製程,還可以在晶片50與承個10之間 形成穩定之電性連接效果。 田…、在上述步驟d之後,本發贿裝架構⑽之製造方法還可以 另外再進行-回銲步驟,即對第—連接墊13 '馳4q及第—鲜塾犯 進行加熱,賤得該等獅結在—起。然後,再形成—封㈣於該 承載W之第-表面U上,如第三F _示,該封雜覆蓋該晶片 5〇、該固晶架構30及該承載器1〇之第—表面 請參照第四®所示,於本發簡餘構⑽之承載㈣之第一表 面η上還可設置複辑二連接墊15,該些第二繼15係位於晶 片接置區14外。另外,在該承細G之第二表面12上可設置複數個 第三連接墊16 f纖_ 7Q。聲編5Q之背面 犯上亦賴54。姐觀打,繩雜中,可 於封膠之前,進行—打線步驟,以形成複數條銲線80於該晶片50及 200910540 該承載器10之間,用以連接晶片50之第二銲墊52及承載器ι〇之第 一連接墊15。然後,再進行封膠製程,以形成一封膠6〇於該承載器 之第一表面11上,覆蓋該晶片50、該固晶架構3〇、該承載器1〇之 第—表面Η、該些銲線80、該晶片50之第二銲墊54,以及該承載器 10之第二連接墊15。而於封膠之後’該方法還可再包含有植鲜球之步 驟,即形成複數個銲球70於該承載器10之該些第三連接墊16上。 綜上所述,本發明確已符合發明補之要件,爰依法提出專利申 "月准,以上所述者僅爲本發明之較佳實施方式,舉凡熟習本案技術 之人士援依本發明之精神所作之等效修飾或變化,冑涵級後附之申 請專利範圍内。 【圖式簡單說明】 第一圖係一習知封裝結構之示意圖。 第二圖係另一習知封裝結構之示意圖。 第三Α圖係顯示本發明承載器之示意圖。
第三E圖係顯示本發明嵌入— 第三F圖係顯示本發明形成— 塗覆層於承載器之第一表面上之示意圖。 器的第-表面形成-固晶架構之示意圖。 數個銲塊於固綠構之舰巾的示意圖。 晶片於固晶架構之凹槽内的示意圖。 第四圖係顯示本發明封裝架構之示惫圖
封膠於承載ϋ之第_表面上的示意圖。 之示意圖。 之封裝方法之流程圖。 200910540 【主要元件符號說明】 封裝架構 100 承載器 10 承載器之第一表面11 承載器之第一表面12 第一連接墊 13 晶片接置區 14 、 2021 第二連接墊 15 第三連接墊 16 塗覆層 20 固晶架構 30 固晶架構之第 一表面31 固晶架構之第一表面32 凹槽 33 堤壩 34 通孔 35 ' 3031 銲塊 40 晶片 50、203 主動面 51 背面 52 第一銲墊 53 第二銲墊 54 封膠 60 ' 204 鲜球 70 銲線 80 半導體晶片結構體200 阻溢堤 201 基板 202 外銲墊 2022 内連接導電聚合物300 第一基板 301 第一接合墊 3011 導電塊 3012 第二基板 302 第二接合墊 3021 有機保護層 303 12
Claims (1)
- 200910540 拾、申請專利範圍: 1 ·一種封裝架構,包含有: -承載器,具有相對之—第—表面及―第二表面,於該第一表 面上具有複數個第一連接墊; -固晶架構’設置於該承顧上,觀晶架構具有相對之—第 一表面及-第二表面,且棚晶架構之第二表面师貼於該承栽器 之第一表面上,該固晶架構包含有: 一凹槽,形成於該固晶架構之第一表面上; 一堤壩,位於該凹槽周遭; 複數個通孔,位於該凹槽之區域内並貫穿該固晶架構之第 一表面及第二表面;及 複數個輝塊’容納於該些通孔中; 其中該些通孔及其内對應之銲塊係位於該承載器之該些 第-連接塾上,並且該些第—連接塾與對應之銲塊形成電性接 觸;以及 一晶片,具有相對之-主動面及-麵,於該主動面上具有複 數個第-銲塾’該晶片係嵌置於該固晶架構之凹槽内,且其主動面 係緊貼於賴晶架構之第—表面上,而該些第—銲墊則與對應之鲜 塊形成電性接觸。 2.如申請專利範圍第1項所述之封裝架構,更包含有一封膠, 係設置於該承翻之第-表面上,並且覆蓋該晶片、翻晶架構及 13 200910540 該承载器之第一表面。 .爾利輪!項所述之封裝架構,其 是攝之高細、_物㈣㈣度。… 之第4 :申請專利範圍第1項所述之封裝架構,其中於該承載器 B片接f面上蝴—晶咖區,她係形成於該 日日片接置區内。 該晶片接置區内 =Μ請專· „4項所述之封餘構,其中棚晶架構 4係位於該晶片接置區外,而該固晶架構之凹槽之區域係位於 6 .如申請專利_第4項所述之封縣構,其中於該承載器 之第—表面上還具有複數個第二連接墊,且該些第二連接塾係位於 該晶片接置區外。 7如申凊專利範圍第6項所述之封裝架構,其中於該晶片之 背面上還具有複數個第二銲墊。 8.如申請專利範圍第7項所述之封裝架構,其還包含有複數 條鲜線’連接於該晶片之第二銲塾與該承載器之第二連接墊之内。 9·如申請專利範圍第8項所述之封裝架構,其中更包含有一 封膠’該封膠覆蓋該晶片、該固晶架構、該承載器之第一表面、該 些銲線、該晶片之第二銲塾,以及該承載器之第二連接墊。 10 ·如申請專利範圍第】或9項所述之封裝架構’其中於該承 載器之第二表面上具有複數個第彡連接墊’該些第三連接墊上設置 14 200910540 有複數個銲球。 U ·-種魏架構之製造方法,包含打列步驟: 提供-承載n,該承鮮具有相對之―第—表面及—第二表 面,該第一表面上具有複數個第一連接墊; 形成-固晶架構於縣鶴料_絲上,細晶架構具有相 對之1-表面及-第二表面,且該固晶架構之第二表面緊貼於該 承載器之第-表面,該固晶架構包含有—凹槽,形成於該固晶架構 之第-表面上;-堤場’位於該凹槽周遭;以及複數個通孔,位於 ,凹槽之區域内並貫穿於·晶架構之第—表面及第二表面,且該 通孔係位於該承載ϋ之馳第―連跡上,並賴鮮—連接塾 暴露於其中; &植人概_胁舰巾,該餅藝錄棘載器之該 些第-連接墊上,並且與該些第一連接塾形成電性接觸;以及 嵌入-晶片於該固晶架構之凹槽内,該晶片具有相對之一主動 面及一背面’触動面上具有複數個第—銲墊,且該絲面係緊貼 於該固晶面上’親㈣—_細之鮮塊形成 電性接觸。 κ如申請專利範圍第u項所述之封裝架構之製造方法,更 包含形成-_於該承餘之第―表面上,㈣蓋該以、該固晶 架構及該承裁器之第一表面。 13 .如”專利範圍第u項所述之封裝架構之製造方法,其 15 200910540 中該固晶賴之堤壩之高度係小於或等於該晶片之背面之高度。 14 .如申請專利範圍第11項所述之封裝架構之製造方法,其 中形成該IS晶架構的步驟包含有敷設—塗覆層於該承載器之第一 表面,並侧該鍵層以形成觀晶架構。 15如巾4專鄕圍第14項所述之封裝架構之製造方法,其 中對該塗覆層進行_可輯膽絲刻、濕絲麟離子束姓 刻。 16如申明專利範圍第u項所述之封裝架構之製造方法,其 中於封膠之别’ 4方法還包含有回輝步驟,以對第—連接塾、鲜塊 及第-銲墊進行加熱’以使得鱗元件麟在一起。 17如申叫專利範圍第1丨項所述之封裝架構之製造方法,其 中於該承載器之第-表面上形成有—晶片接置區 ,該些第一連接墊 係形成於該晶片接置區内。 18·如申印專利範圍第17項所述之封裝架構之製造方法,該 口 β曰木構之i疋壩係位於該晶片接置區外,而該固晶架構之凹槽之區 域係位於該晶片接置區内。 19如中轉利麵第17項所述之封餘構之製造方法,其 中該承载ϋϋ面上具有概_二連難,且触第二連接 墊係位於該晶片接置區外。 20如申叫專利範圍帛19項所述之封裝架構之製造方法,其 中該晶片之背面上具有複數個第二銲墊。 200910540 .如申5胃專利姻第2G項所述之封裝架構之製造方法,其 中於封谬之⑴該方法還包含有—打線步驟,其係形賴數條輝線 於該晶片及該承載器之間,用以連接該晶片之第二銲墊及該承載器 之第二連接墊。 22 .如申請專利範圍帛21項所述之封裝架構之製造方法,其 中更包含形成-層於該承餘之第—表面上,以覆蓋該晶片、該 固晶架構、該承載器之第-表面、該些銲線、該晶片之第二鮮塾, 以及該承載器之第二連接墊。 23·如申請專利範圍第η或22項所述之封裝架構之製造方 法,其中該承載器之第二表面上具有複數個第三連接墊。 24 .如申請專利範圍第23項所述之封裝架構之製造方法,其 中於封膠之後’該方法還包含有―麟球之轉,其係形成複數個 銲球於該承载器之該些第三連接墊上。 17
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US9059187B2 (en) * | 2010-09-30 | 2015-06-16 | Ibiden Co., Ltd. | Electronic component having encapsulated wiring board and method for manufacturing the same |
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