Ο Ο 200901417 061100^ 22553twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種線路板製裎（Circuit Board ’且制是有·—難有導電孔以埋式線路 【先前技術】 近年f著電子玉業之生產技術的突餘進，線路板Ο Ο 200901417 061100^ 22553twf.doc/n IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a circuit board (Circuit Board 'and has a conductive hole to be buried) [Prior technology] In recent years, the production technology of the electronic jade industry has made a sudden advance, the circuit board
(Qnmit BGafd)可搭載各種體積精巧之電子零件，以廣 泛地應用於各種不同功㈣f子產品。下文將說明習知之 線路板的製作過程。請參考圖1A至圖1F，圖1A至圖1F :二為=之一種線路板製程的流程剖面圖。習知之線路 二列步驟:首先，如圖1A所示，提供-基板 入土板11(3具有—介電層112以及二銅羯層ιΐ4, 」電層=配設於二銅落層114之間。然後，如圖汨所 不，以？械鑽孔之方式於基板n。上形成—通孔12〇。 接，’如圖1C所示’利用電錢製程於銅謂層114以 内壁上形成—導電層13G，導電層i3G係可電 二电層112兩側之線路。緊接著，如圖1D所示， 阻3上形成1案化光阻層140 ’其中圖案化光 =二暴露出部份導電層13G。接著，如圖1Ε所示，以 二14D異^層14G為I幕’並利驗刻技術對圖案化光阻 二 ' 路之部伤導電I 130以及銅㈣1H進行圖案化 成圖案化導電層削，以及圖案化織層114,， θ木V電層130以及圖案化銅箱層114，即構成一圖案 5 200901417 0611002 22553twf.doc/n 化線路層15〇。之後，如圖1F所示，移除时 140，以完成習知之線路板1〇〇的製作。 、先阻層 提的是，在频電路的設計愈趨複雜以 ^的'WF ’線路板中之線路設計亦愈趨精細 ^ 在上述形賴案化線路層15()之_中，f ^ ’ 姓刻製程來移除圖案化光阻層⑽暴露之部份導電=用 Ο ο 以及銅11層114,以製作出圖案化線路層15。4中:二 銅箔層114以及材質例如是銅 j 由於 其厚度有較大之變異性(即圖二 且習知技術無法穩定地控制㈣ g =層=以及導電層13〇之_呈度），,= =圖案化線路層15。其線路寬度不易符合細線= 魏寬!層114从導電層13G過度㈣而導致 製程ΐ:製作換言之，習知之線路板 中，圖料2^、有 線路板。此外，在習知技術 =化線路層15G與介電層112間僅具有—接觸面， 芦化線路層15G容易因不#之外力而自介電 " 上剝落，導致線路板100之可靠度降低。 此ί卜在後續的晶#縣製程巾，由於圖案化線路層 時，^、面車乂不平整。因此’當晶片配設於線路板100上 虹ιηΓ片日無去有效地與線路板100接合，造成晶片與線路 路犀^之兒性連接品質不佳。另一方面，由於圖案化線 # 、面不平整，因此當晶片配設於線路板100時，晶 '、、、、路板100間之接觸應力分布即不平均，進而影響晶 6 200901417 U6110U2 22553twf.doc/n 片封裝結構之可靠度。 【發明内容】 〇本發明是提供一種具有導電孔之内埋式線路板製 私’其製作出具有較佳可靠度之線路板，且線路板表面有 較佳之平整度’以有效地與—晶片接合。(Qnmit BGafd) can be used in a variety of compact electronic components to be widely used in a variety of different (four) f sub-products. The fabrication process of the conventional circuit board will be described below. Please refer to FIG. 1A to FIG. 1F, FIG. 1A to FIG. 1F are cross-sectional views showing the process of a circuit board process. The conventional two-step circuit steps: First, as shown in FIG. 1A, a substrate-inserted board 11 is provided (3 has a dielectric layer 112 and a copper layer ΐ4, and an electric layer = is disposed between the two copper layers 114). Then, as shown in Fig. 形成, the through hole 12 is formed on the substrate n by means of mechanical drilling. Connected, 'as shown in Fig. 1C', the electric wall process is formed on the inner wall of the copper layer 114. a conductive layer 13G, the conductive layer i3G being a line on both sides of the electrically electric layer 112. Next, as shown in FIG. 1D, a resistive photoresist layer 140 is formed on the resistor 3, wherein the patterned light = two exposed portions Part of the conductive layer 13G. Next, as shown in FIG. 1A, the pattern of the patterned photoresist 2' and the copper (4) 1H is patterned by using the 14D layer 14G as the I-screen. The conductive layer is cut, and the patterned woven layer 114, the θ wood V electrical layer 130 and the patterned copper box layer 114 constitute a pattern 5 200901417 0611002 22553 twf.doc/n circuit layer 15 〇. Thereafter, as shown in FIG. 1F As shown, 140 is removed to complete the fabrication of the conventional circuit board 1 。. The first resistance layer is that the design of the frequency circuit is becoming more and more The circuit design in the 'WF' circuit board mixed with ^ is also more and more fine ^ In the above-mentioned shape circuit layer 15 (), the f ^ ' surname process to remove the patterned photoresist layer (10) exposed Partially conductive = Ο ο and copper 11 layer 114 to form patterned circuit layer 15. 4: 2nd copper foil layer 114 and material such as copper j due to its large variability (ie Figure 2 and The conventional technique cannot stably control (4) g = layer = and the thickness of the conductive layer 13), = = patterned circuit layer 15. The line width is not easy to conform to the thin line = Wei width! The layer 114 is excessive from the conductive layer 13G (4) And the process ΐ: in other words, in the conventional circuit board, the picture material 2^, there is a circuit board. In addition, in the conventional technology = the circuit layer 15G and the dielectric layer 112 only have a - contact surface, the reed circuit layer 15G is easy to peel off due to non-external force, and the reliability of the circuit board 100 is reduced. This ίbu is in the subsequent crystal #县process towel, due to the patterning of the circuit layer, ^, no face car Therefore, when the wafer is disposed on the circuit board 100, the rainbow is not effectively bonded to the circuit board 100. The quality of the connection between the wafer and the circuit path is not good. On the other hand, since the pattern line # and the surface are not flat, when the wafer is disposed on the circuit board 100, the crystal ', , , and the road plate 100 The contact stress distribution is uneven, which in turn affects the reliability of the crystal package. The invention provides a built-in circuit board with conductive holes. A circuit board having better reliability is provided, and the surface of the board has a better flatness 'to effectively bond with the wafer.
為達上边或是其他目的，本發明提出一種具有導電孔 之内埋式線路板製程，其包括下列步驟：首先，提供一内 埋式線路基板’其包括—介電層、—第—線路層以及一第 :線路層:其中，介電層具有相對應之—第—表面與一第 表面帛、線路層内埋於第―表面，^^第—線路層之外 側表面，第-表面共平面，而第二線路層内埋於第二表 2且第二線路層之外側表面與第二表面共平面。然後， =内^線路基板上形成—開孔。接著，於該第一表面、 面？及開孔之内壁上形成-導電層。之後，移除第 ^。、帛二表面上以及開孔外側之導電層，以形成—導 開孔月之一實施例中’於第—表面、第二表面以及 二 成導電層之方式包括下列步驟：首先，於 =、第二表面以及開孔之内壁上形成—電錢種子 者’於電鍍種子層上形成—電錢層，而導電層包括 電鍍層以及電鍍種子層。 =發明之—實施例中，钱種子層為化學銅層。 之—實施例中’於第—表面、第二表 開孔之内虹形料電狀後更包括下 7 200901417 0611002 22553twf.doc/n 開孔中填充-絕緣㈣。接著，移除第—表面、第二 上以及開孔外侧之導電層。夕 面 與第二表面共平面。 後’使絕緣材料與第一表面 声之ί本f明:斤製作出之線路板申，線路層是内埋於介電 與第二表面’且線路層之外側表面與第-； 面以及苐—表面解面，轉/ =壁’以電性連接位於介電層兩二 Ο =技術’本發a綺製作出之之_式線純純平整之^ 内埋於介，之笛#此外’由於上述線路層係 二，層之線路’寬；===== 本二即線闕之線路寬度能符合細線路之規格。換十之， 本發明能製作出品質較佳之細祕板。 、。 為讓本發明之上述和其他目的、特徵和優點能更明顯 明如下y文跡較佳實補，並配合所_式，作詳細說 【實施方式】 埋圖2繪示為本發明較佳實施例之一種具有導電孔之内 =線路板的製作流程圖。請參考圖2，本實施例之 内埃^板製程包括下列步驟：首先，執行步驟S1，提供一 切2路基板。接著，執行步驟S2，於㈣式線路基板 7战—開孔。然後，執行步驟S3，於内埋式線路基板之 8 200901417 0611002 22553twf.doc/n 第一表面、第二表面以及開孔内壁上形成一導電層。之後， 執行步驟S4，移除第一表面、第二表面上以及開孔外側之 導電層，以形成一導電孔。下文令，本實施例將以詳細之 流程剖面圖來說明上述之線路板製程。 圖3A至3E繪示為圖2之具有導電孔之内埋式線路板 的製程剖面圖。此内埋式線路板的製作方法如下所述：首 先，如圖3A所示，提供一内埋式線路基板21〇，其包括一 介電層212、一第一線路層214以及一第二線路層216。其 中"電層212具有相對應之一第一表面2i2a與一·第二表 面212b，而第一線路層214是内埋於第一表面212a，且第 一線路層214之外侧表面與第一表面212a共平面。此外， 第二線路層216是内埋於第二表面212b，且第二線路層216 之外側表面與第二表面212b共平面。接著，如圖3B所示， 於内埋式線路基板210上形成一開孔220。舉例來說，開 孔220可以是一通孔（through hole)或是一盲孔（blind via)圖3B繪示之開孔22〇係以通孔為例，而形成開孔 G 220之方式可以是機械鑽孔、雷射燒孔或是其他適當之方 式。 於内埋式線路基板210上形成開孔220之後，接著如 圖3C至圖3D所示，於第一表面212a、第二表面212b以 1開^ 220之内壁上形成一導電層23〇。在本實施例中， ^成；，層230例如是包括下列步驟：首先，如圖3C所 =於第一表面212a、第二表面212b以及開孔220之内 壁上形成一電鍍種子層232。其中，電鍍種子層232例如 200901417 0611002 22553twf.d〇c/n 是利用化學銅製程而形成於第一表面212a、第二表面212b 以及開孔220内壁上之化學銅層。接著，如圖3D所示， 於電鍍種子層232上形成一電鍍層234。電鍍層234例如 是藉由電鍍製程而形成之一電鑛銅層，而本實施例之導電 層230即包括電鍍種子層232以及形成於電鍍種子層232 上之電鍍層234。 Ο ο 於第一表面212a、第二表面212b以及開孔220内壁 上形成導電層230之後’接者如圖3E所示，移除第—表 面212a、弟一表面212b上以及開孔220外側之導電声 230。舉例來說，本實施例可以利用機械研磨或是化學研^ 等適當方式來移除第一表面212a、第二表面212b上以^ 開孔220外側之導電層230。在執行圖3E之步驟後，導電 層23^僅配設於開孔22〇内壁，且分佈於第一線路層2 = 以及第二線路層216之側面，以電性連接第一線路層214 與第二線路層216。如此-來’内埋式線路板扇^星 一電性連接第-線路層214與第二線路層216 ς 240。此外，本實施例可以有效地改善 = =問職路板之表面不平整是由導電 甏性所導致）。換言之，本實施例之 又 即具有較佳之表面平整度。 内埋式線路板200 此外，為防止外界環境之水氣進入開孔现中， 2花效應（P〇pcornEffect)。在另„較佳實_:，= =212a、第二表面212b以及開孔220之内壁上= Μ層230(如圖犯所示）之後可以於開孔咖 = 10 200901417 \JSJ I 1 \J\JZ. ^.2553twf. doc/n 如是油墨的絕緣材料2 5 〇 (如圖4 A所示），以防止爆米花六文 應劣化内埋式線路板。當然，於開孔顶中填充絕緣材料 250之後，本實蝴雜可彻機械研㈣是其他適 方式來移除第-表面212a、第二表面而上、開孔田 外側之導電層230以及部份位於開孔22()外側之絕 250㈣4B所示），以使填充於開孔22〇之絕緣材料= ”第一表面212a與第二表面212b共平面。換言之，本告In order to achieve the above or other purposes, the present invention provides a buried circuit board process having conductive vias, which includes the following steps: First, providing a buried circuit substrate 'which includes a dielectric layer, a first circuit layer And a first: circuit layer: wherein the dielectric layer has a corresponding one - the first surface and a first surface 帛, the circuit layer is buried in the first surface, the outer surface of the circuit layer, the first surface coplanar And the second circuit layer is buried in the second surface 2 and the outer side surface of the second circuit layer is coplanar with the second surface. Then, the inner hole is formed on the circuit substrate. Then, on the first surface, the surface? And forming a conductive layer on the inner wall of the opening. After that, remove the ^. And the conductive layer on the surface of the second surface and the outer side of the opening to form a conductive layer in the first embodiment, the first surface, the second surface and the second conductive layer comprise the following steps: First, at =, The second surface and the inner wall of the opening form - the electric money seeder's formed on the electroplated seed layer - the electric money layer, and the conductive layer comprises a plating layer and a plating seed layer. = Invented - In the embodiment, the money seed layer is a chemical copper layer. In the embodiment, after the i-shaped surface and the second surface of the opening, the rainbow-shaped electric material further includes the following 7 200901417 0611002 22553twf.doc/n filling-insulation (4) in the opening. Next, the conductive layers on the first surface, the second upper surface, and the outer side of the opening are removed. The evening surface is coplanar with the second surface. After the 'insulation material and the first surface of the sound of the f: the production of the circuit board, the circuit layer is buried in the dielectric and the second surface 'and the outer surface of the circuit layer and the -; surface and 苐- surface solution, turn / = wall 'electrically connected to the dielectric layer two or two Ο = technology 'this hair a 绮 produced by the _ line pure and flat ^ buried in the media, the flute #又' Since the above line layer is two, the line of the layer is 'wide'; ===== The line width of the second line is in line with the specification of the thin line. In the tenth, the present invention can produce a fine board with better quality. ,. The above and other objects, features and advantages of the present invention will become more apparent from the following description. A flow chart of making a circuit board with a conductive hole. Referring to FIG. 2, the internal board process of the embodiment includes the following steps: First, step S1 is performed to provide a 2-way substrate. Next, step S2 is performed to make a hole in the (4) type circuit substrate. Then, step S3 is performed to form a conductive layer on the buried surface substrate 8 200901417 0611002 22553 twf.doc/n first surface, second surface, and inner wall of the opening. Thereafter, step S4 is performed to remove the conductive layer on the first surface, the second surface, and the outside of the opening to form a conductive hole. Hereinafter, the present embodiment will explain the above-described circuit board process in a detailed process sectional view. 3A to 3E are cross-sectional views showing the process of the buried wiring board having the conductive holes of Fig. 2. The method for fabricating the buried circuit board is as follows: First, as shown in FIG. 3A, a buried circuit substrate 21 is provided, which includes a dielectric layer 212, a first circuit layer 214, and a second line. Layer 216. Wherein the electric layer 212 has a corresponding one of the first surface 2i2a and the second surface 212b, and the first circuit layer 214 is embedded in the first surface 212a, and the outer surface of the first circuit layer 214 is first Surface 212a is coplanar. In addition, the second circuit layer 216 is buried in the second surface 212b, and the outer surface of the second wiring layer 216 is coplanar with the second surface 212b. Next, as shown in FIG. 3B, an opening 220 is formed in the buried circuit substrate 210. For example, the opening 220 may be a through hole or a blind via. The opening 22 shown in FIG. 3B is a through hole. The manner of forming the opening G 220 may be Mechanical drilling, laser burning, or other suitable means. After the opening 220 is formed in the buried circuit substrate 210, a conductive layer 23 is formed on the inner surface of the first surface 212a and the second surface 212b by the opening 220 as shown in FIG. 3C to FIG. 3D. In the present embodiment, the layer 230 includes, for example, the following steps: First, a plating seed layer 232 is formed on the inner walls of the first surface 212a, the second surface 212b, and the opening 220 as shown in FIG. 3C. The electroplated seed layer 232, for example, 200901417 0611002 22553 twf.d〇c/n, is a chemical copper layer formed on the first surface 212a, the second surface 212b, and the inner wall of the opening 220 by a chemical copper process. Next, as shown in FIG. 3D, a plating layer 234 is formed on the plating seed layer 232. The plating layer 234 is formed, for example, by an electroplating process, and the conductive layer 230 of the present embodiment includes a plating seed layer 232 and a plating layer 234 formed on the plating seed layer 232. ο ο After forming the conductive layer 230 on the first surface 212a, the second surface 212b, and the inner wall of the opening 220, the connector is removed as shown in FIG. 3E, and the first surface 212a, the second surface 212b, and the outer side of the opening 220 are removed. Conductive sound 230. For example, in this embodiment, the conductive layer 230 on the first surface 212a and the second surface 212b to be outside the opening 220 may be removed by a suitable method such as mechanical polishing or chemical polishing. After the step of FIG. 3E is performed, the conductive layer 23 is disposed only on the inner wall of the opening 22 and distributed on the side of the first circuit layer 2 and the second circuit layer 216 to electrically connect the first circuit layer 214 with The second circuit layer 216. Thus, the 'internal circuit board fan' is electrically connected to the first line layer 214 and the second line layer 216 ς 240. In addition, this embodiment can be effectively improved = = the surface irregularity of the service board is caused by the conductivity of the conductive). In other words, this embodiment has a better surface flatness. Buried circuit board 200 In addition, in order to prevent the external environment from entering the opening, the water effect (P〇pcornEffect). On the other side of the better _:, = = 212a, the second surface 212b and the inner wall of the opening 220 = Μ layer 230 (as shown in the figure) can be opened in the hole = 10 200901417 \JSJ I 1 \J \JZ. ^.2553twf. doc/n If the insulating material of the ink is 2 5 〇 (as shown in Figure 4 A), to prevent the popcorn six should degrade the buried circuit board. Of course, fill the insulation in the top of the opening. After the material 250, the actual mechanical modification (4) is another suitable way to remove the first surface 212a, the second surface, the conductive layer 230 outside the open field, and a portion located outside the opening 22 () Absolutely 250 (four) 4B) so that the insulating material filled in the opening 22 = = "the first surface 212a is coplanar with the second surface 212b. In other words, this statement
O o 板·，除了有較佳之表面平整度之外只 本貝施例亦钟效地防止爆米花效應劣化内埋式 亦即，f實關之_式祕板，有較狀結構 綜上所述’本發明是於一内埋式線路基板 又道 H ’以電性連接介電層兩侧之線路層 、 本發明之岐魏路财下冊點： •知技咖’ 介t 明之㈣式祕板魏路層係内㈣ 門有二“及第—表面，因此線路層與介電芦之 7有g之接合性質。換言之，本發明 :層之 線路層具有較佳之可靠度。 里式線路板其 (二）由於本發明之線路層是内埋於介電声 發Γΐ製作具有導電孔之内埋式線路板時，此^ 到4程所應用之軸彳液作用而影響之=不易雙 線路層之線路寬騎能符合細線路之規格:2路寬度， 明所製作出之_式線路板為具有較佳品質之本發 —(二）在本翻巾，祕層是岐於介路板。 與第二表面，且線路層之外側表面與第—表 11 η ο 200901417 0611002 22553twf.doc/n 由共平面。此外’電性連接介雷 導電…埋心 整之表面。因二在後;埋式線路板有較平 有較平1之2二此=片明之内埋式線路板 片與内埋錢路板之^=====晶 i可=片翻埋搞路_構成之^封裝結構有^ 限定=、ΐ發明已喻佳實_減如上，並非用以 =當此技藝者，在不脫離本發二 範圍冬視德心由—許之更動與潤#，因此本發明之保護 【圖;簡單說明】利範圍所界定者為準。 面圖圖1Α至圖1F|f示為f知之—種線路板製程的流程剖 埴式線 =;=:佳實施例之-種具有導電孔之内 的製示為圖2之具有導電孔之内埋式線路板 電孔本發贼佳實闕種具有導 円埋式線路板的部分製程剖面圖。 12 200901417 0611002 22553twf.doc/n 【主要元件符號說明】 100 ··線路板 110 :基板 112 :介電層 114 :銅箔層 114’ ：圖案化銅箔層 120 :通孔 130 :導電層 130’ ：圖案化導電層 140 :圖案化光阻層 150 :圖案化線路層 200、200’ ：内埋式線路板 210 :内埋式線路基板 212 :介電層 212a :第一表面 212b :第二表面 214 :第一線路層 216 :第二線路層 220 :開孔 230 :導電層 232 :電鍍種子層 234 :電鍍層 240 :導電孔 250 :絕緣材料 S1〜S4 :各個步驟 c 13O o board · In addition to the better surface flatness, only the Benbe example can effectively prevent the popcorn effect from degrading the embedded type, that is, the _ _ _ _ _ _ _ _ _ _ _ _ _ _ The invention is based on a buried circuit substrate and H' to electrically connect the circuit layers on both sides of the dielectric layer, and the present invention is in the form of a 岐 路 : : : : : : : : • • • • • • • • • • 知 知 知 知 知 四 四 四In the Weilu layer system (4), the door has two "and the first surface, so the circuit layer and the dielectric reed 7 have the bonding property of g. In other words, the present invention: the circuit layer of the layer has better reliability. (2) Since the circuit layer of the present invention is embedded in a dielectric acoustic hair to produce an internal buried circuit board having conductive holes, the influence of the shaft sputum applied to the four passes is affected by the difficulty of the double circuit layer. The line wide ride can meet the specifications of the fine line: 2 way width, the _ type circuit board produced by Ming is the best quality of the hair - (2) in this sneaker, the secret layer is smashed on the interface board. With the second surface, and the outer surface of the circuit layer is the same as the first table 11 η ο 200901417 0611002 22553twf.doc/n Coplanar. In addition, 'electrical connection Jie Lei conductive... buried the entire surface. Because the second is behind; buried circuit board has a flat and flat 1 2 2 = the buried buried circuit board and buried ^路========================================================================================================== The scope of the second issue of the winter vision is - Xu Zhijian and Run #, so the protection of the present invention [figure; simple description] is defined by the scope of interest. The surface diagram of Figure 1Α to Figure 1F|f The process of the circuit board process is 埴 线 ============================================================================================== Partial process cross-section of the buried circuit board. 12 200901417 0611002 22553twf.doc/n [Description of main component symbols] 100 · · Circuit board 110 : Substrate 112 : Dielectric layer 114 : Copper foil layer 114 ' : Patterned copper foil Layer 120: via 130: conductive layer 130': patterned conductive layer 140: patterned photoresist layer 150: patterned circuit layer 200, 2 00': buried circuit board 210: buried circuit substrate 212: dielectric layer 212a: first surface 212b: second surface 214: first circuit layer 216: second circuit layer 220: opening 230: conductive layer 232: plating seed layer 234: plating layer 240: conductive hole 250: insulating material S1 to S4: each step c 13