1354356 九、發明說明： 【發明所屬之技術領域】 ’尤指一種無 本發明係有關於-種封裝基板及其製法 核心基板之多層封裝基板及其製法。 【先前技術】 為提尚半導體晶片封裝用之其此^ ώ WAP山 我用之基板之佈線精密度，業界 逆發展出一種增層技術（β ild (r u 、 U1id up)，亦即在一核心基板1354356 IX. Description of the invention: [Technical field to which the invention pertains] ‘especially, a multi-layer package substrate having a package substrate and a method for manufacturing the same, and a method for fabricating the same. [Prior Art] In order to improve the wiring precision of the substrate used in semiconductor chip packaging, the industry has developed a layer-adding technology (β ild (ru, U1id up), that is, in a core Substrate
Hore board)表面利用線路辦屏姑丄 層技術父互堆疊多層介電 層及線路層，並於該介電層中 丨包智T開叹導電盲孔（Conductive via)以供上下層線路之間電性 〇 r生運接，其中，該線路增層製 程係影響基板線路密度的關鍵。 請參閱第係為習知增層基板之製法。首 先，如第1A圖所示，提供一例如銅箔基板（c_er⑽㈣ laminated，CCL)之具金屬薄層1〇1之絕緣層1〇〇，並於 其中鑽設有複數個通孔102。如第1B圖所示，再經過鍍 籲銅以於該金屬薄層101之表面及於該通孔1〇2之孔壁上形 成有金屬層103 ;如第ic圖所示，復填充一導電或不導 電之塞孔材料11 (如絕緣性油墨或含銅導電膏等）以填滿 該通孔102殘留空隙，俾形成一電鍍導通孔（pTH)1〇2a以 電性導通該絕緣層100上下表面之金屬層1〇3 ;如第1D 圖所示’之後以刷磨製程去除多餘塞孔材料U，以維持 核心基板線路表面之平整度；如第1E圖所示，最後再將 該絕緣層100兩面之金屬薄層1〇1及金屬層1〇3進行圖案 化製私’藉以構成一具雙面之内層線路層1 04的核心基板 5 110717 1354356 10結構。 之後’如第IF圖所示’於該核心基板1〇上下表面之 内層線路層104上形成一介電層i 2，利用雷射鑽孔（Laser drUHng)技術於該介電層12上形成複數開孔12〇 ;接 .·著’如f 1G圖所示，於該介電層12及開孔12〇表面以無 \電解電鍍銅方式形成一導電層13,在該導電層13上施加 一阻層14’並形成有外露出部分導電層13之開口後進行 電鍍製程，以於該導電層13表面形成線路層15。之後， •如第1H圖所#，去除該阻層14並進行㈣，以移除先前 覆蓋於阻層14下之導電層13。如此，運用料流程重複 形成介電層及線路層，即製成一具多層線路之基板。 惟，上述之具多層線路之基板製程中，係採用表面包 覆有金屬薄層之絕緣層結構作爲芯層（c〇re)，並於該芯 f上進行線路製程以形成一核心基板，核心基板於製程中 f 了塞孔及刷磨製程，會增加基板製造步驟。尤其重要的 #是’核心基板中形成有多數電鍍導通孔⑽），而一般電 ，導通孔⑽）之孔徑係約在1〇〇㈣以上，相對地，導電 =之孔徑約在5Mm左右，且可以電鑛線路方式形成， =此’比較而言該電鐘導通孔之結構佔用過大佈線空間， 而不利於細線路結構之形成。 ，上4之多層封裝基板製程中，需先製備-核心 :: 反’接著再於該核心基板上形成介電層及線路層， ::成’此技術具有佈線密度低，層數多，導線長且阻 〇、問題，對於向頻基板較難應用。又因疊層數多，其 ]]07]7 6 1354356 製程步驟也較複雜。 ： 因此，如何提供一種多層封租夷杯月甘# •習知技術中佈線密度低，芦|< 土 及”衣法，以避免 步驟複雜的問題，實已成爲目 阻抗向及製程 k【發明内容】 ’、| 克服之難題。Hore board) The surface layer of the screen is used to stack multiple layers of dielectric layers and circuit layers, and in the dielectric layer, 丨 智 T 开 导电 导电 导电 Con Con Con Con Con Con Con Con Con Con Con Con Con Con Con Con Con Con The electrical 〇r is transported, wherein the line build-up process is the key to affecting the substrate line density. Please refer to the system for making the substrate. First, as shown in Fig. 1A, an insulating layer 1 of a thin metal layer 1 〇1 of a copper foil substrate (c_er (10) (4) laminated, CCL) is provided, and a plurality of through holes 102 are drilled therein. As shown in FIG. 1B, a copper layer is further plated to form a metal layer 103 on the surface of the metal thin layer 101 and the hole wall of the through hole 1〇2; as shown in FIG. Or a non-conductive plug material 11 (such as an insulating ink or a copper-containing conductive paste, etc.) to fill the gaps in the via hole 102, and form a plating via (pTH) 1〇2a to electrically conduct the insulating layer 100. The metal layer of the upper and lower surfaces is 1〇3; as shown in FIG. 1D, the excess plug material U is removed by a brushing process to maintain the flatness of the core substrate line surface; as shown in FIG. 1E, the insulation is finally performed. The metal thin layer 1〇1 and the metal layer 1〇3 on both sides of the layer 100 are patterned to form a core substrate 5 110717 1354356 10 structure having a double-sided inner layer circuit layer 104. Then, as shown in FIG. IF, a dielectric layer i 2 is formed on the inner wiring layer 104 of the upper and lower surfaces of the core substrate, and a plurality of dielectric layers 12 are formed on the dielectric layer 12 by laser drilling (Laser drUHng) technology. a conductive layer 13 is formed on the surface of the dielectric layer 12 and the opening 12 by electroless plating, and a conductive layer 13 is applied on the conductive layer 13 as shown in FIG. The resist layer 14' is formed with an opening exposing a portion of the conductive layer 13 and then subjected to an electroplating process to form a wiring layer 15 on the surface of the conductive layer 13. Thereafter, as in FIG. 1H, the resist layer 14 is removed and (4) is removed to remove the conductive layer 13 previously covered under the resist layer 14. In this way, the dielectric layer and the circuit layer are repeatedly formed by using a material flow, that is, a substrate having a multilayer circuit is formed. However, in the above-mentioned substrate process with a multilayer circuit, an insulating layer structure having a thin metal layer is used as a core layer, and a wiring process is performed on the core f to form a core substrate. The substrate has a plug hole and a brushing process during the process, which increases the substrate manufacturing steps. Especially important is that 'the core substrate is formed with a plurality of plated vias (10)), while the general electrical, via (10) has a pore size of about 1 〇〇 (four) or more, and relatively, the conductivity = the aperture is about 5 Mm, and It can be formed by electric ore line method. = This is comparatively speaking, the structure of the conduction hole of the electric clock occupies excessive wiring space, which is not conducive to the formation of a fine line structure. In the process of the multi-layer package substrate of the above 4, it is necessary to prepare - core:: reverse 'and then form a dielectric layer and a circuit layer on the core substrate, :: into ' this technology has a low wiring density, a large number of layers, wires Long and obstructive, problem, difficult to apply to the frequency substrate. Due to the large number of stacks, the process steps of ]]07]7 6 1354356 are also complicated. : Therefore, how to provide a multi-layer seal rental Yi Cup Yue Gan # • The low-density wiring in the conventional technology, the reed | soil and "clothing method to avoid the complexity of the steps, has become the objective impedance and process k [ SUMMARY OF THE INVENTION ',| Overcome the problem.
： 鑒於上述習知技術之缺點，太恭n H ，供一種能形成細線路結構之多層封目的在於提 本笋明n AA^ 了裝基板及其製法。 丰心月之另一目的在於提供_ •封裝基板及其製法。 此間化衣程之多層 為達上述目的及其他目的， 基板，係包括1入W —種多層封裝 于匕括.第-介電層’係具有第一導電盲 表面及相對該第一表面坌_ 孔弟一 Α 衣甶之弟一表面，且該第一導雷亡：?丨Μ 該第二表面;第一線路層，係設於該第：介電 二亥第二续致增層結構’係設於該第一介電層之第-表面 二導命亡，層上，並形成有電性連接該第一線路層之第 一 毛目孔；第一防焊層，係設於該第一介電芦 導電盲孔上，且該第-防焊層具有 *二Μ弟一導電盲孔的底部外露於該第一開孔中，俾作為 2電性接觸整；以及第一導電層’係設於該第一線路層 第介電層之第一表面之間及該第一導電盲孔與該 介電層之間’而未覆蓋第一導電盲孔的底部。 ^ 依上述結構，復包括有例如為鈦/銅（Ti/Cu)之第一導 ^ %。又於泫第一線路層與該第一表面之間、及該第一 ‘電盲孔與該第一介電層之間。該第一介電層係為感光高 110717 丄乃4356 分子或熱固型高分子’較佳可為具芳香基的石夕氧高分子 其分子式係例如為： ^Η3 CH3 一 (ΑιΊ-〇—-)m-)n— ch3 ch3 該增層結構包括至少一第二介電層、設於該第二介電 層ΐ之第=線路層、以及設於該第二介電層中並電性連接 j第一及第二線路層之第二導電盲孔，於該增層結構上設 2電性連接該第二線路層之第二電性接觸墊，且於該增層 盍有第二防焊層，該第二防焊層具有第二開孔以 路出該第二電性接觸墊。 依上述結構，復包括於該第一防焊層上及其第一開孔 表面、該第二防焊芦及立黛_ 坪層及/、弟一開孔表面形成導電凸塊 :Electroplatings〇lder)，該導電凸塊係為錫、船、 ^、錄、絡1等金屬所組成之群組之—者，且分 連接該第一及第二電性接觸墊。 本發明復揭示一種多尽# 種夕層封裴基板之製法，係包括：提 供一承载板，於其至少一 #而π Λ、θ丄 V表面形成具有相對之第一及第二 表面之第一介電層，JL中哕筐入平a # 亥第一介電層之第二表面係接觸 .^ 4 ;丨电層中形成介電層開孔，以露出該 承載板之部份表面；於該第一兩 七墙 ^ 示；丨包層上及介電層開孔中形 成第一導電層；於該第一導電 I - Μ ^ ^ ^ 命冤層上形成弟一阻層，並於該 第阻層中形成有第一開口區 部分第—導# # β > a 路Θ弟”甩層上的 ^層及该介電層開孔中的第一導電層;於該第 Π0717 8 1354356 一開口區中形成第一線路声， 一導雨亡θ亚於该介電層開孔中形成第 〜孔，移除該第—阻層：弟 於該第-介電層及該第一線路層上形成增二導;層’· 第二表面及該第一導二露出該第-介電層之 之第二表面及第—導電盲孔上开 =第以一及於曰該第一介電層 防焊層中形成第 / ' 1焊層’且該第- 於該第-開孔，，俾:為;供=一導電盲孔 ^ 作為弟一電性接觸墊。 該承载板係為金屬板 (Ti/Cu)。 忒弟一導電層係為鈦/銅 本發明復揭示一種吝爲44壯#， 供一承載板，其至少—表面；/基板之製法，係包括··提 介電層上形成輔助導:/、有輔助介電層；於該辅助 屬^於该金屬層上形成具有相對 =成金 二電：’該第—介電層以第二 该第一介電層中彡 W啊必孟屬層，且於 # ^ 中形成介電層開孔，以露出該全 表面;於該第一介電 ：/金屬層之部份 第—導電厚.於兮法 表面上及介電層開孔中形成 一阻層令形成有第一開口區，以露出\第_^/於該第 分第—導電層及該介電芦 / "电層上的部 開口區中形成第一線路： ' 的第一導電層;於該第-導電盲孔；移㈣帛二亚於該介電層開孔中形成第- 該第—介電層1;第:層及其所覆蓋之第—導電層;於 載板、金屬層、辅助導^路層上形成增層結構；移除該承 補助Μ層、及輔助介電層，以露出該第 】】07】7 9 1354356 ;丨迅層之第二表面及第一導電盲孔的底部；以及於該 第”包層之第二表面及第一導電盲孔上形成第一防焊 層，且該第一防焊層中形成第一開孔，以供該第一導電盲 孔的底部外露於該第一開孔中，俾作為第一電性接觸勢。 該承載板係為絕緣板；該第一導電層係為鈦/銅 (Ti/Cu)。 該第-介電層可為具芳香基的石夕氧高分子，其係與金 屬承載板接合性不佳，@ m^ ^ 低“t个1土❿叮使心—介電層直接剝除該承 载板，再斂蝕去除該承載板所覆蓋的導電層，i 介電層之分子式係例如為： ?H3 ch3 — (ΑΓ-(S丨卜0 十)m-)n— CH3 CHs 。 電声上心：:：括至少一第二介電層、形成於該第二介 連‘該以及形成於該第二介電層中並電性 上形成電性連接該第二線路層之；：= 於該增層結構 增層結構及第二電性接觸塾上覆蓋0接觸塾，且於該 防谭層並形成第二開孔以露出;防焊層’該第二 依上述製法’復包括於該苐一防：：接觸墊。 表面、該第二防焊層及1第 h上及其第-開孔 该導笔凸塊分別電性連接該第一導电凸塊，且 综上所述，本發明之多声 ^生接觸墊。 於承载板上先形成第一介電m及其製法，主要係 曰及弟—線路層，再於該第一 Π0717 】0 1354356 ••介電層及第-線路層上形成增層結構，之後移除該承載板 以露出形成於該第一介電層中之第一導電盲孔，然後於該 .第-介電層及外露之第一導電盲孔上形成第一防焊層，及 .在該增層結構上形成第二防焊層，俾以形成無核心基板之 ••多層封裝基板’俾可提高佈線密度，另由於本發明係益核 .‘心基板及免製作電鍍導通孔，進而能簡化製程 線路結構。 又’本發0月藉由第—介電層與金屬承載板接合性不 么而可使第介電層直接剝除該承載板，而習用的介命 層材料與金屬承载板大都無法直接剝除，通常僅能藉由^ 刻金屬承载板’以分離介電層材料與金屬承載板， 則可以避免㈣金屬承载板的繁複步驟及耗費時間，進而 提高製程效率。 延而 再者，藉由第一防焊層具有第一開孔以露出該第 電盲孔的底部，並以第一導電盲孔的底部作為第一電 鲁接墊，而達成細間距的效果。 【實施方式】 以下係藉由特定的具體實例說明本發明之實施 熟悉此技藝之人士可由本說明書所揭示之内容輕 瞭解本發明之其他優點與功效。 也 [第一實施例] 請蒼閱第2A至2J圖，係為本發明之多層封裝基板制 法之剖面示意圖。 衣 如第2A圖所示’提供一係為金屬板之承載板2〇，其 Π〇7]7 11 1354356 至少-表面形成具有相對之第—表面da 之第一介電層21，且該M入年贷 表面21b 且落弟一介電層21之第二 接觸該承載板20，並於兮μ 上γ落弟一介電層21中形 層開孔別，以露出該承载板2〇之部份表面。 1 軾井層21_係為感光高分子或熱固型高分子， 較么為/、方曰基的矽氧高分子，其分子式係例 ch3 ch3 一 (Ar_(S|i-〇十)m-)n— ch3 ch3 ο 如第2B圖所示，接著，於該第一介電層 層開孔210表面形成第一導恭 ；，^ rT./r ,而㈣ 泠电層22,其較佳材質為鈦/鋼 (广），而與弟一介電層21有較佳接合性 續的電鍍品質；接著’於該第一導電層22 二灸 層23，並於該第一阻層23中 + ^ 且 曰以中形成複數第一開口區23〇， 以露出第-介電層21上的部份第一導電 開孔210中之第一導電層22。 ^丨电層 如第2C圖所示，於該第-開口區230中之第一導雷 層22上形成第一線路層24， 斧电 並於該介電層開孔210之第 一導電層22上形成第一導電盲孔241。 如第2D圖所示，移除該第一 一導電層22。 層23及其所覆蓋之第 ，如第2E圖所示，於該第一介電層2ι第一表面⑴ 及第一線路層24上形成增居纟士嫉 ^ ^ ^ 曰、、，。構25，該增層結構25包 、一第二介電層251、形成於該第二介電層251上之 110717 12 1354356 層252、以及複數形成於該第二介電層 •电性連接該第—及第二線路層24,252之第二導電盲孔 2$且於該增層結構25上形成有複數電性連接該= 路層252之第二電性接觸墊254。 如第2F圖所示，移除該承載板2〇及其所覆望 =電㈣’進而露出該第一導電盲孔241的底：上 &瓜使用的介電層中’因其與金屬承載板的接 .故右用以接合金屬承載板，將於移除金屬承载板之 :程中’需使用蝕刻技術以完全移除金屬承載板，不僅容 ^银刻過度而破壞内部線路，且關之製程步驟繁複及 費，。有鏗於此，於所述之製法中，該第一介電層 具芳香基的矽氧高分子材質’其係與金屬材質之:柘 20接合性不佳，而可使該第一介電層2ι直 ^ 板2〇,再微韻移除該承載板2〇所覆蓋的第—導電 及第SI?所示，於該第一介電層21之第二表面训 及第一導电盲孔241的底部241〇上形成第一 %’且該第-防焊層27a中形成有第—開孔⑽以露^ 第一導電盲孔241的底部2410，使該第-導電盲孔241 的底部2410外露於第一開孔、之表面作為第 觸墊仏’又於增層結構25上形成第二防焊層27b，該第 層饥並形成第二開孔27。,以露出第二電性接觸 如第2H圖所示’接著’於該第—防桿層^上及1 第-開孔隱中、第二防焊層27b及其第二開孔㈣ 110717 13 1354356 .中形成例如為鈦/銅（T i / Cu )之第二導電層2 81 ;再於該 :第二導電層281上形成第二阻層282,並於該第二阻層282 中形成I數第二開口區2820，以露出該些第一開孔27〇a 及第二開孔270b。 如第21圖所示，於該第二開口區282〇中之第二導電 層281上升少成^電凸塊（Μ ) 28， 其係為錫、錯、銅、鎳、絡、鈦等金屬所組成之群組之一 者’且分別電性連接該第一電性接觸墊2栳及 ♦觸墊254。 # 如第2J圖所示，移除該第二阻層282及其所覆罢 第二導電層281。 孤义 [第二實施例] 請參閱第3A至31圖’本實施例與第—實施例之 在於該承載板係為絕緣板。 走異 =提供—係為絕緣板之承載板2〇, 八^一表面具有輔助介電層31;接著，於該輔助八 =面形成一輔助導電層32;之後，於.該輔2 二=…系為銅之金屬層33。該辅助導電 仏例如為鈦/銅（Ti/cu)。 ^•嘈32 如第3B圖所示，於該金屬層33上形成具有 ★ 人:面21a、及第二表面21b之第—介電層u，且=第 ”电層21以第二表面21b接觸該金屬層扣、，〜 介電層21中形成複數介電層開孔210, _ :於該第〜 33之部份表面。其中 ：出該金屬層 冤層21係為感光高分子 H0717 14 1354356 .或熱固型南分子，較佳為具芳香基的矽氧高分子，其分子 *· 式係例如為： . ch3 ch3 -(Ar-(Si-〇>Si-)m-)- • CH3 ch3 。 如第3C圖所示’於該第一介電層21及介電層開孔 210上形成例如為鈦/銅（了丨/。）的第一導電層22;接 著’於該第一導電層22上形成第—阻層23，並形成複數 第開口區230，以露出該第一介電層21上之部分第一 導電層22及該介電層開孔21〇中的第一導電層22。 如第3D圖所示，於該第—開口㊣23〇中及第一介電 層表面之第一導電層22上形成第一線路層24，並於 該第一介電層21及介電層開孔21〇之第一導電層22上形 成第一導電盲孔241。 如第3E圖所示，再移除該第一阻層23及其所覆蓋之 第導電層22’以露出該第一線路層24。 如第3F圖所示，於該第一介電層。及該第一線路層 24上形成係如第2E圖所述之增層結構25。 如第3G圖所示，移除該承載板2〇，、輔助介電層3卜 輔助導電層32、金屬層33、及為金屬 =電層22，以露出該第-介電層21之第二表面2 =該 第一導電盲孔241的底部2410。 如第3H圖所示，於該第一介電層21之第二表面⑽ 及第-導電盲礼241上形成有第一防焊層27a，且該第一 110717 15 1354356 ·.防焊層27a中形成有第一開孔27〇3以露出該第—導電盲 )孔如的底部剛，使該第一導電盲孔如的底部編 •外露於第-開孔270a之表面作為第一電性接觸塾池； 又於*亥增層結構25上形成有第二防焊層饥，該第二防 焊層27b並形成有第二開孔2雇以露出該第二電 墊 254。 如第31圖所示，於第一防焊層27a上及其第一開孔 270a表面、第二防焊層2?b及其第二開孔27牝表面形成 •係如第2 J圖所述之導電凸塊28。 本發明復揭示一種多層封裝基板，係包括：第一介電 =1’係具有第一導電盲孔241、第一表自⑴及相對該 表面21a之第一表面2lb，且該第一導電盲孔241的 ，部2410外露於第二表面21b;第一線路層24，係設於 j第-介電層21第—表面21a ;增層結構25，係設於該 ,丨电層21之第一表面213及該第一線路層24上，並 % 成有複數電性連接該第一線路層24之第二導電盲孔 2M;第一防焊層27a，係設於第一介電層21第二表面21匕 j第“導電盲孔241上，且具有第一開孔27〇a ,以供第 導電目孔241的底部2410外露於該第一開孔27〇a中， =作為第一電性接觸墊24a;以及第一導電層22，係設於 第線路層24與第一介電層21之第一表面2ia之間、及 導電s孔241與第一介電層21之間，而未覆蓋第一 笔a孔241的底部241 〇。 依上述結構，復包括有例如為鈦/銅（Ti/Cu)之第一導 16 ]]0717 1354356 電層22，係設於該第一線路層24與該第一表面2比之 間、及該第-導電盲孔241與該第一介電層21之間。 、依上述結構，該第一介電㉟21 4具芳香基的石夕氧 为子’其分子式為： CH3 CH3 —(Ar-(S丨卜 ch3 ch3 •第二：=結構，包括至少一第二介電層25卜設於該 一）丨书a上之第二線路層252、以及複數設於該第二介 電=中並電性連接該第一及第二線路層24 252之第二導 電盲孔253 ’於該增層結構25上設有複數電性連接該第 -線，層252之第二電性接觸塾脱，另於該增層結構25 上覆蓋有第二防焊層27b，且該第二防焊層27b具有第二 開孔270b以露出該第二電性接觸塾⑽。 依上述結構，於第一防焊層27a上及其第一開孔27〇a •表面、第二防谭層27b及其第二開孔27〇b表面 電凸塊28,該導電凸塊28分別電性連接該第一電性接觸 塾24a及苐一電性接觸塾254。 因此，本發明之多層封裝基板及其製法，主要係於承 載板上先形成第-介電層及第一線路層，再於該第一介電 層及第一線路層上形成增層結構，之後移除該承載板以露 出形成於該第一介電層中之第一導電盲孔的底部，缺後於 該外露之第,一導電盲孔及第一介電層上形成第一防焊 層，且在該增層結構上形成第二防焊層，俾形成無核心基 110717 17 1354356 板之夕層封裝基板，俾可提高佈線密度，且由於本發明中 …核〜基板及免製作電料通孔，進而能簡化製程以及形 成細線路結構。 / ★又，錯由第一介電層與金屬承載板接合性不佳，而可 使第”電層直接剝除該承載板，以避免 複步驟及耗㈣間，進而提高製程效率。載板的尔In view of the above-mentioned shortcomings of the prior art, a multi-layered package for forming a fine circuit structure is to provide a substrate and a method for manufacturing the same. Another purpose of Fengxinyue is to provide _ • package substrate and its manufacturing method. The plurality of layers of the coating process are for the above purpose and other purposes, and the substrate comprises a multi-layer package of a plurality of layers. The first dielectric layer has a first conductive blind surface and is opposite to the first surface 坌Confucius Α Α 一 甶 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一The first surface of the first dielectric layer is formed on the first surface of the first dielectric layer, and is formed with a first capillary hole electrically connected to the first circuit layer; the first solder resist layer is disposed on the first a dielectric reed conductive blind hole, and the first solder resist layer has a bottom portion of the second conductive body and a conductive blind hole exposed in the first opening, the germanium is electrically connected as 2; and the first conductive layer is The first conductive layer is disposed between the first surface of the dielectric layer and the first conductive via and the dielectric layer and does not cover the bottom of the first conductive via. ^ According to the above structure, the first derivative of, for example, titanium/copper (Ti/Cu) is included. And between the first circuit layer and the first surface, and between the first 'electric blind via and the first dielectric layer. The first dielectric layer is a photosensitive high 110717 丄 is a 4356 molecule or a thermosetting polymer. Preferably, the molecular formula of the yoke oxygen polymer having an aromatic group is, for example, ^Η3 CH3 (ΑιΊ-〇- -) m-) n - ch3 ch3 The build-up structure includes at least one second dielectric layer, a second circuit layer disposed on the second dielectric layer, and an electrical layer disposed in the second dielectric layer Connecting the second conductive blind vias of the first and second circuit layers of the j, and providing a second electrical contact pad electrically connected to the second circuit layer on the build-up structure, and having a second protection layer on the build-up layer a solder layer, the second solder mask having a second opening to exit the second electrical contact pad. According to the above structure, the first solder resist layer and the first opening surface thereof, the second solder resist and the vertical 黛 ping layer and/or the opening surface of the first hole are formed with conductive bumps: Electroplatings〇lder The conductive bumps are a group of metals such as tin, boat, ^, recording, and network 1, and are connected to the first and second electrical contact pads. The invention discloses a method for manufacturing a multi-layered encapsulating substrate, comprising: providing a carrier plate, wherein at least one of the surfaces of the π Λ and θ 丄 V forms a first and second surface opposite to each other a dielectric layer, the second surface of the first dielectric layer of the JL middle plate is in contact with the second surface of the layer A. The dielectric layer is formed in the germanium layer to expose a part of the surface of the carrier plate; Forming a first conductive layer on the first and second walls; forming a first conductive layer on the cladding layer and the opening of the dielectric layer; forming a resist layer on the first conductive I - Μ ^ ^ ^ Forming, in the first resistive layer, a first open region portion, a first conductive layer, and a first conductive layer in the dielectric layer opening; 1354356 forming a first line sound in an open area, forming a first hole in the opening of the dielectric layer, removing the first resist layer: the first dielectric layer and the first Forming a second conductivity on the circuit layer; the second surface and the first surface of the first dielectric layer exposing the second surface of the first dielectric layer and the first conductive via hole are opened on the first surface and the first conductive layer Forming a / '1 solder layer' in the solder resist layer of the dielectric layer and the first - opening, 俾: is; for = a conductive blind hole ^ as an electrical contact pad. It is a metal plate (Ti/Cu). The conductive layer of the younger brother is titanium/copper. The invention discloses a type of 壮44, which is a carrier plate, at least the surface thereof, and the substrate is made of Forming an auxiliary conductive layer on the dielectric layer: /, having an auxiliary dielectric layer; forming a relative = gold metal on the auxiliary metal layer: 'the first dielectric layer and the second first dielectric layer The middle layer W is a layer of dielectric layer, and a dielectric layer opening is formed in #^ to expose the full surface; the first dielectric: / part of the metal layer is - conductive thick. on the surface of the germanium Forming a resist layer in the opening of the dielectric layer to form a first opening region to expose the opening portion of the first conductive layer and the dielectric resection layer Forming a first line: a first conductive layer; forming a first-first dielectric layer 1 in the opening of the dielectric layer; and forming a first conductive layer; Coverage a layer; forming a build-up structure on the carrier, the metal layer, and the auxiliary conductive layer; removing the supporting layer and the auxiliary dielectric layer to expose the first] 07] 7 9 1354356; a second surface and a bottom of the first conductive via hole; and a first solder resist layer formed on the second surface of the first cladding layer and the first conductive via hole, and the first solder mask is formed in the first solder resist layer The bottom of the first conductive blind via is exposed in the first opening, and the crucible serves as a first electrical contact potential. The carrier plate is an insulating plate; the first conductive layer is titanium/copper (Ti/Cu). The first dielectric layer may be an aromatic ferritic polymer, which is poorly bonded to the metal carrier plate, @m^^ low "t 1 soil ❿叮 direct core-dielectric layer stripping The carrier plate is then etched away to remove the conductive layer covered by the carrier plate. The molecular structure of the i dielectric layer is, for example: ?H3 ch3 — (ΑΓ-(S丨卜0 十) m-)n-CH3 CHs. The upper surface of the sound:: includes at least one second dielectric layer formed in the second dielectric layer and formed in the second dielectric layer and electrically connected to the second circuit layer; Having a 0 contact 塾 on the build-up structure and the second electrical contact 塾, and forming a second opening in the anti-tank layer to expose; the solder resist layer 'the second method according to the above method' In the first protection:: contact pad. The surface, the second solder mask and the first h-th and the first-opening hole of the guide pen bump are electrically connected to the first conductive bump, respectively. The multi-sound contact pad of the present invention is formed on the carrier board by first forming a first dielectric m and a method for manufacturing the same, which is mainly a 曰 弟 弟 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 17 17 17 17 17 17 17 17 Forming a build-up structure on the electrical layer and the first-line layer, and then removing the carrier plate to expose the first conductive blind via formed in the first dielectric layer, and then in the first-dielectric layer and the exposed Forming a first solder resist layer on a conductive via hole, and forming a second solder resist layer on the buildup layer structure to form a multi-layer package substrate without a core substrate, which can increase wiring density, and further, the present invention It is a core substrate and free of electroplated vias, which simplifies the process wiring structure. Also, in the first month, the first dielectric layer can be directly bonded to the metal carrier by the first dielectric layer. The carrier plate is stripped, and the conventional living layer material and the metal carrier plate are mostly not directly stripped. Generally, only the metal carrier plate can be separated to separate the dielectric layer material from the metal carrier plate, thereby avoiding (4) metal. The complicated steps of the carrier board and the time consuming, thereby improving the process efficiency. Further, the first solder resist layer has a first opening to expose the bottom of the first electric blind hole, and the bottom of the first conductive blind hole As the first electric lug pad, and achieved [Embodiment] The following describes the implementation of the present invention by way of specific specific examples. Those skilled in the art can understand the other advantages and effects of the present invention by the contents disclosed in the present specification. [First Embodiment] Please refer to Figures 2A to 2J for a cross-sectional view of the method for manufacturing the multi-layer package substrate of the present invention. As shown in Fig. 2A, the package provides a carrier plate 2 of a metal plate, which is 7] 7 11 1354356 at least the surface forms a first dielectric layer 21 having a first surface-to-surface da, and the M is connected to the surface 21b and the second of the dielectric layer 21 contacts the carrier 20 and is on the 兮μ The γ 落 一 a dielectric layer 21 is formed with a hole in the shape to expose a part of the surface of the carrier plate 2 . 1 The well layer 21_ is a photosensitive polymer or a thermosetting polymer, which is a helium-oxygen polymer of /, and is a molecular formula of ch3 ch3 (Ar_(S|i-〇十)m -) n - ch3 ch3 ο As shown in Fig. 2B, next, a first guide is formed on the surface of the first dielectric layer opening 210, ^ rT. / r, and (d) a tantalum layer 22, which is The preferred material is titanium/steel (wide), and has a better bonding quality with the dielectric layer 21; then the second conductive layer 22 is moxibustion layer 23, and the first resist layer 23 And a plurality of first open regions 23A are formed in the middle to form a first conductive layer 22 in a portion of the first conductive vias 210 on the first dielectric layer 21. As shown in FIG. 2C, a first wiring layer 24 is formed on the first lightning guiding layer 22 in the first opening region 230, and the first conductive layer is electrically connected to the dielectric layer opening 210. A first conductive blind via 241 is formed on 22. The first conductive layer 22 is removed as shown in Fig. 2D. The layer 23 and the layer covered by it, as shown in FIG. 2E, form an enhanced gentleman 嫉 ^ ^ ^ 曰 , , on the first surface (1) of the first dielectric layer 2 1 and the first wiring layer 24. a layer 25, a second dielectric layer 251, a 110717 12 1354356 layer 252 formed on the second dielectric layer 251, and a plurality of dielectric layers formed on the second dielectric layer. The second conductive via 2 ′ of the first and second circuit layers 24 , 252 and the second electrical contact pad 254 electrically connected to the circuit layer 252 are formed on the build-up structure 25 . As shown in FIG. 2F, the carrier board 2 is removed and its cover = electric (four)' to expose the bottom of the first conductive blind via 241: the upper & melon used in the dielectric layer 'because of the metal The connection of the carrier board. Therefore, the right side is used to join the metal carrier board, and the metal carrier board will be removed: an etching technique is needed to completely remove the metal carrier board, which not only allows the silver to be excessively damaged but also destroys the internal line, and The process steps are complicated and costly. In the above method, in the method of manufacturing, the first dielectric layer has an aromatic-based helium-oxygen polymer material, which is made of a metal material: 柘20 has poor bonding property, and the first dielectric material can be used. The layer 2 is directly connected to the board 2, and then the first conductive layer and the second layer covered by the carrier board 2 are removed, and the first surface of the first dielectric layer 21 is coated with the first conductive blind. A first %' is formed on the bottom 241 of the hole 241, and a first opening (10) is formed in the first solder resist layer 27a to expose the bottom portion 2410 of the first conductive blind hole 241, so that the first conductive blind hole 241 The bottom portion 2410 is exposed on the surface of the first opening as a first contact pad, and a second solder resist layer 27b is formed on the build-up structure 25, and the first layer hunts to form a second opening 27. , to expose the second electrical contact as shown in FIG. 2H 'following' on the first - anti-bar layer and 1 - opening, the second solder mask 27b and its second opening (4) 110717 13 Forming a second conductive layer 2 81 such as titanium/copper (T i / Cu ); forming a second resist layer 282 on the second conductive layer 281 and forming the second resist layer 282 The second opening area 2820 is numbered to expose the first opening 27a and the second opening 270b. As shown in FIG. 21, the second conductive layer 281 in the second opening region 282 is raised into a small electrical bump (Μ) 28, which is a metal such as tin, copper, nickel, cobalt, titanium, or the like. One of the group is formed and electrically connected to the first electrical contact pad 2 ♦ and the ♦ contact pad 254, respectively. # The second resist layer 282 and the second conductive layer 281 are removed as shown in Fig. 2J. Solitary meaning [Second embodiment] Please refer to Figs. 3A to 31'. This embodiment and the first embodiment are that the carrier plate is an insulating plate. The difference is provided as follows: the carrier plate of the insulating plate is 2〇, and the surface of the surface has an auxiliary dielectric layer 31; then, an auxiliary conductive layer 32 is formed on the auxiliary octet surface; after that, the auxiliary 2 2 = ... is a metal layer 33 of copper. The auxiliary conductive crucible is, for example, titanium/copper (Ti/cu). ^•嘈32 As shown in FIG. 3B, a first dielectric layer u having a ★ person: face 21a and a second surface 21b is formed on the metal layer 33, and the first electrical layer 21 is formed on the second surface 21b. Contacting the metal layer buckle, a plurality of dielectric layer openings 210 are formed in the dielectric layer 21, _: a portion of the surface of the portion 331. wherein: the metal layer 21 layer 21 is a photosensitive polymer H0717 14 1354356. Or a thermosetting southern molecule, preferably a fluorinated polymer having an aromatic group, the molecular formula of which is, for example: . ch3 ch3 -(Ar-(Si-〇>Si-)m-)- • CH3 ch3. As shown in FIG. 3C, a first conductive layer 22 such as titanium/copper is formed on the first dielectric layer 21 and the dielectric layer opening 210; a first resistive layer 23 is formed on the first conductive layer 22, and a plurality of first open regions 230 are formed to expose a portion of the first conductive layer 22 and the dielectric layer opening 21 of the first dielectric layer 21. a conductive layer 22. As shown in FIG. 3D, a first wiring layer 24 is formed on the first conductive layer 22 of the first opening 23 及 and the first dielectric layer, and the first dielectric layer is formed on the first dielectric layer 21 and dielectric layer opening 21〇 A first conductive via hole 241 is formed on the first conductive layer 22. As shown in FIG. 3E, the first resist layer 23 and the first conductive layer 22' covered thereby are removed to expose the first circuit layer 24. As shown in FIG. 3F, a build-up structure 25 as described in FIG. 2E is formed on the first dielectric layer and the first circuit layer 24. As shown in FIG. 3G, the carrier board 2 is removed. , the auxiliary dielectric layer 3, the auxiliary conductive layer 32, the metal layer 33, and the metal=electric layer 22 to expose the second surface 2 of the first dielectric layer 21 = the bottom portion 2410 of the first conductive blind via 241 As shown in FIG. 3H, a first solder resist layer 27a is formed on the second surface (10) of the first dielectric layer 21 and the first conductive pad 241, and the first 110717 15 1354356 · solder resist layer a first opening 27〇3 is formed in 27a to expose the bottom of the first conductive hole, such as a bottom of the first conductive blind, such as a bottom portion of the first conductive hole 270a as a first electric The second solder mask layer 27b is formed with a second opening 2 and is exposed to expose the second electric pad 254. 3 1 is formed on the first solder resist layer 27a and the surface of the first opening 270a, the surface of the second solder resist layer 2b and the second opening 27 thereof, as shown in FIG. 2J. The conductive bumps 28. The present invention further discloses a multilayer package substrate, comprising: a first dielectric = 1 ' having a first conductive blind via 241, a first surface from (1) and a first surface 2lb opposite the surface 21a, and The portion 2410 of the first conductive blind via 241 is exposed on the second surface 21b; the first wiring layer 24 is disposed on the first surface 21a of the j-dielectric layer 21; and the build-up structure 25 is disposed thereon. The first surface 213 of the electrical layer 21 and the first circuit layer 24 are respectively formed with a plurality of second conductive blind vias 2M electrically connected to the first circuit layer 24; the first solder resist layer 27a is provided on the first surface a second surface 21匕j of the dielectric layer 21 is “on the conductive via 241 and has a first opening 27〇a for the bottom 2410 of the first conductive via 241 to be exposed in the first opening 27〇a , as the first electrical contact pad 24a; and the first conductive layer 22 is disposed between the first circuit layer 24 and the first surface 2ia of the first dielectric layer 21, and the conductive hole 241 and the first dielectric Between layers 21, A pen not overlap the first hole 241 of the bottom 241 billion. According to the above structure, the first conductive layer 16 such as titanium/copper (Ti/Cu) is included, and the electrical layer 22 is disposed between the first circuit layer 24 and the first surface 2, and The first conductive via 241 is between the first dielectric layer 21 and the first conductive layer 21 . According to the above structure, the first dielectric 3521 4 has an aromatic group, and the molecular formula is: CH3 CH3 — (Ar-(S丨ch ch3 ch3 • second:= structure, including at least one second) The dielectric layer 25 is disposed on the first circuit layer 252 on the first substrate a, and the second conductive layer disposed in the second dielectric= electrically connected to the first and second circuit layers 24 252. The blind hole 253 ′ is provided with a plurality of electrical connections to the first line, the second electrical contact of the layer 252 is removed, and the second layer 28 is covered with the second solder resist layer 27 b. The second solder mask 27b has a second opening 270b to expose the second electrical contact 塾 (10). According to the above structure, on the first solder resist 27a and the first opening 27〇a • surface, The second anti-tank layer 27b and the second opening 27b are surface electric bumps 28, and the conductive bumps 28 are electrically connected to the first electrical contact port 24a and the first electrical contact port 254, respectively. The multi-layer package substrate and the manufacturing method thereof are mainly formed on the carrier board to form a first dielectric layer and a first circuit layer, and then formed on the first dielectric layer and the first circuit layer. a layer structure, after which the carrier plate is removed to expose a bottom portion of the first conductive via hole formed in the first dielectric layer, and the first portion of the conductive via hole and the first dielectric layer are formed on the exposed portion a solder resist layer, and a second solder resist layer is formed on the build-up structure, and a germanium-free package substrate having no core base 110717 17 1354356 is formed, which can improve the wiring density, and the present invention is a core to a substrate and It is not necessary to make electric material through holes, which can simplify the process and form a fine circuit structure. / ★ Also, the first dielectric layer and the metal carrier plate are not well bonded, and the first electric layer can directly strip the carrier board. In order to avoid the re-step and consumption (four), and thus improve the efficiency of the process.
再者’藉由第—防焊層之第-開孔露出該第一導電盲 孔的底部’以作為第-電性連接墊’而達成細間距的效果。 上述實施例僅例示性說明本發明之原理及其功效，而 非用於限制本發明。任何孰習 17热自此項技蟄之人士均可在不違 月本發明之精神及範疇下，對 微。 可下對上述貫施例進行修飾與改 3C。因此’本發明之權利俾罐益阁 ，應如後述之巾請專利 乾圍所列。 【圖式簡單說明】 弟1A至1H圖係為習知辦展翼化> ΟΑ θ層基板之製法剖面示意圖； 第2Α至2J圖係為本發明之吝馬 —η, 知月之夕層封裝基板之製法第一 貫細例之剖面示意圖；以及 弟3Α至31圖係為本發明 實施例之剖面示意圖。 之多層封裝基板之製法第二 【主要元件符號說明】 10 核心基板 100 絕緣層 101 金屬薄層 102 通孔 110717 18 1354356 102a 電鍍導通孔 103 、 33 金屬層 104 内層線路層 11 塞孔材料 12 介電層 120 開孔 13 導電層 14 阻層 15 線路層 20 、 20， 承載板 21 第一介電層 210 介電層開孔 21a 第一表面 21b 第二表面 22 第一導電層 23 第一阻層 230 第一開口區 24 第一線路層 241 第一導電盲孔 2410 底部 24a 第一電性接觸墊 25 增層結構 251 第二介電層 252 第二線路層 1354356 253 第二導電盲孔 ·. 254 第二電性接觸墊 27a 第一防焊層 270a 第一開孔 27b 第二防焊層 270b 第二開孔 28 導電凸塊 281 第二導電層 φ 282 第二阻層 2820 第二開口區 31 輔助介電層 32 輔助導電層Further, the effect of fine pitch is achieved by exposing the bottom portion of the first conductive via hole by the first opening of the first solder resist layer as the first electrical connection pad. The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Anyone who is a student of this skill can do so against the spirit and scope of the invention. The above examples can be modified and modified. Therefore, the right of the present invention can be listed in the patents as described later. [Simple diagram of the drawing] The brothers 1A to 1H are the schematic diagrams of the manufacturing method of the 办 θ layer substrate; the 2nd to 2J diagrams are the 吝马-η of the invention, the layer of the moon A schematic cross-sectional view of a first embodiment of a method for fabricating a package substrate; and a schematic view of a third embodiment of the present invention is a schematic cross-sectional view of an embodiment of the present invention. Method for manufacturing multi-layer package substrate [Main element symbol description] 10 core substrate 100 insulating layer 101 metal thin layer 102 through hole 110717 18 1354356 102a plating via 103, 33 metal layer 104 inner layer circuit layer 11 plug material 12 dielectric Layer 120 opening 13 conductive layer 14 resist layer 15 circuit layer 20, 20, carrier plate 21 first dielectric layer 210 dielectric layer opening 21a first surface 21b second surface 22 first conductive layer 23 first resist layer 230 First opening region 24 first circuit layer 241 first conductive blind hole 2410 bottom portion 24a first electrical contact pad 25 build-up structure 251 second dielectric layer 252 second circuit layer 1354356 253 second conductive blind hole ·. 254 Two electrical contact pads 27a first solder mask layer 270a first opening 27b second solder resist layer 270b second opening 28 conductive bump 281 second conductive layer φ 282 second resist layer 2820 second open region 31 auxiliary Electrical layer 32 auxiliary conductive layer
20 Π071720 Π0717