1355053 » · 九、發明說明： •【發明所屬之技術領域】 • 本發明係㈣於—種封裝基板結構及其製法，尤指一 種細線路之封裝基板及其製法。 •【先前技術】 為符合半導體封裝件輕薄短小、多功能、高速度及古 頻化的開發方向’該封職板已朝向細線路及小孔徑: 展。現有封裝基板製程從傳、统_微米之關鍵尺^ 丨（entice dimension) ’包括線路寬度（width)及線路 距等，已縮減至22微米，並且持續朝向更小 鍵尺寸發展。 為提高半導體晶片封裳用之封裝基板之佈線密度，業 界遂發展出一種增層技術（Built-up)，亦即在一核心板 (Core circui t board)表面利用線路增層技術交互堆疊多 層介電層及線路層。 〃請參閱第1A至1G圖，係為習知封裝基板增層製法； 如第1A圖所示’ S供一表面設有導電線路| ι〇ι之承载 層ίο,該導電線路層101具有複數導電線路l〇ia與電性 連接墊102，接著於該承載層1〇及導電線路層ι〇ι上形 成介電層11a’且於該介電層lla中形成複數盲孔ιι〇/ 以顯露該電性連接# 102;如帛1B圖所*，於該介電層 11a及盲孔iiGa表面上形成導電層m，接著於該導電層 12a上形成光阻層13a，該光阻们3a形成複數圖案化開 口區130a’以顯露盲孔110a中及部份之介電層na上的 110687 5 丄乃5053 12a;如第1C圖所示，於該盲孔U()a中電鑛形成 书盲孔14〇a，且於該圖案化開口區130a之介電層lla 上形成-線路| Ua，且該線路層14a纟有複數線路Si4ia 與電性連接部U2a; w1D圖所示，移除該光阻層… 及其所覆盍之導電層l2a’以顯露該複數線路141&與電 連接。P H2a,如第1E、1F圖所示’係重覆第以圖至 1D圖所示之線路製程，於該介電層⑴上、該線路層 + =上形成增層結構15，其具有另一介電層11卜複數導 電盲孔140b及另一線路層14b，且該線路層⑽且有複 數線路141b與電性連接部肋；如帛1G圖所示，於增 層結構15最外層之介電層m上形成絕緣保護層16，且 ;/、邑’’彖保濩層16中形成複數開孔i 6〇，以顯露最外層 之線路層14b作為電性接觸墊143。 惟，該電性連接墊102及電性連接部142a l42b之寬 度係大於該導電盲孔之寬度，使同—線路層 中之該線路141a，141b之間的間距無法縮小，各 电性連接墊102之間及各電性連接部142a，142b之間的間 距亦無法縮小，致使佈線密度無法提高，不利於封裝基板 之發展趨勢。 六因此，如何提出一種封裝基板，以避免習知技術之伟 f二間/良費，而無法提高線路之佈線密度的缺失，實已成 爲目前業界亟待克服之課題。 【發明内容】 鑒於上述習知技術之缺失，本發明之主要目的係提供 110687 6 1355053 ， * .-種提高線路佈局密度之細線路之封裳基板及。 封述目的及其他目的，本發明揭露-種：線路之 .封衣基板衣法，係包括：提供一承载層，於立至少 ,形成導電線路，且該導電線路具有第—電性連接部；於^ :二形成第一介電層，並於該第-介電 耵I肩路該弟-電性連接部，且該 之孔徑大於該第-電性連接部之寬度；於該第—介電声 表面及該盲孔中形成導電層； 曰 ^ β y , '必等电層上形成阻層，且 1:阻層形成開口區’該開口區對應該盲孔， =盲孔之孔徑；於該開口區中之導電層上形成； I線路層，而於該盲孔中之導電層上形成第—導電盲孔以 “生連接該第一電性連接部與該第一線路層，且該第一電 部之寬度小於該第—導電盲孔之孔徑，以使該第- 所择Γ孔L覆該第冑性連接部；以及移除該阻層及其 後盍之導電層，以顯露該第一介電層及第一線路層。 於上述之製法中，該承載層係可為絕緣板、具内層線 之封裝基板或多層封裝基板内部之介電材料層。 亡於上迷之製法中，該第—線路層可具有設於第一導電 =上之第二電性連接部，且該第二電性連接部之寬度小 於第一導電盲孔之孔徑。 於上34之製法中，復可包括增層結構，其具有形成於 :第，層及該第一線路層上之至少一第二介電層、形 展於該第—介電層上之第二線路層、及形成於該第二介電 曰中且電性連接邊第二線路層之複數第二導電盲孔，且部 110687 7 1355053 份第二導電盲孔電性連接該第—線路層。 於上述製法，以形成增層結構為基本需 =具有第二電性連接部，以使該第二導電盲二二 ^電性連接部，而該第二線路層可具有第三電= =導 ^ 三電性連接部可設於該第二導電盲孔上或被該 书目孔所包覆。此外，該增層結構最外面之 3具有^數電性接觸塾，且於該增層結構上形成絕二 接‘塾亚蔓層形成複數開孔以對應顯露該電性 丨/、中，戎電性接觸墊之寬度可大於該第_ 孔之孔徑。 冲—命包目 本發明復提供-種細線路之封裝基板，係包括：承载 θ ’糸至少一表面具有$電線路，且該導電線路具有第— :性=部；第—介電層，係設於該承載層及導電線路 ，弟—導電盲孔，係設於該第一介電層中，並電性 ^導電線路之第-電性連接部，且該第—電性連接部之 :::於该第一導電盲孔之孔徑’以使該第一導電盲孔包 覆该第-電性連接部；卩及第—線路層，係設於該第—介 電層上且具有第二電性連接部，該第二電性連接部電性 接該第一導電盲孔。 依上述結構，該承載層係可為絕緣板、具内層線路之 于裝基板或多層封裝基板内部之介電材料層。 又’該第一線路層可具有設於該第一導電盲孔上之第 二電性連接部，且該第二電性連接部之寬度可小於該第一 導電盲孔之孔徑。 110687 8 此外，於另一結構能声由 ^ 結構，其具有設於該第—二1⑥封裝基板復可包括增詹 一第_八+ @ 7丨电層及該第一線路層上之至少 於嗲第,电層上之弟二線路層、及設 導泰亡π七 电性連接該弟二線路層之複數第二 ¥电目孔’且部份第二導雷亡 1中笔性連接該第'線路層。 二導恭亡φ 有弟一电性連接部，且該第 有第三電性連接部’且今第雷接/查而該弟二線路層可具 盲孔上或被第二導带“ 较丨叹㈣弟一導電 所包覆。此外，該增層結構最外 第一線路層可具有複數電性接觸塾，且該增声 護層，其係具有複數開孔以對應顯露性接 孔徑。 該電性接觸塾之寬度大於該第二導電盲孔之 夂垂由上可知，本發明之細線路之封裝基板及其製法，因 各電性連接部均為導電盲孔所包覆，且該第一線路層之第 •:電’:生連接部之寬度小於第一導電盲孔之孔徑，故，使本 X月藉由上述兩個結構特徵，可避免線路佔用面積過大， 以達到細線路並提高線路佈設密度之目的。 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 式热悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 請參閱第2A至2L圖，係詳細說明本發明之細線路之 封裝基板及其製法之剖面示意圖。 9 Π0687 如第2A圖所示，提供一— 路201夕、 主^ "'表面具有複數導電後 =且二承：該導電線路-具有第-電性連接 電層&，並於該第二21=電二路201上形成第-介 =TL經大於第一電性連接部2㈣ 吏目孔210a對應顯露第一 载層20係為絕緣柄、|㈣ώ P⑽’其中該承 其& 八内層線路之封裝基板或多層封裝 基板内部之介電層之其中一者。 打褒 上妒^圖所不，於該第一介電I 21a及盲孔210a 且接著於該導電層22a上形成阻層仏， 且該阻層23a形成開口區23〇a。 該導電層22a主要係作爲後續電鍍金屬材料所需之 ^傳導路經，其可由金屬、合金或沉積數層金屬層所構 々、如選自銅、錫、鎳、鉻、欽、銅_絡合金或錫—船合金 等所構成之群組之其中一者所組成’係以藏鏟、蒸鍍、無 電電鍍及化學沈積之—者形成；餘層…係例如為乾 膜或液態光阻等光阻層（Phot〇resist)，其利用印刷、旋 2或貼合等方式形成於該導電層22a上，再藉由曝光、顯 影等方式加以圖案化，以形成圖案化開口區23〇a而顯露 部份之導電層22a，其中部份開口區23〇a對應顯露該盲 孔21〇a中之導電層22a，且該開口區23〇a之寬度小於該 盲孔210a之孔徑。 如第2C圖所示，藉由該導電層22a，以於開口區230a 中電鍍形成第一線路層241a，且於盲孔21 〇a中形成第一 10 110687 1355053 :電盲孔24〇a以電性連接第一電性連接 %性連接部202之寬度小於第—導雷亡 口弟一 使得第-導電盲孔2術包;^ a之孔’ Λ第—电性連接部202。 另外，該第-線路層2413具 以電性連接第-導電盲孔2…中，； 部242a之寬度小於第—導 -d生連接 二電性連接部⑽設於第-導電盲孔耻之表面弟 如第2D、2D’圖所示，移除該阻層1355053 » · IX. Description of the invention: • [Technical field to which the invention pertains] The present invention relates to a structure of a package substrate and a method of manufacturing the same, and more particularly to a package substrate of a fine line and a method of manufacturing the same. • [Prior Art] In order to meet the development trend of thin, short, versatile, high-speed and ancient frequency of semiconductor packages, the sealing board has been oriented toward fine lines and small apertures: The existing package substrate process has been reduced to 22 micrometers from the key dimensions of the transmission system, including the line width and line spacing, and continues to develop toward smaller key sizes. In order to improve the wiring density of the package substrate for semiconductor wafer sealing, the industry has developed a layer-up technology, that is, the layer stacking technology is used to alternately stack multiple layers on the surface of a core circui t board. Electrical layer and circuit layer. Please refer to FIGS. 1A to 1G for the conventional package substrate build-up method; as shown in FIG. 1A, the S surface is provided with a conductive line | 〇 之 承 承 , , , , , , , , , , , a conductive layer 10A and an electrical connection pad 102, and then a dielectric layer 11a' is formed on the carrier layer 1 and the conductive layer ι, and a plurality of blind holes ιι〇 are formed in the dielectric layer 11a to reveal The electrical connection #102; as shown in FIG. 1B, a conductive layer m is formed on the surface of the dielectric layer 11a and the blind via iiGa, and then a photoresist layer 13a is formed on the conductive layer 12a, and the photoresist 3a is formed. The plurality of patterned opening regions 130a' are exposed to reveal 110687 5 丄 or 5053 12a on the dielectric layer na of the blind via 110a; as shown in FIG. 1C, the electric ore is formed in the blind via U()a a blind hole 14〇a, and a line|Ua is formed on the dielectric layer 11a of the patterned opening region 130a, and the circuit layer 14a has a plurality of lines Si4ia and an electrical connection portion U2a; The photoresist layer ... and the conductive layer 12a' covered thereon are electrically connected to the plurality of lines 141 & P H2a, as shown in FIGS. 1E and 1F, repeats the line process shown in FIG. 1D to FIG. 1D, and a build-up structure 15 is formed on the dielectric layer (1) and on the circuit layer +=, which has another A dielectric layer 11 includes a plurality of conductive vias 140b and another circuit layer 14b, and the circuit layer (10) has a plurality of lines 141b and electrical connection ribs; as shown in FIG. 1G, at the outermost layer of the buildup structure 15 An insulating protective layer 16 is formed on the dielectric layer m, and a plurality of openings i 6 形成 are formed in the 彖 彖 彖 layer 16 to expose the outermost wiring layer 14 b as the electrical contact pads 143. However, the width of the electrical connection pad 102 and the electrical connection portions 142a to 42b is greater than the width of the conductive via hole, so that the spacing between the lines 141a, 141b in the same circuit layer cannot be reduced, and the electrical connection pads are The spacing between the 102 and the electrical connecting portions 142a, 142b cannot be reduced, so that the wiring density cannot be improved, which is disadvantageous for the development trend of the package substrate. Sixth, therefore, how to propose a package substrate to avoid the fascination of the prior art, and the lack of wiring density of the line, has become an urgent problem to be overcome in the industry. SUMMARY OF THE INVENTION In view of the above-mentioned shortcomings of the prior art, the main object of the present invention is to provide 110687 6 1355053, a kind of thin-lined substrate with improved line layout density. The purpose of the present invention and other objects, the invention discloses: a method of packaging a substrate, comprising: providing a carrier layer, at least forming a conductive line, and the conductive line has a first electrical connection; Forming a first dielectric layer on the second dielectric layer, and forming the first dielectric layer on the first dielectric interlayer, and the aperture is larger than the width of the first electrical connection portion; A conductive layer is formed on the electroacoustic surface and the blind hole; 曰^β y , 'the resist layer is formed on the isoelectric layer, and 1: the resist layer forms the open region'. The open region corresponds to the blind hole, and the aperture of the blind hole; Forming a first circuit layer on the conductive layer in the open region; and forming a first conductive via hole on the conductive layer in the blind via to "connect" the first electrical connection portion and the first circuit layer, and The width of the first electric portion is smaller than the aperture of the first conductive via hole, so that the first selected pixel L covers the second connection portion; and the conductive layer of the resist layer and the rear germanium is removed to The first dielectric layer and the first circuit layer are exposed. In the above method, the carrier layer may be an insulating plate with an inner layer The dielectric material layer is mounted on the substrate or the multi-layer package substrate. In the above method, the first circuit layer may have a second electrical connection portion disposed on the first conductive=, and the second electrical connection The width of the portion is smaller than the aperture of the first conductive via hole. In the method of the above 34, the complex includes a build-up structure having at least one second dielectric layer formed on the first layer and the first circuit layer, a second circuit layer formed on the first dielectric layer and a plurality of second conductive blind holes formed in the second dielectric layer and electrically connected to the second circuit layer, and the portion is 110687 7 1355053 The second conductive blind via is electrically connected to the first circuit layer. In the above method, the formation of the build-up structure is basically required to have a second electrical connection portion, so that the second conductive blind two-two electrical connection portion The second circuit layer may have a third electrical connection. The electrical connection portion may be disposed on or covered by the second conductive blind hole. Further, the outermost layer of the buildup structure has ^ Electrically contacting the crucible, and forming a plurality of openings on the layered structure to form a plurality of openings Correspondingly, the width of the electrical contact pads may be greater than the aperture of the first hole. The package of the invention provides a package substrate of fine lines, including: bearing θ ' The at least one surface has a $electric line, and the conductive line has a first-:-----the dielectric layer is disposed on the carrying layer and the conductive line, and the conductive-blind hole is disposed in the first medium In the electrical layer, electrically connecting the first electrical connection portion of the conductive line, and the first electrical connection portion is::: the aperture of the first conductive blind hole to cover the first conductive blind hole The first electrical connection portion is electrically connected to the first conductive blind hole. The second electrical connection portion is electrically connected to the first conductive blind hole. According to the above structure, the carrier layer may be an insulating plate, a layer of dielectric material having an inner layer on the substrate or the multilayer package substrate. Further, the first circuit layer may have a second electrical connection portion disposed on the first conductive via hole, and the width of the second electrical connection portion may be smaller than the aperture of the first conductive via hole. 110687 8 In addition, in another structure, the sound structure is provided, and the device has a structure on the first to the second 16th package substrate including at least one of the _8+@7 丨 electrical layer and the first circuit layer.嗲 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The 'circuit layer. The second guide is dead and has a mechanical connection, and the third electrical connection is the first one. The sigh (4) is coated with a conductive material. In addition, the outermost first circuit layer of the build-up structure may have a plurality of electrical contact ridges, and the sound-increasing cover layer has a plurality of openings to correspond to the exposive aperture. The width of the electrical contact 塾 is larger than that of the second conductive blind hole. The package substrate of the thin circuit of the present invention and the manufacturing method thereof are covered by the conductive blind holes, and the electrical connection portion is covered by the conductive blind hole. The first line layer of the first circuit layer::electricity: the width of the raw connection portion is smaller than the aperture of the first conductive blind hole, so that the above two structural features can avoid the excessive occupied area of the line to achieve fine lines. The purpose of the present invention is to clarify the other advantages and effects of the present invention. The embodiments of the present invention can be easily understood by those skilled in the art from the disclosure of the present invention. Please refer to Figures 2A to 2L, DETAILED DESCRIPTION OF THE INVENTION A schematic diagram of a package substrate of a thin circuit of the present invention and a method for fabricating the same are provided. 9 Π0687 As shown in FIG. 2A, a road 201 is provided, and the main surface has a plurality of conductive states and the second conductor: the conductive The circuit has a first electrical connection layer & and a first dielectric layer is formed on the second 21=electric two-way 201. The first carrier layer is exposed corresponding to the first electrical connection portion 2 (4). The 20 series is an insulating handle, and (4) ώ P(10)' is one of the dielectric layers of the package substrate or the multilayer package substrate of the eight inner layer of the circuit. The upper layer is not included in the first layer. The conductive layer 21a and the blind via hole 210a are formed on the conductive layer 22a, and the resist layer 23a forms an open region 23〇a. The conductive layer 22a is mainly used as a conductive path for the subsequent plating of the metal material. , which may be composed of a metal, an alloy or a plurality of layers of a metal layer, such as a group selected from the group consisting of copper, tin, nickel, chromium, chin, copper-alloy or tin-boat alloy. 'The system is formed by shovel, evaporation, electroless plating and chemical deposition; For example, it is a photoresist layer such as a dry film or a liquid photoresist, which is formed on the conductive layer 22a by printing, spin-bonding or bonding, and then patterned by exposure, development, or the like. a portion of the conductive layer 22a is formed by forming the patterned opening region 23a, wherein a portion of the opening region 23a corresponds to the conductive layer 22a in the blind hole 21a, and the width of the opening region 23a The hole diameter of the blind hole 210a is smaller than that of the blind hole 210a. As shown in Fig. 2C, the first circuit layer 241a is plated in the opening region 230a by the conductive layer 22a, and the first 10 110687 1355053 is formed in the blind hole 21 〇a. : The electric blind hole 24〇a is electrically connected to the first electrical connection. The width of the % connection portion 202 is smaller than that of the first guide port, and the first conductive padding hole 2 is used for the first conductive padding hole 2; Electrical connection portion 202. In addition, the first-line layer 2413 is electrically connected to the first-conducting blind hole 2...; the width of the portion 242a is smaller than the first-conductive-d-connected two-electrode connection (10) is set in the first-conductive blind hole shame The surface is removed as shown in Figures 2D and 2D'.
>導電層22a，以顯露該第一介帝 二所U 1书層21a及弟一線路層 2仏。弟加圖係以上視圖顯示第2D圖中虛線框中之第 =層241a、第二電性連接部2似、第一導電盲孔⑽ 與導電線路2〇1及第一電性連接部2〇2之空間型態。如圖 :不’該導電線路2G1之第—電性連接部搬為第一導電 盲孔24〇a所包覆’而該第一線路層241a之第二電性連接 部242a與第-導電盲孔24〇a相接部位僅位於第—導電盲 孔24Ga之表面範圍内，俾以免除習知技術之連接部位佔 用面積過大之問題。 如第2E圖至2H圖所示，重覆第2A圖至第2D圖所示 之線路製程，以於該第一介電層21a及第一線路層241日 上开> 成增層結構25，且該增層結構25具有 設於第一介電 層21a及苐一線路層241a上之至少一第二介電層21b、 設於第二介電層21b上之第二線路層241b、及設於第二 介電層21b中且電性連接第一及第二線路層241a，241b 之第二導電盲孔240b。 11 Π0687 1355053 °亥弟~~線路層241b具有覓度小於第二導電盲孔24〇b 之孔徑之第三電性連接部242b，且部份第三電性連接部 242b設於第二導電盲孔24〇b之部份表面而部份第三電 性連接部242b被第二導電盲孔240b所包覆。 如第21圖至2K圖所示，接著，於該增層結構託最 外層之第二線路層241c形成複數電性接觸墊242c，且該 電性接觸塾242c之寬度大於第二導電盲孔2傷之孔徑: 如第2L圖所示’於增層結構25最外層之第二介電層 <b、第二線路層241c及電性接觸塾242。上形成絕緣保 »曰26，且於該絕緣保護層26中形成複數開孔2⑽以 顯露該電性接觸墊242c。 本發明復提供-種細線路之封裝基板，係包括：承 2θ〇ι2Γ右於/至少一表面設有導電線路201，且導電線路 八有弟一電性連接部2〇2;第一介電層21心係机於 承制2〇及導電線路201上；帛一導電盲孔24Ga，_ 介電層2la中’並電性連接至導電線路2()ι之第一 'j接部202’該第—電性連接部挪之寬度小 =電目孔240a之孔徑，以使第一導電盲孔2伽包 21性::：2°2;以及第—線路層’係設於第-介電戶 21a上且電性達接第—導電盲孔施。 电層 依上述結構’該承载層2〇係為絕緣板、具 之封裝基板或多層封穿其4 «線路 路層灿具有設於Γ-導板 =部之介電材料層。該第-線 部242a，且第二電性連24Ga上之第二電性連接 电性連接部242a之寬度小於第一導電盲 110687 12 1355053 ♦ ♦ . 孔240a之孔徑。 該封裝基板復包括增層結構25，其具有設於第一介 電層21a及第一線路| 241a上之至少―第二介電層 抓、設於第二介電層21b上之第二線路層懸，24lc、曰 及設於第二介電層21b中且電性連接第二線路層 241b’241c之複數第二導電盲孔24〇b，且部份第二導電盲 孔2働電性連接第-線路層241a。該第二導電盲孔觸 包覆第二電性連接部242a，而第二線路層241[)且有第三 電性連接部242b，以設於第二導電盲孔鳩 導電盲孔240b所包覆。 此外，該增層結構25最外面之第二線路層⑽具有 ^數電性接觸墊242c，且該增層結構25上設有絕緣保護 曰26,其具有複數開孔26〇以對應顯露電性接觸塾如〇 ^電性接觸塾242c之寬度大於第二導電盲孔2傷之孔 綜上所述，本發明之細線路之封裝基板及其製法，因 電線路之第-電性連接部之寬度小於第一導電盲孔之 孔化’使第-電性連接部為第—導電盲孔所包覆，且該第 :及第三電性連接部之寬度小於該第二導電盲孔^孔 訌，故，使本發明藉由各電性連接部設於各導電盲孔表 :’且各導電盲孔包覆各電性連接部之上述兩二構特 ::皁以免除線路佔用面積過大之弊端，以達細線路並提 同線路佈設密度之目的。 上述實施例係用以例示性言兒明本發明之原理及其功 110687 13 1355053 效’而非用於限制本發明。^^ 2 ^ 产土 b +卷明任何熟習此項技藝之人士均可 在不运为本發明之精神及銘# ,,π 甲及乾命下，對上述實施例進行修 改。因此本發明之權利保確 ^ '、°又乾圍，應如後述之申請專利範 固所列。 【圖式簡單説明】 第1Α至1G圖係為習知半導體封裝基板增層製法之流 程示意圖；以及 第2A至2L圖係為本發明細線路之封裝基板及其製法 •之剖面示意圖；其中，第2D，圖係為第2D圖之上視圖。 【主要元件符號說明】 10, 20 承載層 101 導電線路層 l〇la,201 導電線路 102 電性連接墊 11a,lib 介電層 110a,210a 盲孔 12a, 22a 導電層 13a 光阻層 130a 圖案化開口區 14a, 14b 線路層 140a,140b 導電盲孔 141a,141b 線路 142a,142b 電性連接部 143,242c 電性接觸墊 14 110687 1355053 15, 25 增層結構 16, 26 絕緣保護層 160, 260 開孔 202 第一電性連接部 21a 第一介電層 21b 第二介電層 23a 阻層 230a 開口區 240a 第一導電盲孔 240b 第二導電盲孔 241a 第一線路層 242a 第二電性連接部 241b 、 241c 第二線路層 242b 第三電性連接部> Conductive layer 22a to expose the first U1 book layer 21a and the second circuit layer 2A. The above view shows the first layer 241a, the second electrical connection portion 2, the first conductive blind hole (10) and the conductive line 2〇1 and the first electrical connection portion 2 in the dotted frame in the 2D drawing. 2 spatial type. As shown in the figure: the second electrical connection portion 242a of the first circuit layer 241a and the first conductive boundary are not covered by the first conductive layer 24a. The contact portion of the hole 24〇a is only located in the surface range of the first conductive blind hole 24Ga, so as to avoid the problem that the occupied area of the connection portion of the prior art is too large. As shown in FIGS. 2E to 2H, the line process shown in FIGS. 2A to 2D is repeated to open the first dielectric layer 21a and the first circuit layer 241. The build-up structure 25 has at least one second dielectric layer 21b disposed on the first dielectric layer 21a and the first wiring layer 241a, a second wiring layer 241b disposed on the second dielectric layer 21b, and The second conductive blind via 240b is disposed in the second dielectric layer 21b and electrically connected to the first and second circuit layers 241a, 241b. 11 Π 0687 1355053 ° Haidi~~ circuit layer 241b has a third electrical connection portion 242b having a smaller diameter than the second conductive blind hole 24〇b, and a portion of the third electrical connection portion 242b is disposed on the second conductive blind A portion of the surface of the hole 24〇b and a portion of the third electrical connection portion 242b are covered by the second conductive blind hole 240b. As shown in FIG. 21 to FIG. 2K, a plurality of electrical contact pads 242c are formed on the second circuit layer 241c of the outermost layer of the build-up structure, and the width of the electrical contact pads 242c is greater than the second conductive vias 2. Aperture of the wound: As shown in Fig. 2L, the second dielectric layer <b, the second wiring layer 241c and the electrical contact 242 are formed at the outermost layer of the buildup structure 25. An insulating layer is formed on the substrate 26, and a plurality of openings 2 (10) are formed in the insulating protective layer 26 to expose the electrical contact pads 242c. The present invention provides a package substrate of a fine line, comprising: a conductive line 201 disposed on the right side of at least one surface of the substrate, and a conductive connection line 〇2; The layer 21 core machine is formed on the conductor 2 and the conductive line 201; the first conductive hole 24Ga, the dielectric layer 2a' is electrically connected to the first 'j junction 202' of the conductive line 2 () The width of the first electrical connection portion is small = the aperture of the electric hole 240a, so that the first conductive blind hole 2 is smeared 21::: 2 ° 2; and the first circuit layer is set at the first The electric household 21a is electrically connected to the first conductive blind hole. Electrical layer According to the above structure, the carrier layer 2 is an insulating plate, has a package substrate or a plurality of layers of a dielectric material layer which is disposed on the Γ-guide plate. The width of the second electrical connection portion 242a on the second electrical connection 24Ga is smaller than the width of the first conductive blind 110687 12 1355053 ♦ ♦ . The package substrate further includes a build-up structure 25 having at least a second dielectric layer disposed on the first dielectric layer 21a and the first line 241a, and a second line disposed on the second dielectric layer 21b. a plurality of second conductive blind vias 24b disposed in the second dielectric layer 21b and electrically connected to the second wiring layer 241b' 241c, and a portion of the second conductive vias 2 The first-line layer 241a is connected. The second conductive blind via contacts the second electrical connection portion 242a, and the second circuit layer 241[] has a third electrical connection portion 242b to be disposed in the second conductive blind via conductive blind via 240b. cover. In addition, the outermost second circuit layer (10) of the build-up structure 25 has a plurality of electrical contact pads 242c, and the build-up structure 25 is provided with an insulating protection 曰 26 having a plurality of openings 26 〇 to correspondingly expose electrical properties. The contact substrate such as the electrical contact 塾 242c has a width greater than that of the second conductive blind hole 2, and the package substrate of the thin circuit of the present invention and the method for manufacturing the same, due to the first electrical connection of the electrical circuit The width is smaller than the hole of the first conductive blind hole', so that the first electrical connection portion is covered by the first conductive blind hole, and the width of the first and third electrical connection portions is smaller than the second conductive blind hole Therefore, the present invention is provided in each of the conductive blind vias by the respective electrical connection portions: 'and each of the conductive blind vias covers the two two-components of each of the electrical connecting portions:: soap to avoid excessive line occupation area The drawback is to achieve the purpose of thinning the line and laying the line with the density. The above-described embodiments are intended to illustrate the principles of the invention and its function, and not to limit the invention. ^^ 2 ^ Producing soil b + Explain Anyone who is familiar with this skill can modify the above embodiment without the spirit of the invention and the meaning of #, 甲甲和干命. Therefore, the rights of the present invention are guaranteed to be ', ° and dry, and should be listed in the patent application form described later. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to 1G are schematic flowcharts of a conventional semiconductor package substrate build-up method; and FIGS. 2A to 2L are cross-sectional views of a package substrate of the thin line of the present invention and a method for manufacturing the same; 2D, the figure is the top view of the 2D figure. [Main component symbol description] 10, 20 carrier layer 101 conductive circuit layer l〇la, 201 conductive circuit 102 electrical connection pad 11a, lib dielectric layer 110a, 210a blind hole 12a, 22a conductive layer 13a photoresist layer 130a patterned Open area 14a, 14b circuit layer 140a, 140b conductive blind hole 141a, 141b line 142a, 142b electrical connection portion 143, 242c electrical contact pad 14 110687 1355053 15, 25 build-up structure 16, 26 insulation protection layer 160, 260 opening 202 first electrical connection portion 21a first dielectric layer 21b second dielectric layer 23a resist layer 230a open region 240a first conductive blind hole 240b second conductive blind hole 241a first circuit layer 242a second electrical connection portion 241b 241c second circuit layer 242b third electrical connection
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