TWI576030B - Printed circuit board and fabricating method thereof - Google Patents

Description

Printed circuit board and manufacturing method thereof

The present invention relates to a printed circuit board and a method of fabricating the same.

In the conventional printed circuit board manufacturing, a solder printing process is employed to apply a solder mask layer on the surface of the completed circuit layer and form a plurality of openings in the solder resist layer. To expose the contact pads of the underlying circuit layer. Next, a print stencil is placed on the surface of the substrate, and the solder paste is squeezed into the solder mask opening in the stencil opening by a doctor blade, and then the template is removed and reflowed to melt the solder paste. For the solder ball.

In addition, today's electronic products continue to be light, thin, short, small, high speed, high frequency and multi-functional development. To meet these demands, the size of the wafer needs to be smaller and the number of I/O needs to be more, which means the circuit board The wiring area and the pitch between the solder balls also need to be increased and reduced, respectively. However, in the above solder printing process, limited by the image transfer alignment error, the size of the contact pads of the outermost layer of the printed circuit board must be larger than the aperture of the solder resist opening, which makes it difficult to reduce the pitch between the solder balls. Packing density is difficult to increase.

The industry has developed a bump on line (BOL) structure, as shown in FIGS. 1A and 1B, having a substrate surface S on a printed circuit board. The circuit layer 10 and the solder resist layer 20, wherein the plurality of openings 22 formed in the solder resist layer 20 correspond to the line 12 of the lower circuit layer 10 (outermost layer) instead of the contact pad 14, wherein the line width W of the line 12 can be less than The aperture D of the solder layer opening 22. In this way, the line 12 of the circuit layer 10 can be used instead of the contact pad 14 to connect with the solder ball B in the subsequent solder printing process, so that the pitch between the solder balls B (ie, the pitch P between the lines 12) can be greatly reduced. Increase package density.

However, as shown in FIG. 1C, when a plurality of solder resist opening 22 of the line 12 corresponding to the wiring layer 10 is formed by exposure development, the area between the line 12 and the edge of the solder resist opening 22 is rather narrow. The developing syrup is less likely to enter, and it is easy to leave a solder resist residue 23 at the bottom of the solder resist opening 22 after development, which may affect the yield and reliability of the subsequent package.

Therefore, there is a need in the industry for a novel printed circuit board and a method of fabricating the same, in order to solve or alleviate the above problems.

According to an embodiment of the present invention, a method for fabricating a printed circuit board includes: providing a substrate; forming a circuit layer on the substrate, wherein the circuit layer includes a plurality of lines; forming an insulating layer on the circuit layer; etching back etching a layer to expose an upper surface of the circuit layer; a solder resist layer formed on the insulating layer and the circuit layer, wherein the solder resist layer has a plurality of openings corresponding to the lines of the circuit layer, and the line width of each line is smaller than the openings Aperture; and forming a surface treatment layer on each line.

According to an embodiment of the present invention, a method for fabricating a printed circuit board includes: providing a substrate; forming a circuit layer on the substrate, wherein the circuit layer includes a plurality of lines; forming a first solder resist layer on the circuit layer; Etch etching a first solder resist layer to expose an upper surface of the circuit layer; a second solder resist layer formed on the first solder resist layer and the circuit layer, wherein the second solder resist layer has a plurality of openings corresponding to the lines of the circuit layer And the line width of each line is smaller than the aperture of each opening; and a surface treatment layer is formed on each line.

According to an embodiment of the invention, a printed circuit board includes: a substrate; a circuit layer on the substrate, the circuit layer includes a plurality of lines; an insulating layer on the circuit layer, the insulating layer having a plurality of first openings a circuit for respectively burying the circuit layer and exposing the upper surfaces of the lines; a solder resist layer on the circuit layer and the insulating layer, the solder resist layer having a plurality of second openings corresponding to the lines, wherein each line The line width is smaller than the aperture of each of the second openings; a plurality of surface treatment layers are respectively located on the line; and a plurality of solder balls are respectively located on the surface treatment layer.

According to an embodiment of the invention, a printed circuit board includes: a substrate; a circuit layer on the substrate, the circuit layer includes a plurality of lines; a first solder resist layer on the circuit layer, the first solder resist layer a plurality of first openings for respectively burying the lines of the circuit layer and exposing the upper surfaces of the lines; a second solder resist layer on the circuit layer and the first solder resist layer, and the second solder resist layer having a plurality of The second openings respectively correspond to the foregoing lines, wherein the line width of each line is smaller than the aperture of each second opening; a plurality of surface treatment layers are respectively located on the line; and a plurality of solder balls are respectively located on the surface treatment layer.

The above and other objects, features, and advantages of the present invention will become more apparent and understood by the appended claims appended claims

10‧‧‧Line layer

12‧‧‧ lines

14‧‧‧Contact pads

20‧‧‧ solder mask

22‧‧‧ solder mask opening, opening

23‧‧‧ solder mask residue

100‧‧‧Substrate

100a‧‧‧ first surface

100b‧‧‧ second surface

101‧‧‧conductive via electrodes

102‧‧‧Line layer

102a‧‧‧ Inner layer

102b‧‧‧Interlayer plug

102c‧‧‧ outer circuit layer

102d‧‧‧Opening

103‧‧‧Insulation

104‧‧‧Contact pads

106‧‧‧ lines

108‧‧‧Insulation

108a‧‧‧first opening

109‧‧‧First solder mask

109a‧‧ first opening

110‧‧‧ solder mask, second solder mask

112‧‧‧Second opening, opening

114‧‧‧Surface treatment layer

115‧‧‧ seed layer

116‧‧‧ solder balls

117‧‧‧ Cover pattern layer

118‧‧‧ openings

119‧‧‧metal layer

B‧‧‧ solder ball

D, D1, D2‧‧‧ aperture

P‧‧‧ spacing

S‧‧‧ substrate surface

W, W1, W2‧‧‧ line width

1A is a schematic cross-sectional view showing a conventional bump-line (BOL) structure; FIG. 1B is a top view showing the relationship between the line and the solder resist opening in FIG. 1A; FIG. 1C is a view showing formation A schematic view of the solder resist residue remaining in the opening of the solder resist layer in FIG. 1A.

2A to 2F are cross-sectional views showing a method of fabricating a printed circuit board according to an embodiment of the present invention.

Fig. 3 is a top plan view showing the relationship between the line, the surface treatment layer and the opening of the solder resist layer in Fig. 2F.

4A to 4F are cross-sectional views showing a method of fabricating a printed circuit board according to another embodiment of the present invention.

Fig. 5 is a top plan view showing the relationship between the line, the surface treatment layer and the opening of the second solder resist layer in Fig. 4F.

6A to 6E are cross-sectional views showing a method of fabricating a wiring layer according to an embodiment of the present invention.

The following is a detailed description of the embodiments and examples accompanying the drawings, which are the basis of the present invention. In the drawings or the description of the specification, the same reference numerals are used for the same or the same parts, and in the drawings, the shape or thickness of the embodiment can be enlarged and indicated in a convenient and simplified manner. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and in particular, The examples are merely illustrative of specific ways of using the invention and are not intended to limit the invention.

Referring first to FIG. 2F, a cross-sectional view of a printed circuit board in accordance with an embodiment of the present invention is shown. In this embodiment, the printed circuit board includes a substrate 100, a wiring layer 102, an insulating layer 108, a solder resist layer 110, a plurality of surface treatment layers 114, and a plurality of solder balls 116. The circuit layer 102 is formed on the substrate 100, which may be a single layer or a plurality of circuit layers. If the circuit layer 102 is a multilayer circuit layer, the inner circuit layer 102a, the outer circuit layer 102c, and the inner and outer layers may be electrically connected. Via plugs 102b of circuit layers 102a and 102c. The outer wiring layer 102c includes at least one contact pad 104 and a plurality of lines 106, wherein the wiring 106 is used to form an electrical connection with a subsequently formed solder bump (ie, a bump on line (BOL) structure). The insulating layer 108 is formed on the wiring layer 102 and has a plurality of first openings 108a for respectively burying the contact pads 104 and the wiring 106 in the outer wiring layer 102c and exposing the upper surfaces of the contact pads 104 and the wiring 106. The solder resist layer 110 is formed on the wiring layer 102 and the insulating layer 108, and has a plurality of second openings 112 corresponding to the lines 106 in the outer wiring layer 102c, respectively. The surface treatment layer 114 corresponds to the line 106 disposed in each of the second openings 112, and the solder balls 116 are correspondingly disposed on each of the surface treatment layers 114. Referring to FIG. 3 together, a top view of the relationship between the line 106, the surface treatment layer 114 and the solder resist opening (ie, the second opening 112) in FIG. 2F is shown. In the present embodiment, each of the lines 106 and the respective surface treatment layers 114 have substantially the same line width W1 which is smaller than the aperture D1 of each of the second openings 112 of the solder resist layer 110.

2A to 2F are cross-sectional views showing a method of fabricating a printed circuit board according to an embodiment of the present invention. Please refer to Figures 2A to 2F in order.

As shown in FIG. 2A, a substrate 100, such as a core board, is provided. The substrate 100 has a first surface 100a (eg, a wafer surface) and a first surface Two surfaces 100b (eg, welded faces). In some embodiments, the material of the substrate 100 may include a paper phenolic resin, a composite epoxy resin, a polyimide resin, a glass fiber, or the like. The core material of the conventional core.

Next, one or more circuit layers 102 are formed on the first surface 100a of the substrate 100. If the circuit layer 102 is a multilayer circuit layer, the inner circuit layer 102a, the outer circuit layer 102c, and the inner and outer lines may be electrically connected. The via plugs 102b of layers 102a and 102c. The outer wiring layer 102c includes at least one contact pad 104 and a plurality of lines 106, wherein the wiring 106 is used to form an electrical connection with a subsequently formed solder bump (ie, a bump wiring (BOL) structure). It should be understood that one or more circuit layers may be formed on the second surface 100b of the substrate 100, and the substrate 100 may have one or more conductive via electrodes 101 for electrically connecting the first surface 100a. A circuit layer (not labeled) on the circuit layer 102 and the second surface 100b. The circuit layer 102 and the conductive via electrodes 101 can be fabricated by a conventional printed circuit board process, and will not be described herein.

As shown in FIG. 2B, an insulating layer 108 is formed over the wiring layer 102 to cover the contact pads 104 and the lines 106 in the outer wiring layer 102c. In some embodiments, the material of the insulating layer 108 may include an epoxy resin, a bismaleimide triacine (BT), an ABF film (Ajinomoto built-up film), Polyphenylene (PPE), or polytetrafluorethylene (PTFE), and the formation method of the insulating layer 108 may be coating or thermocompression bonding.

As shown in FIG. 2C, the insulating layer 108 is etched back to expose the upper surface of the outer wiring layer 102c (contact pads 104 and lines 106) of the wiring layer 102. In this In an embodiment, the insulating layer 108 may be etched back by physical grinding or chemical mechanical polishing (CMP) such that the upper surface of the insulating layer 108 and the exposed outer wiring layer 102c are substantially Coplanar. In addition, in some embodiments, the upper surface of the insulating layer 108 and the outer wiring layer 102c may be further cleaned by chemical etching or plasma etching to make the subsequently formed structural layer and the insulating layer 108 and the outer wiring layer 102c. The degree of bonding can be increased.

As shown in FIG. 2D, a solder resist layer 110 is formed on the insulating layer 108 and the wiring layer 102, wherein the solder resist layer 110 has a plurality of (second) openings 112 corresponding to the lines 106 in the outer wiring layer 102c. In some embodiments, the solder resist layer 110 may be photosensitive, sensible heat, or a combination thereof. For example, the solder resist layer 110 may be a green paint, such as an ultraviolet type green paint or a heat hard green paint. The solder resist layer 110 may be formed by coating or dry film bonding, and the opening 112 is formed in the solder resist layer 110 through an exposure and development process.

As shown in FIG. 2E, a surface treatment layer (or conductive bump) 114 is formed on the exposed line 106 in each opening 112 of the solder resist layer 110 to prevent oxidation of the line 106 and increase subsequent formation. The bonding ability of the solder ball 116 (Fig. 2F). In some embodiments, the material of the surface treatment layer 114 may include copper, titanium, electroless nickel/gold, nickel immersion gold (ENIG), enamel immersion gold (ENEPIG), electroless tin plating (Immersion Tin), or The organic solder resist film (OSP), and the surface treatment layer 114 may be formed by electroless plating.

As shown in FIG. 2F, a solder ball 116 is formed on each surface treatment layer. In some embodiments, the material of the solder ball 116 may include tin, tin lead, Tin-silver-copper, tin-copper, tin-bismuth, tin-bismuth-nickel or alloys of the above.

According to the manufacturing method disclosed in the above 2A to 2F, the fabrication of the printed circuit board according to an embodiment of the present invention can be accomplished. It should be particularly noted that, in the present embodiment, when the (second) opening 112 in the solder resist layer 110 is formed by the exposure and development method, the line 106 in the outer layer wiring layer 102c corresponding to the opening 112 is buried in the insulating layer. 108, so that the flow of the developer solution is not hindered, so that the portion of the developer solution and the corresponding opening 112 of the solder resist layer 110 can smoothly and completely function, leaving the solder resist residue at the bottom of the opening 112, which is advantageous. Improve the yield and reliability of subsequent packaging of printed circuit boards (especially printed circuit boards with bump wiring (BOL) structures).

Next, please refer to FIG. 4F, which shows a cross-sectional view of a printed circuit board according to another embodiment of the present invention, wherein components identical to those of FIG. 2F are given the same reference numerals. In this embodiment, the printed circuit board includes a substrate 100, a wiring layer 102, a first solder resist layer 109, a second solder resist layer 110, a plurality of surface treatment layers 114, and a plurality of solder balls 116. The circuit layer 102 is formed on the substrate 100, which may be a single layer or a plurality of circuit layers. If the circuit layer 102 is a multilayer circuit layer, the inner circuit layer 102a, the outer circuit layer 102c, and the inner and outer layers may be electrically connected. The via plugs 102b of the circuit layers 102a and 102c. The outer wiring layer 102c includes at least one contact pad 104 and a plurality of lines 106, wherein the wiring 106 is used to form an electrical connection with a subsequently formed solder bump (ie, a bump wiring (BOL) structure). The first solder resist layer 109 is formed on the circuit layer 102 and has a plurality of first openings 109a for respectively embedding the contact pads 104 and the lines 106 in the outer circuit layer 102c and exposing the upper surfaces of the contact pads 104 and the lines 106. . The second solder resist layer 110 is formed on the circuit layer 102 and the first solder resist layer 109, and has a plurality of second openings 112, corresponding to the line 106 in the outer circuit layer 102c, respectively. The surface treatment layer 114 corresponds to the line 106 disposed in each of the second openings 112, and the solder balls 116 are correspondingly disposed on each of the surface treatment layers 114. Referring to FIG. 5 together, it is a top view showing the relative relationship between the line 106, the surface treatment layer 114 and the second solder resist opening (ie, the second opening 112) in FIG. 4F. In the present embodiment, each of the lines 106 and the surface treatment layers 114 generally have the same line width W2 which is smaller than the aperture D2 of each of the second openings 112 of the second solder mask layer 110.

4A to 4F are cross-sectional views showing a method of fabricating a printed circuit board according to another embodiment of the present invention, wherein components identical to those of Figs. 2A to 2F are given the same reference numerals and their description will be omitted. Please refer to Figures 4A to 4F in order.

As shown in FIG. 4A, in the same manner as the second embodiment of the foregoing embodiment, a substrate 100 is provided, and a circuit layer 102 is formed on the substrate 100. The circuit layer 102c of the circuit layer 102 includes at least one contact pad 104. And a plurality of lines 106, wherein the lines 106 are used to form an electrical connection with a subsequently formed solder bump (ie, a bump wiring (BOL) structure).

As shown in FIG. 4B, a first solder resist layer 109 is formed on the wiring layer 102 to cover the contact pads 104 and the wiring 106 in the outer wiring layer 102c. In some embodiments, the first solder mask layer 109 may be photosensitive, sensible heat, or a combination thereof. For example, the first solder resist layer 109 may be a green paint, such as an ultraviolet type green paint or a heat hard green paint. . The first solder resist layer 109 may be formed by coating or dry film pressing.

As shown in FIG. 4C, the first solder resist layer 109 is etched back to expose the upper surface of the outer wiring layer 102c (contact pads 104 and lines 106) of the wiring layer 102. In this embodiment, the first solder resist layer 109 may be etched back by physical brushing or chemical mechanical polishing to make the first solder resist layer 109 and the exposed outer layer layer 102c The upper surface is generally coplanar. In addition, in some embodiments, the upper surfaces of the first solder resist layer 109 and the outer wiring layer 102c may be further cleaned by chemical etching or plasma etching to make the subsequently formed structural layer and the first solder resist layer 109 and The degree of bonding between the outer wiring layers 102c can be improved.

As shown in FIG. 4D, a second solder resist layer 110 is formed on the first solder resist layer 109 and the circuit layer 102, wherein the second solder resist layer 110 has a plurality of (second) openings 112 corresponding to the outer circuit layer. Line 106 in 102c. In some embodiments, the second solder resist layer 110 and the first solder resist layer 109 may have the same material. For example, the second solder resist layer 110 may be green paint, such as ultraviolet green paint or heat hard green paint. Wait. The second solder resist layer 110 may be formed by coating or dry film pressing, and the opening 112 is formed in the second solder resist layer 110 through an exposure and development process.

As shown in FIG. 4E, in the step of FIG. 2E of the foregoing embodiment, a surface treatment layer (or conductive) is formed on the exposed line 106 in each opening 112 of the second solder resist layer 110. Bumps 114 to prevent oxidation of line 106 and increase the bonding capability of subsequently formed solder balls 116 (Fig. 4F). Next, as shown in FIG. 4F, a solder ball 116 is formed on each of the surface treatment layers in the same manner as in the second embodiment of the foregoing embodiment.

According to the manufacturing method disclosed in the above 4A to 4F, the fabrication of the printed circuit board of another embodiment of the present invention can be completed. Similar to the foregoing embodiment (Figs. 2A to 2F), in the present embodiment, when the (second) opening 112 in the second solder resist layer 110 is formed by the exposure developing method, the outer layer wiring layer 102c corresponding to the opening 112 The line 106 is buried in the first solder resist layer 109, so that the flow of the developer solution is not blocked, so that the portion of the developing potion and the corresponding opening 112 of the second solder resist layer 110 can smoothly and completely function without leaving Lower solder resist residue in opening 112 At the bottom, it is beneficial to improve the yield and reliability of subsequent packaging of printed circuit boards (especially printed circuit boards with bump wiring (BOL) structures).

6A to 6E are cross-sectional views showing a method of fabricating a circuit layer according to an embodiment of the present invention, wherein components similar to those of FIGS. 2A and 4A are denoted by the same reference numerals and the description thereof will be omitted. Please refer to Figures 6A to 6E in order.

As shown in FIG. 6A, an inner wiring layer 102a is formed on the first surface 100a of the substrate 100, and an insulating layer 103 is formed on the substrate 100 and the inner wiring layer 102a. In some embodiments, the material of the insulating layer 103 may include an epoxy resin, a bismaleimide triacine (BT), an ABF film (Ajinomoto built-up film), Polyphenylene (PPE) or polytetrafluoroethylene (PTFE), and the formation method of the insulating layer 103 may be coating or thermocompression bonding. It should be understood that one or more circuit layers may be formed on the second surface 100b of the substrate 100, and the substrate 100 may have one or more conductive via electrodes 101 for electrically connecting the first surface 100a and the first surface. The circuit layer on the surface 100b.

As shown in FIG. 6B, at least one opening 102d is formed in the insulating layer 103, and the inner layer wiring layer 102a is connected, and a seed layer 115 is conformally formed on the insulating layer 103 and the opening 102d. In some embodiments, the seed layer 115 and the inner wiring layer 102a may have the same material, including copper, tin, nickel, aluminum, chromium, titanium, tungsten, the above alloy, or a combination thereof, and the seed layer 115 The formation method may be physical vapor deposition, chemical vapor deposition, sputtering, or electroless plating.

As shown in FIG. 6C, a mask pattern layer 117 is formed on the seed layer 115, wherein the mask pattern layer 117 has a plurality of openings 118 to expose the opening 102d and a portion of the seed layer 115. In some embodiments, the mask pattern layer 117 can include A photosensitive material, such as a photoresist or a dry film, and an opening 118 is formed in the mask pattern layer 117 through an exposure development process.

As shown in Fig. 6D, a metal layer 119 is formed in the opening 118 and the exposed portion of the seed layer 115, respectively, and is filled in the opening 102d. In some embodiments, the metal layer 119 and the seed layer 115 may have the same material, and the metal layer 119 may be formed by electroplating or electroless plating. For example, the seed layer 115 can be used as an electrode and an electroplating process can be performed to form a metal layer (ie, a plated metal layer) 119 within each opening 118.

Next, as shown in FIG. 6E, the mask pattern layer 117 and the seed layer 115 under it can be sequentially removed by a conventional stripping method and an etching process to complete the outer layer layer 102c (contact pads 104 and lines). 106) production.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. Those skilled in the art having the ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Substrate

100a‧‧‧ first surface

100b‧‧‧ second surface

101‧‧‧conductive via electrodes

102‧‧‧Line layer

102a‧‧‧ Inner layer

102b‧‧‧Interlayer plug

102c‧‧‧ outer circuit layer

104‧‧‧Contact pads

106‧‧‧ lines

109‧‧‧First solder mask

109a‧‧ first opening

110‧‧‧Second solder mask

112‧‧‧Second opening, opening

114‧‧‧Surface treatment layer

116‧‧‧ solder balls

W2‧‧‧ line width

Claims (11)

A manufacturing method of a printed circuit board, comprising: providing a substrate; forming a circuit layer on the substrate, wherein the circuit layer comprises a plurality of lines; forming an insulating layer on the circuit layer; etching the insulating layer to expose Forming an upper surface of the circuit layer; forming a solder resist layer on the insulating layer and the circuit layer, wherein the solder resist layer has a plurality of openings respectively corresponding to the lines of the circuit layer, and lines of the respective lines a width that is smaller than the apertures of the openings; and a surface treatment layer formed on each of the lines. The method of fabricating a printed circuit board according to claim 1, wherein the insulating layer is etched back to expose the upper surface of the circuit layer by physical brushing or chemical mechanical polishing. The method for fabricating a printed circuit board according to claim 1 or 2, wherein in the step of etching back the insulating layer to expose an upper surface of the wiring layer, the method further comprises: etching back the insulating layer to The upper surface of the wiring layer is coplanar; and the insulating layer and the upper surface of the wiring layer are cleaned by chemical etching or plasma etching. A manufacturing method of a printed circuit board, comprising: providing a substrate; forming a circuit layer on the substrate, wherein the circuit layer comprises a plurality of lines Forming a first solder resist layer on the circuit layer; etching back the first solder resist layer to expose an upper surface of the circuit layer; forming a second on the first solder resist layer and the circuit layer a solder resist layer, wherein the second solder resist layer has a plurality of openings respectively corresponding to the lines of the circuit layer, and a line width of each of the lines is smaller than an aperture of each of the openings; and forming on each of the lines A surface treatment layer. The method of fabricating a printed circuit board according to claim 4, wherein the etching the first solder resist layer to expose the upper surface of the circuit layer is achieved by physical brushing or chemical mechanical polishing. The manufacturing method of the printed circuit board of claim 4, wherein in the step of etching back the first solder resist layer to expose the upper surface of the circuit layer, the method further comprises: The solder layer is etched back to be coplanar with the upper surface of the wiring layer; and the first solder resist layer and the upper surface of the wiring layer are cleaned by chemical etching or plasma etching. The method for fabricating a printed circuit board according to claim 1 or 4, wherein a surface treatment layer is formed on each of the lines by electrodeless plating, and the materials of the surface treatment layers include copper. , titanium, electroless nickel/gold, nickel immersion gold (ENIG), nickel-palladium immersion gold (ENEPIG), electroless tin plating (Immersion Tin), or organic solder mask (OSP). The method for manufacturing a printed circuit board according to claim 1 or 4, further comprising: A solder ball is formed on each of the surface treatment layers. A printed circuit board comprising: a substrate; a circuit layer on the substrate, the circuit layer comprising a plurality of lines; an insulating layer on the circuit layer, the insulating layer having a plurality of first openings for respectively exposing An upper surface of the circuit; a solder resist layer on the circuit layer and the insulating layer, the solder resist layer having a plurality of second openings respectively corresponding to the lines, wherein each of the lines has a line width smaller than each The apertures of the second openings; and a plurality of surface treatment layers are respectively located on the lines. A printed circuit board comprising: a substrate; a circuit layer on the substrate, the circuit layer comprising a plurality of lines; a first solder resist layer on the circuit layer, the first solder resist layer having a plurality of An opening to respectively expose upper surfaces of the lines; a second solder resist layer on the circuit layer and the first solder resist layer, the second solder resist layer having a plurality of second openings respectively corresponding to And a line, wherein each of the lines has a line width smaller than an aperture of each of the second openings; and a plurality of surface treatment layers are respectively located on the lines. The printed circuit board of claim 9 or 10, further comprising: a plurality of solder balls respectively located on the surface treatment layers.