0611002 22553twf.doc/n 九、發明說明： 【發明所屬之技術領域】 種線路板製程（Circuit Board 於一種具有導電孔之内埋式線路 本發明是有關於— Process)，且特別是有關 板製程。 【先前技術】 (dt隨電子工業之生產技術的突飛猛進，線路板 (C_t BGard)可搭載各種體積精巧之電子零件，以廣 泛地應祕各種不同功能的電子產品 之0611002 22553twf.doc/n IX. Description of the invention: [Technical field of the invention] A circuit board process (Circuit Board in a buried circuit with conductive holes is described in the present invention), and particularly related to the board process . [Prior Art] (Dt with the rapid advancement of the production technology of the electronics industry, the circuit board (C_t BGard) can carry a variety of compact electronic components to cover a wide range of electronic products with different functions.
r:製作過程。請參她至圖二至圖F =包=:路;。習知之線路 mm/ 圖A所示，提供一基板 人八 土板110具有一介電層112以及二銅箔層114, "電層112配設於二銅箔層114之間。麸 示，以機械鑽孔之方式於基板110上形成、一通孔f20。所 接者’如圖1C所示，利用電鍍製程於銅箱層114以 上形成—導電層13G’導電層⑽係可電 電層112兩側之線路。緊接著，如圖1D所示， / Μ ’曰130上形成一圖案化光阻層140，其中圖案化光 露出部份導電層130。接著，如圖1£所示’以 声Μ 〇最ΐ層14 0為罩幕，並利用餘刻技術對圖案化光阻 路Γ份導電層130以及銅箱層114進行圖案化 _ J，圖案化導電層13G’以及圖案化_層114,， Θ案匕V電層i3G，以及圖案化銅溶層114，即構成一圖案 1343110 061J 002 22553twf.doc/n =線路層15〇。之後，如圖1F所示，移除圖案化光阻層 140 ’以完成習知之線路板100的製作。 提的是，在频電路的設計純複雜以及愈趨 精細的情況下，祕板k線路設計亦愈職細。然而，r: The production process. Please refer to her to Figure 2 to Figure F = package =: road; The conventional circuit mm/FIG. A provides a substrate for the earthboard 110 having a dielectric layer 112 and a two-copper layer 114. The electrical layer 112 is disposed between the two copper foil layers 114. In the bran, a through hole f20 is formed on the substrate 110 by mechanical drilling. As shown in Fig. 1C, the electroconductive layer (13) is formed on the copper box layer 114 by an electroplating process to form a conductive layer (10) on both sides of the electro-optic layer 112. Next, as shown in Fig. 1D, a patterned photoresist layer 140 is formed on /?' 130, wherein the patterned light exposes a portion of the conductive layer 130. Next, as shown in FIG. 1 'the squeaking 〇 〇 14 14 14 14 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The conductive layer 13G' and the patterned layer 114, the patterned germanium V electrical layer i3G, and the patterned copper soluble layer 114 form a pattern 1343110 061J 002 22553twf.doc/n = circuit layer 15A. Thereafter, as shown in FIG. 1F, the patterned photoresist layer 140' is removed to complete the fabrication of the conventional wiring board 100. It is mentioned that in the case where the design of the frequency circuit is purely complex and finer, the design of the secret circuit k is also more and more detailed. however,
在上述形成圖案化線路層15〇之過程中，習知技術係應用 钱刻製程來移除圖案化光阻層刚暴露之部份導電層^ ，_層114’以製作出圖案化線路層15〇。其中，θ由於 銅清層114以及材質例如是銅之導電㉟13〇在形成過程中 其厚度有較大之變異性（即圖案化線路層15〇之表面較不 平整）’且習知技術無法穩定地控制姓刻變異性（敍刻液對 銅箱層m以及導電们30之姓刻程度），因此習知技術製 作出之圖案化線路層15〇其祕寬度不Μ合細線路之規 格(餘刻液會對銅闕114以及導電層13G過度㈣而導致 ，路寬度不易符合細線路之規格）。換言之，f知之線路板 衣程不易製作出具有細線路之線路板。此外，在習知技術 中’圖案化線路層150與介電層112間僅具有一接觸面， 因此習知之®案化線路層15G容易因不當之外力而自介電 層112上剝落，導致線路板1〇〇之可靠度降低。 此外，在後續的晶片封裝製程中，由於圖案化線路層 150之表面較不平整。因此，當晶片配設於線路板⑽上 時’晶片無法有效地與線路板100接合，造成晶片與線路 板100間之電性連接品質不佳。另一方面，由於圖案化線 路層之表料平整’因此當W配設於線路板i⑽時，晶 片與線路板100間之接觸應力分布即不平均，進而影響晶 0611002 22553twf.doc/n 片封裝結構之可靠度。 【發明内容】 本發明是提供一種具有導電孔之内埋式線路板製 铋，其製作出具有較佳可靠度之線路板，且線路板 較佳之平做，叫效軸接合。叛表面有 為達上述或是其他目的，本發明提出一種具有導電孔 ^埋式線路板製程，其包括下财驟：首先，提供-内 二L線路基板，其包括—介電層、—第—線路層以及—第 二枣路層。其中，介電層具有相對應之一第一表面與一第 側線路層内埋於第一表面’且第一線路層之外 面，且μ第—表面共平面，而第二線路層内埋於第二表 於内埋^二線路層之外側表面與第二表面共平面。然後， 第二表式線路基板上形成一開孔。接著，於該第一表面、 一表^面^及開孔之内壁上形成一導電層。之後，移除第 電孔。第—表面上以及開孔外側之導電層，以形成一導 開孔^本發明之—實施例中，於第—表面、第二表面以及 第〜表内壁^形成導電層之方式包括下列步驟：首先，於 層。、第二表面以及開孔之内壁上形成一電鍍種子 電鮮展I於電鍵種子層上形成一電链層，*導電層包括 又曰以及電鍍種子層。 ^本發明之一實施例中，電鍍種子層為化學銅層。 開孔之^明之—實施例中，於第—表面、第二表面以及 壁上形成導電層之後更包括下列步驟：首先，於 1343110 0611002 22553twf.doc/n 開孔中填充一絕緣材料。接著，移除 # _ 上以及開孔外側之導電層。之後 二面、第二表面 與第二表面共平面。 H緣材料與第-表面 在本發明所製作出之線路板中 層之第-表面與第二表面，且線路層之外==介; 第二Γ共平面，而導電層則是配電 本發明所製作出之之内埋式線=較= 内埋於介電層之第-表面以及第二夺而由於上逑線路層係 電層之間有較佳之接合性質。另外:由於與介 介電層中，因此本發明在製作具有 =^層疋内埋於 時，線路層之線路寬度即不易受到製埋式線路板 影響，即線路層之線路寬度能符合細線路之Hi刻液 本發明能製作出品質錄之細祕板。袼。換S之’ 易懂i 他目的、特徵和優點能更明顯 明如下了文特舉實施例，並配合所_式，作詳細說 【實施方式】 圖2繪示為本發明較佳實施例之一 埋式線路_製作流程圖。¥電孔之内 式線路板製程包括下列步驟圖執=實施例之内埋 内埋式線路基板。接菩： 執仃步驟L提供- 上形成—開孔。然^執内埋式線路基板 执仃步驟S3’於内埋式線路基板之 0611002 22553twf.doc/n 第-表面、第二表面以及開孔内壁上形成一導電層。之後， t行步驟S4,移除第—表面、第二表面上以及開孔外側之 ^電層’ 導電孔。下文中，本實施娜以詳細之 々IL私剖面圖來說明上述之線路板製程。 圖3A至：3E纟會不為@ 2之具有導電孔之内埋式線路板 ’程剖賴。此内埋式線路板的製作方法如下所述：首 ，，如圖3A所示，提供一内埋式線路基板21〇，其包括— 二電層212、-第-線路層214以及—第二線路層216。复 中，介電層2U料相對應之一第—表面212&與一第二^ 面12b而第一線路層214是内埋於第一表面212a，且第 了線路層214之外側表面與第一表面212a共平面。此外， 第線路層216是内埋於第二表面212b，且第二線路層216 之外側表面與第二表面21沘共平面。接著，如圖3B所示， 於内埋式線路基板21G上形成-開孔22G。舉例來說，開 ^ 220可以是一通孔（through hole)或是一盲孔（blind 22〇圖3B繪示之開孔220係以通孔為例，而形成開孔 方式可以是機械鑽孔、雷射燒孔或是其他適當之方 式0 於内埋式線路基板210上形成開孔220之後，接著如 圖3C至闇。〇 ^ D所示’於第一表面212a、第二表面212b以 及開孔^ < $ ϋ之内壁上形成一導電層230。在本實施例中， ^ V电層230例如是包括下列步驟：首先，如圖3c所 示，於第〜士 不表面212a、第二表面212b以及開孔220之内 土上七成〜電鍍種子層232。其中，電鍍種子層232例如 0611002 22553twf.d〇c/i 疋利用化學銅製程而形成於第—表面212a、第二表面幻此 以及開孔220内壁上之化學鋼層。接著，如圖3D所示， 於電鍍種子層232上形成一電鍍層234。電鍍層234例如 是藉由電鍍製程而形成之一電鍍鋼層，而本實施例之導電 層230即包括電鍍種子層232以及形成於電鍍種子層232 上之電鍍層234。 於第一表面212a、第二表面212b以及開孔220内壁 上形成導電層230之後，接著如圖3E所示，移除第一表 面212a、第二表面212b上以及開孔22〇外側之導電層 230。舉例來說，本實施例可以利用機械研磨或是化學研磨 等適當方式來移除第一表面212a、第二表面2l2b上以及 開孔220外側之導電層230。在執行圖3E之步驟後，導電 層230僅配設於開孔220内壁，且分佈於第一線路層214 以及第二線路層216之側面，以電性連接第一線路層214 與第二線路層216。如此一來，内埋式線路板2〇〇即具有 一電性連接第一線路層214與第二線路層216之導電孔 240。此外，本實施例可以有效地改善習知之線路板表面不 平整之問題（線路板之表面不平整是由導電層之形成厚度 變異性所導致）。換言之，本實施例之内埋式線路板2〇〇 即具有較佳之表面平整度。 此外，為防止外界環境之水氣進入開孔230中，造成 爆米花效應（Popcorn Effect)。在另一較佳實施例中，在第 一表面212a、第二表面212b以及開孔220之内壁上形成 導電層230(如圖3D所示）之後可以於開孔220中填充一例 0611002 22553twf.doc/n 如疋油墨的絕緣材料250(如圖4A所示），以防止爆米花效 應劣化内埋式線路板。當然，於開孔22〇中填充絕緣材料 250之後，本實施例同樣可利用機械研磨或是其他適當之 方式來移除第一表面212a、第二表面212b上、開孔22〇 外侧之導電層230以及部份位於開孔22〇外側之絕 离如圖4B戶斤示），以使填充於開孔22〇之絕緣材料材= 與第-表面212a與第二表面212b共平面。換言之，本者 施例之内埋式線路板，除了有較佳之表面平整度之外1 本實施例絲有效地防止爆純效應劣㈣埋魏路板。 亦即，本實_之_續路板·，機狀結構 綜上所述，本發明是於一内埋式線路基板中製作一又導 層。相_知技術， 介電細埋於 線路層具有較佳之;^之本發明之内埋式線路板其 (二）由於本發明之線路層是内埋於介電層中 製作具有導電孔之内埋式線路板時，線路 j衣私所應用之_液作用而影響到線路層ς j又 線路層之線路寬度即能符合細線路之規格。換Ί ^ 明所製作出之内埋式線路板為具有較佳品質之二路本么 (三)在本發明中，線路層是内埋於介電d 與弟二表面，且線路層之外側表d 1343110 0611002 22553twf.d〇c/n 導is ^外’電性連接介電層兩側之導電層僅配叹於 :)在^明之内埋式線路板有較^ 整之表面心二由於本發明之内埋式線路板有較平 地與内埋式線路板接合日片 日日片此有效 較佳之電性連接品質。此外片路板之間即具有 有較平敕W 卜由於本發明之㈣式線路板 片與“：此當晶片配置於内埋式線路板時，晶 之，即具妹平均之應力分佈。換言 之可靠度。/、埋式線路板所構成之晶片封裝結構有較佳 限定發明已以較佳實施例揭露如上，然其並非用以 和範圍^何㈣此技藝者，在*麟本發明之精神 y當，::ΪΓΐ==者::本發明之保護 【圖式簡單說明】 面圖圖1Α至圖IF繪示為習知之—種線路板製程的流程剖 圖2繪示為本發明較佳實施例之一種具有導電孔之内 式線路板的製作流程圖。 圖3A至3E %示為圖2之具有導電孔之内埋式線 程剖面圖。 圖4A至4B繪示為本發明較佳實施例之另一種具有導 之内埋式線路板的部分製程剖面圖。 12 1343110In the above process of forming the patterned wiring layer 15 , a conventional technique is applied to remove a portion of the conductive layer _ layer 114 ′ that has just been exposed by the patterned photoresist layer to form a patterned wiring layer 15 . Hey. Where θ is due to the copper clad layer 114 and the material such as copper, the conductive 3513 其 has a large variability in the thickness of the formation process (ie, the surface of the patterned circuit layer 15 较 is not flat) and the conventional technology cannot be stabilized. The ground control of the singularity of the surname (the degree of engraving of the copper box layer m and the conductivity of the conductors 30), so the patterned circuit layer 15 made by the prior art does not conform to the specifications of the thin line. The engraving will be caused by the copper crucible 114 and the conductive layer 13G being excessive (four), and the road width is not easy to conform to the specifications of the fine line). In other words, it is difficult to fabricate a circuit board having a thin line. In addition, in the prior art, there is only one contact surface between the patterned circuit layer 150 and the dielectric layer 112, so that the conventional circuit layer 15G is easily peeled off from the dielectric layer 112 due to improper external force, resulting in a line. The reliability of the board 1 is reduced. In addition, in the subsequent wafer packaging process, the surface of the patterned wiring layer 150 is less flat. Therefore, when the wafer is disposed on the wiring board (10), the wafer cannot be effectively bonded to the wiring board 100, resulting in poor electrical connection quality between the wafer and the wiring board 100. On the other hand, since the surface of the patterned circuit layer is flat, the contact stress distribution between the wafer and the circuit board 100 is uneven when W is disposed on the circuit board i (10), thereby affecting the crystal 0611002 22553 twf.doc/n chip package. The reliability of the structure. SUMMARY OF THE INVENTION The present invention provides a buried circuit board made of conductive holes, which is manufactured with a circuit board having better reliability, and the circuit board is preferably made flat and called a shaft joint. The invention has a process for achieving the above-mentioned or other purposes, and the present invention provides a process for conducting a buried circuit board, which includes the following steps: First, an inner-two L-line substrate is provided, which includes a dielectric layer, - the circuit layer and the second jujube layer. Wherein the dielectric layer has a corresponding one of the first surface and a first side circuit layer buried in the first surface 'and outside the first circuit layer, and the μ first surface is coplanar, and the second circuit layer is buried in The second surface is coplanar with the second surface on the outer side surface of the buried circuit layer. Then, an opening is formed on the second surface circuit substrate. Then, a conductive layer is formed on the first surface, a surface, and an inner wall of the opening. After that, remove the electric hole. The first surface and the conductive layer on the outside of the opening to form a conductive opening. In the embodiment, the manner of forming the conductive layer on the first surface, the second surface and the inner surface of the first surface includes the following steps: First, at the layer. Forming an electroplated seed on the second surface and the inner wall of the opening, forming an electric chain layer on the electric seed layer, and the electroconductive layer comprises a crucible and a plating seed layer. In one embodiment of the invention, the electroplated seed layer is a chemical copper layer. In the embodiment, after forming the conductive layer on the first surface, the second surface and the wall, the method further comprises the following steps: First, filling an opening material in the opening of the 1343110 0611002 22553 twf.doc/n. Next, remove the conductive layer on # _ and outside the opening. Thereafter, the second surface and the second surface are coplanar with the second surface. The H-edge material and the first surface are on the first surface and the second surface of the middle layer of the circuit board produced by the present invention, and the circuit layer is outside the ===; the second Γ is coplanar, and the conductive layer is the power distribution device of the present invention. The buried line produced is = the inner surface of the dielectric layer is buried and the second layer is better because of the better bonding properties between the electrical layers of the upper layer. In addition, since the present invention is embedded in the dielectric layer, the line width of the circuit layer is not easily affected by the buried circuit board, that is, the line width of the circuit layer can conform to the fine line. Hi Engraving The present invention can produce a fine board of quality records. Hey. For the sake of understanding, the purpose, the features and the advantages of the present invention will be more apparent. The following is a detailed description of the embodiments, and is described in detail with reference to the embodiments. FIG. 2 illustrates a preferred embodiment of the present invention. A buried line _ production flow chart. The inner circuit board process of the electric hole includes the following steps: the embedded buried circuit substrate in the embodiment. Connected to Bodhisattva: Stubborn Step L provides - Forming - Opening. Then, the embedded circuit substrate is subjected to step S3' to form a conductive layer on the inner surface of the buried circuit substrate, the surface of the second surface, the second surface, and the inner wall of the opening. Thereafter, step S4 is performed to remove the conductive holes on the first surface, the second surface, and the outer side of the opening. Hereinafter, the present embodiment describes the above-described circuit board process by a detailed 々IL private sectional view. Figure 3A to: 3E纟 will not be @2's buried circuit board with conductive holes. The method for fabricating the buried circuit board is as follows: First, as shown in FIG. 3A, an embedded circuit substrate 21 is provided, which includes a second electrical layer 212, a first-circuit layer 214, and a second Circuit layer 216. In the middle, the dielectric layer 2U corresponds to one of the first surface 212& and the second surface 12b, and the first circuit layer 214 is buried in the first surface 212a, and the outer surface of the first circuit layer 214 is A surface 212a is coplanar. In addition, the first wiring layer 216 is buried in the second surface 212b, and the outer surface of the second wiring layer 216 is coplanar with the second surface 21沘. Next, as shown in FIG. 3B, an opening 22G is formed on the buried wiring substrate 21G. For example, the opening 220 can be a through hole or a blind hole. The opening 220 is illustrated by the through hole. The opening can be mechanical drilling. The laser hole or other suitable manner is formed after the opening 220 is formed on the buried circuit substrate 210, and then as shown in FIG. 3C to the dark side, the first surface 212a, the second surface 212b, and the opening are shown. A conductive layer 230 is formed on the inner wall of the hole ^. In the embodiment, the ^V electrical layer 230 includes, for example, the following steps: First, as shown in FIG. 3c, at the surface of the second surface 212a, the second The surface 212b and the soil in the opening 220 are 70% to electroplated seed layer 232. The electroplating seed layer 232, for example, 0611002 22553 twf.d〇c/i 形成 is formed on the first surface 212a and the second surface by using a chemical copper process. And a chemical steel layer on the inner wall of the opening 220. Next, as shown in FIG. 3D, a plating layer 234 is formed on the plating seed layer 232. The plating layer 234 is formed, for example, by an electroplating process to form an galvanized steel layer. The conductive layer 230 of the embodiment includes a plating seed layer 232 and is formed on The plating layer 234 is plated on the seed layer 232. After the conductive layer 230 is formed on the first surface 212a, the second surface 212b, and the inner wall of the opening 220, then the first surface 212a and the second surface 212b are removed as shown in FIG. 3E. The conductive layer 230 is disposed on the outer side of the opening 22, and the conductive layer 230 on the outside of the opening 220 can be removed by a suitable method such as mechanical polishing or chemical polishing. After the step of FIG. 3E is performed, the conductive layer 230 is disposed only on the inner wall of the opening 220 and distributed on the side of the first circuit layer 214 and the second circuit layer 216 to electrically connect the first circuit layer 214 with The second circuit layer 216. The buried circuit board 2 has a conductive hole 240 electrically connected to the first circuit layer 214 and the second circuit layer 216. In addition, the embodiment can effectively improve the learning. It is known that the surface of the circuit board is not flat (the surface unevenness of the wiring board is caused by the thickness variability of the formation of the conductive layer). In other words, the buried circuit board 2 of the present embodiment has a better surface flatness. In addition, In order to prevent the moisture of the external environment from entering the opening 230, a Popcorn effect is caused. In another preferred embodiment, the conductive is formed on the inner surfaces of the first surface 212a, the second surface 212b and the opening 220. The layer 230 (shown in FIG. 3D) may then be filled with an insulating material 250 (shown in FIG. 4A) of an example of 0610102 22553 twf.doc/n, such as an ink, in the opening 220 to prevent the popcorn effect from degrading the buried wiring board. . Of course, after the insulating material 250 is filled in the opening 22, the embodiment can also remove the conductive layer on the first surface 212a, the second surface 212b, and the outside of the opening 22 by mechanical grinding or other suitable means. 230 and a portion of the outer side of the opening 22 are shown in Fig. 4B, so that the insulating material filled in the opening 22 is coplanar with the first surface 212a and the second surface 212b. In other words, in addition to the better surface flatness of the buried circuit board of the present embodiment, the wire of the present embodiment effectively prevents the explosion effect from being inferior (four) buried Wei road board. That is, the present invention is a continuation board, and the machine structure is described above. The present invention is to fabricate a conductive layer in a buried circuit substrate. Phase-known technology, dielectric buried in the circuit layer is better; ^ the buried circuit board of the present invention; (b) because the circuit layer of the present invention is buried in the dielectric layer to have conductive holes When the buried circuit board is used, the liquid layer applied by the circuit can affect the line layer and the line width of the circuit layer can meet the specifications of the fine line. In the present invention, the buried circuit board is a two-way circuit having better quality. (III) In the present invention, the circuit layer is buried in the dielectric d and the second surface, and the outer side of the circuit layer Table d 1343110 0611002 22553twf.d〇c/n Guide is ^ external 'electrically connected to the conductive layer on both sides of the dielectric layer only sigh:) in the ^ Ming within the buried circuit board has a more complete surface of the heart due to The buried circuit board of the present invention has a relatively good electrical connection quality with a flat and a buried circuit board. In addition, there is a flatness between the film boards. Because of the (four) type circuit board of the present invention and ": when the wafer is disposed on the buried circuit board, the crystal has a uniform stress distribution. In other words, Reliability. /, the chip package structure of the buried circuit board has a better definition. The invention has been disclosed above by the preferred embodiment, but it is not intended to be used in the scope of the art. y当:::ΪΓΐ==者:: The protection of the present invention [Simplified description of the drawings] FIG. 1A to FIG. IF are schematic diagrams of a conventional circuit board process. FIG. 2 is a view of the present invention. FIG. 3A to FIG. 3E are cross-sectional views of the buried thread with conductive holes of FIG. 2. FIG. 4A to FIG. 4B are diagrams showing a preferred embodiment of the present invention. Another partial process profile of a buried buried circuit board. 12 1343110
0611002 22553twf.doc/n 【主要元件符號說明】 100 :線路板 112 :介電層 114’ ：圖案化銅箔層 130 :導電層 140 :圖案化光阻層 200、200’ ：内埋式線路板 212 :介電層 212b :第二表面 216 :第二線路層 230 :導電層 234 :電鍍層 250 :絕緣材料 110 :基板 114 :銅箔層 120 :通孔 130’ ：圖案化導電層 150 :圖案化線路層 210 :内埋式線路基板 212a :第一表面 214 :第一線路層 220 :開孔 232 :電鍍種子層 240 :導電孔 S1〜S4 :各個步驟 13 (S )0611002 22553twf.doc/n [Description of main component symbols] 100: circuit board 112: dielectric layer 114': patterned copper foil layer 130: conductive layer 140: patterned photoresist layer 200, 200': buried circuit board 212: dielectric layer 212b: second surface 216: second wiring layer 230: conductive layer 234: plating layer 250: insulating material 110: substrate 114: copper foil layer 120: via 130': patterned conductive layer 150: pattern The circuit layer 210: the buried circuit substrate 212a: the first surface 214: the first circuit layer 220: the opening 232: the plating seed layer 240: the conductive holes S1 to S4: each step 13 (S)