TW200847353A - Flip chip device with ACF connections - Google Patents

Flip chip device with ACF connections Download PDF

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Publication number
TW200847353A
TW200847353A TW096119037A TW96119037A TW200847353A TW 200847353 A TW200847353 A TW 200847353A TW 096119037 A TW096119037 A TW 096119037A TW 96119037 A TW96119037 A TW 96119037A TW 200847353 A TW200847353 A TW 200847353A
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TW
Taiwan
Prior art keywords
conductive
substrate
bumps
anisotropic conductive
bonding
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Application number
TW096119037A
Other languages
Chinese (zh)
Other versions
TWI332254B (en
Inventor
Po-Chien Lee
Original Assignee
Resound Technology Inc
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Priority to TW096119037A priority Critical patent/TWI332254B/en
Publication of TW200847353A publication Critical patent/TW200847353A/en
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Publication of TWI332254B publication Critical patent/TWI332254B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body

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  • Wire Bonding (AREA)

Abstract

Disclosed is a flip chip device with ACF connections, primarily comprising a substrate, a bumped chip and a special ACF (Anisotropic Conductive Film). The ACF is interposed between the substrate and the bumped chip. The ACF contains a plurality of conductive posts in parallel, which are encapsulated in resin in a regular distribution with a same pitch. When the bumped chip is bonded to the substrate, two ends of some of the conductive posts electrically connect the bumps on the bumped chip and the substrate to achieve electrical interconnection. Utilizing the conductive posts to replace conventional conductive balls difficult to become homogenized, adjacent bumps won't generate electrical short. Furthermore, production yield of flip-chip bonding is improved, and the cost of the ACF is reduced.

Description

200847353 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種覆晶裝置，特別係有關於一種 異方性導電接合之覆晶裝置。 【先前技術】 在以在覆晶接合技術中，異方性導電接合 (anisotropic conductive bonding)是其中一種重要且不 p 可被取代的方法，相較於共晶焊接方式，異方性導電接 合係能以低溫低壓合的條件達到高密度的電性連通。然 而’目刖所採用的異方性導電接合膠膜（ACF)係在一半 固化树月曰内封设有複數個等球徑的導電球，並且該些導 電球的分散密度必須相當均勻，故異方性導電接合膠膜 的成本很高。此外，當覆晶壓合力量過大，導電球無法 順利地電性接觸晶片凸塊與基板接墊；當覆晶壓合力量 過大，導電球表面的電鍍層易於破裂，導致電性斷路， 〇 因此可作業參數範圍（即製程窗）顯得狹窄，故覆晶接合 良率與產品可靠性需要作進一步的改善。 請參閱第1圖所示，一種習知的異方性導電接合之 覆晶裝置1〇〇包含一基板11〇、一凸塊化晶片12〇以及 一異方性導電膠膜130。該基板110係具有一上表面 in、一下表面112及複數個形成於該上表面ln之接 a塾 °亥凸塊化晶片120係具有一主動面Mi及一 责面 ”中该主動面1 2 1係形成有複數個凸塊1 2 3。 該異方性導電膠膜13〇係介設於該凸塊化晶片12〇與該 200847353 基板110之間，該異方性導電膠膜13〇係包含有複數個 等球徑之導電球131。該些導電球131係被要求均勻分 散在该異方性導電膠膜1 3 0内，方可達到縱向的異方性 導電導致I程困難度相當鬲與昂貴成本。當部分之導 電球131不正常的聚集，會導致該些凸塊123之間的短 路。此外’通常該些導電球1 3 1之球體係為絕緣樹脂 球’在球外周面係電鍍包覆有一金屬層丨3 2。當覆晶接 〇 合時，該些導電球1 3 1會在該些凸塊1 23與該些接合墊 1 1 3之間被擠壓，過大的晶片壓合強度會導致被擠壓之 該些導電球131之金屬層132產生龜裂，甚至引起在該 些凸塊1 2 3與該些接合墊1 1 3之間的電性斷路。 【發明内容】 本發明之主要目的係在於提供一種異方性導電接合 之覆晶裝置，藉由複數個導電柱係為規則化等距排列並封 設於一樹脂内，作為一異方性導電膠膜，避免習知導電球 不正常聚集而導致兩相鄰之凸塊間之短路，並可提升覆 晶接合良率並降低異方性導電成本。 本發明之次一目的係在於提供一種異方性導電接合 之覆aa裂置’由於導電柱係可彎曲或穿刺入凸塊，可以 確保良好的異方性導電接合成功率，解決了習知異方性 導電膠膜内導電球表面電鍍層破裂導致電性斷路的問題。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明，一種異方性導電接合之覆晶 裝置主要包含一基板、一凸塊化晶片以及一異方性導電 6 膠 化 膜 膠 化 該 於 該 〇 措 之 接 U 些 塊 些 排 些 片 塊與對應之接 在前述的覆晶裝置中， 凸塊與對應之該些接合 與該基板的間隙。 在前述的覆晶裝置中， 200847353 膜。该基板之一表面係形成有複數個接合墊。該 晶片係一表面係形成有複數個凸塊。該異方性導 係介設於該基板與該凸塊化晶片之間，該異方性 膜係包含有複數個導電柱，其中該些導電柱係為 等距排列並封設於一樹脂内。#該凸塊化晶片'接 基板以致使該些凸塊與對應之該些接合墊之間 該些導電柱之柱高時，部分導雷知 |刀导冤柱之兩端係電性 些凸塊與對應之該些接合墊。 本發明的目的及解決其技術問題還可採用以下 施進一步實現。 在前述的覆晶裝置中，在每一凸 間係可連接有至少三個導電柱。 在前述的覆晶裝置中，上述該此 一凸塊與對應 合墊之間的部分導電柱係可產生彎曲形變。 在前述的覆晶fn上述在該些凸❹對 接合墊之間的部分導電柱之一端係可穿刺入 在前述的覆晶裝置中，上述在兮 4在該些凸塊與對應 接合勢之外的其餘導電柱係可為等間距、等長且 列0 該些導電桎的長度係大 墊的間隙且小於該凸塊 上述在該些凸塊與對應 凸塊 電膠 導電 規則 合至 隙小 連接 技術 合墊 該些 之該 些凸 之該 平行 於該 化晶 之該 7 200847353 些接合墊之外的其餘導電柱係可為電性獨立並提供該 晶片至該基板之熱耦合路徑。 在前述的覆晶裝置中’該些導電桂係可為電鑄微導 體。 在前述的覆晶裝置中，該些導電柱之材質係可選自 金、銅、鎳與上述任一組成合金之其中之一。 在前述的覆晶裝置中，該基板係可為一玻璃線路板。 f\ 在前述的覆晶裝置中’該基板係可為一電路薄膜或 一印刷電路板。 在前述的覆晶裝置中，該基板係可為一晶片或一半 導體線路板。 【實施方式】 依據本發明之第一具體實施例，揭示一種異方性導 電接合之覆晶裝置。第2圖係為該覆晶裝置之截面示意 圖。第3圖係為該覆晶裝置中複數個導電柱之位置分布 示意圖。第4A至4B圖係為該覆晶裝置於製程中一凸 塊化晶片之截面示意圖。請參閱第2圖所示，一種異方 性導電接合之覆晶裝置200主要包含一基板210、一凸 塊化晶片2 2 0以及一異方性導電膠膜2 3 〇。 如第2圖所示，該基板2丨〇係具有一上表面2丨丨及 下表面212。該基板210之該上表面211係形成有複 數個接合墊2 1 3 該基板2 1 0係可為一玻璃線路板、200847353 IX. Description of the Invention: [Technical Field] The present invention relates to a flip chip device, and more particularly to a flip chip device for anisotropic conductive bonding. [Prior Art] In the flip chip bonding technique, anisotropic conductive bonding is one of the important and non-p-replaceable methods, and the anisotropic conductive bonding system is compared to the eutectic soldering method. High-density electrical communication can be achieved under conditions of low temperature and low pressure. However, the anisotropic conductive bonding film (ACF) used in the project is sealed with a plurality of conductive balls of equal spherical diameter in a half-cured tree, and the dispersion density of the conductive balls must be fairly uniform. The cost of the anisotropic conductive bonding film is high. In addition, when the flip-chip bonding force is too large, the conductive ball cannot smoothly contact the wafer bump and the substrate pad smoothly; when the flip chip pressing force is too large, the plating layer on the surface of the conductive ball is easily broken, resulting in an electrical disconnection. The range of workable parameters (ie, the process window) appears to be narrow, so the flip chip bonding yield and product reliability need to be further improved. Referring to FIG. 1, a conventional anisotropic conductive bonding flip chip device 1A includes a substrate 11A, a bumped wafer 12A, and an anisotropic conductive film 130. The substrate 110 has an upper surface in, a lower surface 112, and a plurality of abutting bumps 120 formed on the upper surface ln having an active surface Mi and an active surface. 1 is formed with a plurality of bumps 1 2 3 . The anisotropic conductive film 13 is interposed between the bumped wafer 12 and the 200847353 substrate 110, and the anisotropic conductive film 13 is The conductive ball 131 includes a plurality of equal-spherical conductive balls 131. The conductive balls 131 are required to be uniformly dispersed in the anisotropic conductive film 130 to achieve longitudinal anisotropy conduction, resulting in difficulty in the I-path.鬲 and expensive cost. When some of the conductive balls 131 are abnormally aggregated, a short circuit between the bumps 123 is caused. In addition, 'the ball system of the conductive balls 133 is usually an insulating resin ball' on the outer circumference The electroplating is coated with a metal layer 丨3 2 . When the flip chip is bonded, the conductive balls 133 are squeezed between the bumps 1 23 and the bonding pads 1 1 3 , which are too large. The wafer press-bonding strength causes the metal layer 132 of the conductive balls 131 to be cracked to be cracked, even causing The electrical disconnection between the bumps 1 2 3 and the bonding pads 1 1 3 . The main object of the present invention is to provide an anisotropic conductive bonding flip chip device by using a plurality of conductive pillars Arranged equidistantly and encapsulated in a resin, as an anisotropic conductive film, avoiding the abnormal gathering of the conductive balls, resulting in short circuit between two adjacent bumps, and improving the flip-chip bonding Rate and reduce the anisotropy conduction cost. The second object of the present invention is to provide an asymmetrical crack of the asymmetrical conductive joint. 'Because the conductive pillar can be bent or puncture into the bump, good anisotropic conduction can be ensured. The bonding success rate solves the problem that the electroplating layer on the surface of the conductive ball in the conventional anisotropic conductive film is broken to cause an electrical disconnection. The object of the present invention and solving the technical problem thereof are achieved by the following technical solutions. According to the present invention, An anisotropic conductive bonding flip chip device mainly comprises a substrate, a bumped wafer and an anisotropic conductive 6 gelatinized film glued to the U. In the above-mentioned flip chip device, the bumps and the corresponding gaps between the bumps and the substrate are formed. In the above-mentioned flip chip device, 200847353 is a film. One surface of the substrate is formed with a plurality of bonding pads. The surface of the wafer is formed with a plurality of bumps. The anisotropic guide is interposed between the substrate and the bumped wafer. The anisotropic film comprises a plurality of conductive pillars, wherein the conductive layers The pillars are equidistantly arranged and encapsulated in a resin. #The bumped wafer is connected to the substrate such that the pillars of the conductive pillars between the bumps and the corresponding bonding pads are partially high. It is known that the two ends of the knives are electrically conductive and corresponding to the bonding pads. The object of the present invention and solving the technical problems thereof can be further achieved by the following. In the foregoing flip chip device, at least three conductive posts may be connected to each of the landlines. In the foregoing flip chip device, a portion of the conductive pillar between the bump and the corresponding pad may be bent. The above-mentioned flip chip fn may be pierced into the above-mentioned flip chip device at one end of the portion of the conductive pillar between the pair of tabs, and the above-mentioned bump 4 is outside the bumps and the corresponding bonding potential The remaining conductive pillars may be equally spaced, equal in length, and 0. The lengths of the conductive turns are the gaps of the large pads and are smaller than the bumps. The above-mentioned bumps and the corresponding bumps are electrically conductively bonded to the gaps. The remaining conductive pillars of the plurality of bond pads, which are parallel to the crystal, may be electrically independent and provide a thermal coupling path of the wafer to the substrate. In the foregoing flip chip device, the conductive cassia may be electroformed micro-conductors. In the above-mentioned flip chip device, the material of the conductive pillars may be selected from one of gold, copper, nickel and any of the above-mentioned alloys. In the above flip chip device, the substrate may be a glass circuit board. f\ In the foregoing flip chip device, the substrate may be a circuit film or a printed circuit board. In the foregoing flip chip device, the substrate may be a wafer or a half conductor circuit board. [Embodiment] According to a first embodiment of the present invention, a flip chip device for anisotropic conductive bonding is disclosed. Fig. 2 is a schematic cross-sectional view of the flip chip device. Figure 3 is a schematic view showing the position distribution of a plurality of conductive columns in the flip chip device. 4A to 4B are schematic cross-sectional views of a bumper wafer in the process of the flip chip device. Referring to FIG. 2, an anisotropic conductive bonding flip chip device 200 mainly comprises a substrate 210, a bumped wafer 220 and an anisotropic conductive film 2 3 〇. As shown in Fig. 2, the substrate 2 has an upper surface 2 and a lower surface 212. The upper surface 211 of the substrate 210 is formed with a plurality of bonding pads 2 1 3 . The substrate 2 1 0 can be a glass circuit board.

同，該基板2 1 0亦可為 另一晶片或一半導體線路板。 8 200847353 如第2圖所示，該凸塊化晶片2 2 0係具有一主動面 221及一背面222。該凸塊化晶片220之該主動面221 係形成有積體電路元件以及對外電性連接之複數個凸 塊223。通常該些凸塊223係為金凸塊，其形狀係為柱 狀。 如第2圖所示，該異方性導電膠膜23 0係介設於該 基板2 1 0與該凸塊化晶片220之間。該異方性導電膠膜 ρ 230係包含有複數個導電柱231Α與231Β，其中該些導 電柱23 1 Α與23 1 Β係為規則化等距排列並封設於一樹 脂232内。其中，如第2及3圖所示，該些導電柱231A 係指為在該些凸塊223與對應之該些接合墊2 1 3之間的 部分導電柱，以供有效電性連接。該些導電柱23丨B係 指在該些凸塊223與對應之該些接合墊2 1 3之外的其餘 導電柱’不作為電性互連但具有散熱之功效。 § β凸塊化晶片2 2 0接合至該基板2 1 0以致使該些 凸塊223與對應之該些接合墊2 1 3之間隙小於該些導電 柱231A與231B之柱高時，部分導電柱（即231A)之兩 端係電性連接該些凸塊223與對應之該些接合墊213。 在本實施例中，配合參閱第3圖所示，在每一凸塊223 與對應之接合墊2 1 3之間係可連接有至少三個導電柱 23!A，以大幅降低在熱應力作用下該凸塊化晶片22〇 與該基板2 1 0之間可能發生的電性斷路。 此外，在本實施例中，導電柱231八與231B的金屬 硬度可小於該些凸塊223，上述該些凸塊223與對應之 9 200847353 該些接合墊2 1 3之間的部分導電柱23丨A係將可產生彎 曲形變，造成該凸塊化晶片22〇輿該基板21〇之間的電 性互連更確實，該些凸塊2 2 3之間仍不會有電性橋接的 問題。相較於習知導電球表面電鍍層易遭受壓破裂。使 用本發明之異方性導電膠膜230能採用於覆晶接合更 大作業參數範圍（即更彈性的製程窗）。而上述在該些凸 塊223與對應之該些接合墊213之外的其餘導電柱 〇 23 1B係仍可為等間距、等長且平行排列。故其餘導電 柱231B係可為電性獨立並提供該晶片至該基板21〇之 熱耦合路徑’具有散熱增益之功效。通常該些導電枉 231A與231B的長度係大於該些凸塊223與對應之該些 接合墊2 1 3的間隙且小於該凸塊化晶片2 2 0與該基板 2 1 0的間隙，可避免該凸塊化晶片220與該基板2 1 0被 刺傷。 較佳地，該些導電柱231A與231B係可為電鑄微導 〇 體，以供低成本製作並可符合等間距、等長且平行排列 的要求。而該些導電柱231A與231B之材質係可選自 金、銅、鎳與上述任一組成合金之其中之一。 第4A至4C圖係用以說明根據本發明之第一具體實 施例之該覆晶裝置200之製造方法。首先，請參閱第 4A圖所示，提供一凸塊化晶片220，其係具有一主動面 221及一背面222且在該主動面221係形成有複數個凸 塊 223。 之後，請參閱第4B圖所示，貼覆一異方性導電膠膜 200847353 230於該凸塊化晶片22〇之該主動面22ι。該異方性導 電膠膜23 0係包含有複數個導電柱231A與231B，該些 導電柱23 1 A與23 1 B係為規則化等距排列並封設於一 樹脂232内。該異方性導電膠膜23〇另包含有一保護膠 f 233’其係覆蓋該些導電柱231八與231b之一端以及 °亥树爿曰2 3 2之一表面，用以防止該些導電柱2 3 1 a與 231B之一端面被該樹脂232過度遮蓋。 最後’請參閱第4C圖所示，撕除該保護膠帶233 並將已貼附有該異方性導電膠膜23〇之該晶片22〇接合 至一基板210。該基板210係具有一上表面211、一下 表面212及複數個形成於該上表面21丨之接合墊213。 在接合該凸塊化晶片220與該基板2 1 〇時，該些接合墊 2 1 3與該些凸塊223之間係相互對準，而該異方性導電 膠膜2 3 0則完全不需要作對位調整。並藉由該樹脂2 3 2 將该凸塊化晶片2 2 0與該基板2 1 〇黏合。當該些凸塊 2 2 3與對應之該些接合墊2 1 3之間隙小於該些導電柱 23 1 A與23 1B之柱高時，部分導電柱23 1 A之兩端係電 性連接該些凸塊223與對應之該些接合墊213。 在本發明之第二具體實施例，揭示另一種異方性導 電接合之覆晶裝置。請參閱第5圖所示，該覆晶裝置 3〇〇主要包含一基板310、一凸塊化晶片320以及一異 方性導電膠膜3 3 0。該基板310係具有一上表面311與 ^表面3 1 2，該基板3 1 0之該上表面3 1 1係形成有複 數個接合墊3 1 3。該凸塊化晶片3 2 0係具有一主動面3 2 1 π 200847353 及一背面3 2 2。該凸塊化晶片3 2 0之該主動面3 2 1係形 成有複數個凸塊323。 該異方性導電膠膜3 3 0係介設於該基板3 1 0與該凸 塊化晶片3 20之間，該異方性導電膠膜3 3 0係包含有複 數個導電柱331Α與331Β，其中該些導電柱331Α與 3 3 1 Β係為規則化等距排列並封設於一樹脂3 3 2内。 當该凸塊化晶片3 2 0接合至該基板3 1 0以致使該些 〇 凸塊3 23與對應之該些接合墊3 1 3之間隙小於該些導電 柱331Α與331Β之柱高時，部分導電柱331Α之兩端係 電性連接該些凸塊3 2 3與對應之該些接合塾3 1 3。 在本實施例中，該些導電柱331Α與331Β之硬度係 大於該些凸塊323之硬度。故上述在該些凸塊323與對 應之該些接合墊3 1 3之間的部分導電柱3 3 1 Α之一端係 可穿刺入該些凸塊323。因此，能達到低成本且高耐用 度的異方性導電接合效果 ( 以上所述，僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，雖然本發明已以較佳實施 例揭露如上，然而並非用以限定本發明，任何熟悉本專 業的技術人員’在不脫離本發明技術方案範圍内，當可 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 容，依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾，均仍屬於本發明技術方案的 範圍内。 12 200847353 【圖式簡單說明】 第1圖··一種習知異方性導電接合之覆晶裝置之截面示 意圖。 第2圖·依據本發明之第一具體實施例，一種異方性導 電接合之覆晶裝置之截面示意圖。 第3圖··依據本發明之第一具體實施例，該異方性導電 接合之覆晶裝置中複數個導電柱之位置分布 不意圖。 第4A至4C圖：依據本發明之第一具體實施例，該異 方性導電接合之覆晶裝置於製程中一凸塊化 晶片之截面示意圖。 第5圖：依據本發明之第二具體實施例，另一種異方性 導電接合之覆晶裝置之截面示意圖。 【主要元件符號說明】 100覆晶裝置 110 基板 111 上 表 面 112 下 表 面 113 接合墊 120 凸塊化 晶 片 121 主 動 面 122 背 面 123 凸塊 130 異方性 導 電膠膜 131 導 電 球 132 金屬層 200 覆晶裝 置 210 基板 211 上 表 面 212 下 表 面 213接合墊 13 200847353 220凸塊化晶片 221主動面 223凸塊 230異方性導電膠膜 231B導電柱 232樹脂 300覆晶裝置 3 1 0基板 3 11上表面 313接合墊 320凸塊化晶片 321主動面 323凸塊 330異方性導電膠膜 331B導電柱 332樹脂 222背面 231A導電柱 233保護膠帶 312下表面 322背面 331A導電柱 14Similarly, the substrate 210 may be another wafer or a semiconductor circuit board. 8 200847353 As shown in FIG. 2, the bumped wafer 220 has an active surface 221 and a back surface 222. The active surface 221 of the bumped wafer 220 is formed with integrated circuit elements and a plurality of bumps 223 electrically connected to each other. Usually, the bumps 223 are gold bumps, and the shape thereof is columnar. As shown in Fig. 2, the anisotropic conductive film 230 is interposed between the substrate 210 and the bump wafer 220. The anisotropic conductive film ρ 230 includes a plurality of conductive pillars 231 Α and 231 Β, wherein the conductive pillars 23 1 Α and 23 1 为 are regularly arranged equidistantly and enclosed in a resin 232. As shown in the second and third figures, the conductive pillars 231A are referred to as partial conductive pillars between the bumps 223 and the corresponding bonding pads 2 1 3 for effective electrical connection. The conductive pillars 23A indicate that the other conductive pillars 223 outside the corresponding bumps 223 and the corresponding bonding pads 2 1 3 are not electrically interconnected but have heat dissipation effects. § The β-bump wafer 2 2 0 is bonded to the substrate 2 1 0 such that the gap between the bumps 223 and the corresponding bonding pads 2 1 3 is smaller than the pillars of the conductive pillars 231A and 231B, and partially conductive The two ends of the column (ie, 231A) are electrically connected to the bumps 223 and the corresponding bonding pads 213. In this embodiment, as shown in FIG. 3, at least three conductive posts 23!A can be connected between each bump 223 and the corresponding bonding pad 2 1 3 to greatly reduce the thermal stress. An electrical disconnection that may occur between the bumped wafer 22 and the substrate 210. In addition, in this embodiment, the metal hardness of the conductive pillars 231 and 231B may be smaller than the bumps 223, and the partial conductive pillars 23 between the bumps 223 and the corresponding 9 200847353 of the bonding pads 2 1 3丨A series will be able to produce bending deformation, resulting in more reliable electrical interconnection between the bumped wafer 22 and the substrate 21 ,, there is still no problem of electrical bridging between the bumps 2 2 3 . Compared with the conventional conductive ball surface, the plating layer is susceptible to pressure cracking. The use of the anisotropic conductive film 230 of the present invention can be employed in flip chip bonding with a larger range of operating parameters (i.e., a more flexible process window). The remaining conductive pillars 23 1B outside the bumps 223 and the corresponding bonding pads 213 may still be equally spaced, equal in length, and arranged in parallel. Therefore, the remaining conductive pillars 231B can be electrically independent and provide the heat-coupled path of the wafer to the substrate 21A with heat dissipation gain. Generally, the lengths of the conductive bumps 231A and 231B are larger than the gap between the bumps 223 and the corresponding bonding pads 21 and less than the gap between the bumped wafers 220 and the substrate 2 1 0, which can be avoided. The bumped wafer 220 is stabbed with the substrate 210. Preferably, the conductive pillars 231A and 231B are electroformed micro-conducting bodies for low cost fabrication and can meet the requirements of equal spacing, equal length and parallel arrangement. The materials of the conductive pillars 231A and 231B may be selected from one of gold, copper, nickel and any of the above alloys. 4A to 4C are views for explaining a method of manufacturing the flip chip device 200 according to the first embodiment of the present invention. First, as shown in FIG. 4A, a bump wafer 220 is provided having an active surface 221 and a back surface 222, and a plurality of bumps 223 are formed on the active surface 221. Thereafter, as shown in FIG. 4B, an anisotropic conductive film 200847353 230 is attached to the active surface 22 of the bumped wafer 22. The anisotropic conductive film 205 includes a plurality of conductive pillars 231A and 231B, and the conductive pillars 23 1 A and 23 1 B are regularly arranged equidistantly and encapsulated in a resin 232. The anisotropic conductive film 23 〇 further includes a protective adhesive f 233 ′ which covers one end of the conductive pillars 231 8 and 231 b and a surface of the Hei Shu 爿曰 2 3 2 to prevent the conductive pillars One end face of 2 3 1 a and 231B is over-covered by the resin 232. Finally, as shown in Fig. 4C, the protective tape 233 is peeled off and the wafer 22 to which the anisotropic conductive film 23 is attached is bonded to a substrate 210. The substrate 210 has an upper surface 211, a lower surface 212, and a plurality of bonding pads 213 formed on the upper surface 21丨. When the bumped wafer 220 and the substrate 2 1 are bonded, the bonding pads 2 1 3 and the bumps 223 are aligned with each other, and the anisotropic conductive film 2 3 0 is not at all Need to make a counter adjustment. The bumped wafer 220 is bonded to the substrate 2 1 by the resin 2 3 2 . When the gap between the bumps 2 2 3 and the corresponding bonding pads 2 1 3 is smaller than the pillars of the conductive pillars 23 1 A and 23 1B, the two ends of the conductive pillars 23 1 A are electrically connected. The bumps 223 and the corresponding bonding pads 213. In a second embodiment of the invention, another anisotropic conductive bonding flip chip device is disclosed. Referring to FIG. 5, the flip chip device 3A mainly includes a substrate 310, a bump wafer 320, and an anisotropic conductive film 310. The substrate 310 has an upper surface 311 and a surface 3 1 2, and the upper surface 31 of the substrate 310 is formed with a plurality of bonding pads 313. The bumped wafer 320 has an active surface 3 2 1 π 200847353 and a back surface 32 2 . The active surface 3 2 1 of the bumped wafer 320 is formed with a plurality of bumps 323. The anisotropic conductive film 305 is interposed between the substrate 310 and the bumped wafer 306. The anisotropic conductive film 305 includes a plurality of conductive pillars 331 and 331. The conductive pillars 331 and 3 3 1 are regularly arranged equidistantly and encapsulated in a resin 3 3 2 . When the bumped wafer 320 is bonded to the substrate 310 to cause the gap between the bumps 3 23 and the corresponding pads 3 1 3 to be smaller than the pillars of the conductive pillars 331 and 331 , The two ends of the conductive pillars 331 are electrically connected to the bumps 3 2 3 and the corresponding joints 331 . In this embodiment, the hardness of the conductive pillars 331 and 331 is greater than the hardness of the bumps 323. Therefore, one of the portions of the conductive pillars 3 3 1 之间 between the bumps 323 and the corresponding bonding pads 313 can be punctured into the bumps 323. Therefore, the low-cost and high-durability anisotropic conductive bonding effect can be achieved (the above is only a preferred embodiment of the present invention, and does not impose any form limitation on the present invention, although the present invention has been preferred. The embodiments are disclosed above, but are not intended to limit the present invention, and those skilled in the art can make some modifications or modifications to equivalent variations when using the above-disclosed technical contents without departing from the scope of the present invention. For the embodiments, any simple modifications, equivalent changes and modifications to the above embodiments in accordance with the technical spirit of the present invention are still within the scope of the technical solutions of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view of a conventional flip-chip device for anisotropic conductive bonding. FIG. 2 is a cross-sectional device of an anisotropic conductive bonding according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view of the flip-chip device of the anisotropic conductive joint according to the first embodiment of the present invention. The positional distribution of the conductive pillars is not intended. 4A to 4C are schematic cross-sectional views of a bumped wafer in the process of the anisotropic conductive bonding flip chip device according to the first embodiment of the present invention. According to a second embodiment of the present invention, a schematic cross-sectional view of another anisotropic conductive bonding flip chip device is provided. [Main element symbol description] 100 flip chip device 110 substrate 111 upper surface 112 lower surface 113 bonding pad 120 bump Wafer 121 Active surface 122 Back surface 123 Bump 130 Anisotropic conductive film 131 Conductive ball 132 Metal layer 200 Flip chip device 210 Substrate 211 Upper surface 212 Lower surface 213 Bond pad 13 200847353 220 Bump wafer 221 Active surface 223 convex Block 230 anisotropic conductive film 231B conductive column 232 resin 300 flip chip device 3 1 0 substrate 3 11 upper surface 313 bonding pad 320 bumped wafer 321 active surface 323 bump 330 anisotropic conductive film 331B conductive column 332 Resin 222 back surface 231A conductive column 233 protection tape 312 lower surface 322 back surface 331A conductive column 14

Claims (1)

200847353 、申請專利範圍 種異方性導電接合之覆晶裝置，包含： 一基板，其一表面係形成有複數個接合墊； Ο 凸塊化曰曰片’其係-表面係形成有複數個凸塊；以及 -異方性導電膠膜，其係介設於該基板與該凸塊化晶片 ▲之間’該異方性導電膠膜係包含有複數個導電柱，其中 該些導電柱係為規則化等距排列並封設於-樹脂内； 當該凸塊化晶片接合至該基板以致使該些凸塊與對應 之該些接合墊之間隙小於該些導電柱之柱高時，部分導 電柱之兩料電性連接㈣凸塊與對叙該些接合塾。 2裝如=利範圍第i項所述之異方性導電接合之覆晶 、一八在母一凸塊與對應之接合墊之間係連接有至 少三個導電柱。 3、 如申請專利範圍第丨 "，甘士、、 項所之異方性導電接合之覆晶 我置 中上述該歧凸嫂鱼斟；ft夕外*从A 八道—凸塊與對應之該些接合塾之間的部 刀導電柱係產生彎曲形變。 4、 如中料利範㈣i項所述之異方 裝置，苴Φ l·、+、士 a Τ电银口之覆晶 ^ ^在该些凸塊與對應之該些接合塾之門& P刀導電柱之一端係、穿刺入該些凸塊。 5如申清專利範圍第 f置，^ μ + 所述之異方性導電接合之覆晶 裝置，其中上述在該此 使 I給道/、 對應之該些接合墊之外的 其餘導電柱你為ΘΒ ~ .. 係為相距、等長且平行排列。 6、如申請專利範圍第 所通之異方性導電桎入+费曰 裝置’其中該此導雷括的子电接合之覆晶 -導電柱的長度係大於該些凸塊與對 15 200847353 應之邊些接合塾的間隙且小於該凸塊化晶片與該基 板的間隙。 7、如申請專利範圍第5項所述之異方性導電接合之覆晶 裝置，其中上述在該些凸塊與對應之該些接合墊之外的 其餘導電柱係為電性獨立並提供該晶片至該基板之執搞 合路徑。 士申π專利|巳圍第i項所述之異方性導電接合之覆晶 f、 裝置，其中該些導電柱係為電鑄微導體。 9、 如申請專利範圍第i項所述之異方性導電接合之覆晶 裝置，其中該些導電柱之材質係選自金、銅、鎳與上述 任一組成合金之其中之一。 10、 如中睛專利範圍第i項所述之異方性導電接合之覆晶 裝置，其中該基板係為一玻璃線路板。 11、 如申凊專利範圍第i項所述之異方性導電接合之覆晶 裝置，其中該基板係為一電路薄膜或一印刷電路板。 、 12、如申請專利範圍第丨項所述之異方性導電接合之覆晶 裳置，其中該基板係為一晶片或一半導體線路板。 16200847353, the patent application scope of the heterogeneous conductive bonding flip chip device, comprising: a substrate, a surface of which is formed with a plurality of bonding pads; Ο a bumped slab "the system-surface system is formed with a plurality of convex And an anisotropic conductive film interposed between the substrate and the bumped wafer ▲. The anisotropic conductive film comprises a plurality of conductive pillars, wherein the conductive pillars are Regularly arranged equidistantly and encapsulated in the resin; partially conductive when the bumped wafer is bonded to the substrate such that the gap between the bumps and the corresponding pads is less than the height of the pillars of the conductive pillars The two materials of the column are electrically connected (4) with the bumps and the joints. 2 Mounting the flip-chip of the anisotropic conductive joint as described in item i of the profit range, and connecting at least three conductive pillars between the mother-bump and the corresponding bonding pad. 3. If the scope of the patent application is 丨", the anisotropic conductive joint of the Ganshi, the project, I put the above-mentioned 嫂 嫂 斟 斟; ft 夕 外 * from A 八 — - bumps and corresponding The portion of the conductive pillar between the joint jaws produces a curved deformation. 4. For example, in the dissimilar device described in item (4) i, 苴Φ l·, +, 士 a Τ 银 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ One end of the knife conductive column is pierced into the bumps. 5, as claimed in the patent scope f, ^ μ + the anisotropic conductive bonding flip chip device, wherein the above-mentioned I give the track /, corresponding to the other conductive posts outside the bond pads you For ΘΒ ~ .. are separated by equal length and arranged in parallel. 6. The length of the isoelectric conductive intrusion + fee device as claimed in the patent application scope, wherein the length of the flip-chip-conductive column of the sub-electrical joint is greater than the number of the bumps and the pair 15 200847353 The gap between the sides of the bonding pads is smaller than the gap between the bumped wafer and the substrate. 7. The flip-chip device of the anisotropic conductive joint according to claim 5, wherein the other conductive pillars outside the bumps and the corresponding bonding pads are electrically independent and provide the same The bonding path of the wafer to the substrate. The patent of the anisotropic conductive joint described in item i, wherein the conductive pillars are electroformed microconductors. 9. The flip chip device of the anisotropic conductive joint according to claim i, wherein the conductive pillars are selected from the group consisting of gold, copper, nickel and one of the alloys of any of the above. 10. The flip-chip device for anisotropic conductive bonding according to item ii of the middle eye patent range, wherein the substrate is a glass circuit board. 11. The flip-chip device for anisotropic conductive bonding according to item ii of the patent application, wherein the substrate is a circuit film or a printed circuit board. 12. The flip-chip solder of the anisotropic conductive joint according to the above application of the patent application, wherein the substrate is a wafer or a semiconductor circuit board. 16
TW096119037A 2007-05-28 2007-05-28 Flip chip device with acf connections TWI332254B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104951156A (en) * 2014-03-31 2015-09-30 宸盛光电有限公司 Capacitive touch control device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104951156A (en) * 2014-03-31 2015-09-30 宸盛光电有限公司 Capacitive touch control device
TWI581163B (en) * 2014-03-31 2017-05-01 宸盛光電有限公司 Capacitive touch device

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