13322541332254
九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種覆晶裝置，特別係有關於 異方性導電接合之覆晶裝置β 【先前技術】 在以往覆晶接合技術中，異方性導電 (anisotropic conductive bonding)是其中一種重要 可被取代的方法’相較於共晶焊接方式，異方性導 合係能以低溫低壓合的條件達到高密度的電性連赶 而’目前所採用的異方性導電接合膠膜（ACF)係在 固化樹脂内封設有複數個等球徑的導電球，並且該 電球的分散密度必須相當均勻，故異方性導電接合 的成本很高。此外，當覆晶壓合力量過大，導電球 順利地電性接觸晶片凸塊與基板接墊；當覆晶壓合 過大’導電球表面的電鍍層易於破裂，導致電性軟 因此可作業參數範圍（即製程窗）顯得狹窄，故覆晶 良率與產品可靠性需要作進一步的改善。 請參閱第1圖所示，一種習知的異方性導電 覆晶裝置100包含一基板11〇、_凸塊化晶片12 一異方性導電膠膜130。該基板110係具有一 111、一下表面112及複數個形成於該上表面Η 合墊1 1 3 »該凸塊化晶片i 2〇係具 背面122’其中該主動面121係形成有複數 該異方性導電膠膜！ 3 〇係介設於該 k 邋化晶片夏: 一種 姿合 且不 電接 。缺 一半 些導 膠膜 無法 力量 路， 接合 合之 以及 表面 之接 及一 123 〇 與該 5 1-332254 基板1 1 0之間，該異方性導電膠膜1 3 〇係包含有複數個 等球徑之導電球131。該些導電球131係被要求均勻分 散在該異方性導電膠膜丨3 〇内，方可達到縱向的異方性 導電’導致製程困難度相當高與昂貴成本。當部分之導 電球131不正常的聚集，會導致該些凸塊123之間的短 路。此外，通常該些導電球1 3 1之球體係為絕緣樹脂 球，在球外周面係電鍍包覆有一金屬層132。當覆晶接 合時’該些導電球131會在該些凸塊123與該些接合墊 113之間被擠壓，過大的晶片壓合強度會導致被擠壓之 該些導電球131之金屬層132產生龜裂，甚至引起在該 些凸塊123與該些接合墊113之間的電性斷路。 【發明内容】 本發明之主要目的係在於提供一種異方性導電接合 之覆晶裝置，藉由複數個導電柱係為規則化等距排列並封 設於一樹脂内’作為一異方性導電膠膜，避免習知導電球 不正常聚集而導致兩相鄰之凸塊間之短路，並可提升覆 晶接合良率並降低異方性導電成本。 本發明之次一目的係在於提供一種異方性導電接合 之覆晶裝置，由於導電柱係可彎曲或穿刺入凸塊，可以 確保良好的異方性導電接合成功率，解決了習知異方性 導電膠膜内導電球表面電鍍層破裂導致電性斷路的問題。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明，一種異方性導電接合之覆晶 裝置主要包含一基板、一凸塊化晶片以及一異方性導電 6 1332254 ‘ 膠膜。該基板之一表面係形成有複數個接合墊。該凸塊 化晶片係一表面係形成有複數個凸塊。該異方性導電膠 膜係介設於該基板與該凸塊化晶片之間，該異方性導電 膠膜係包含有複數個導電柱，其中該些導電柱係為規則 化等距排列並封設於一樹脂内。當該凸堍化晶片接合至 該基板以致使該些凸塊與對應之該些接合墊之間隙小 於該些導電柱之柱高時，部分導電柱之兩端係電性連接 該些凸塊與對應之該些接合墊。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的覆晶裝置中，在每一凸塊與對應之接合墊 之間係可連接有至少三個導電柱。 在前述的覆晶裝置中，上述該些凸塊與對應之該些 接合墊之間的部分導電柱係可產生彎曲形變。 在前述的覆晶裝置中，上述在該些凸塊與對應之該 些接合墊之間的部分導電柱之一端係可穿刺入該些凸 塊。 在前述的覆晶裝置中，上述在該些凸塊與對應之該 些接合墊之外的其餘導電柱係可為等間距、等長且平行 排列。 在前述的覆晶裝置中，該些導電柱的長度係大於該 些凸塊與對應之該些接合墊的間隙且小於該凸塊化晶 片與該基板的間隙。 在前述的覆晶裝置中，上述在該些凸塊與對應之該 7 1332254IX. Description of the Invention: [Technical Field] The present invention relates to a flip chip device, and more particularly to a flip chip device β for anisotropic conductive bonding. [Prior Art] In the conventional flip chip bonding technology, the stranger Anisotropic conductive bonding is one of the most important methods that can be replaced. Compared with the eutectic soldering method, the anisotropic conducting system can reach a high-density electrical connection under the conditions of low temperature and low pressure. The anisotropic conductive bonding film (ACF) is used to seal a plurality of conductive balls of equal spherical diameter in the cured resin, and the dispersion density of the ball must be relatively uniform, so the cost of the anisotropic conductive bonding is high. In addition, when the flip-chip bonding force is too large, the conductive ball smoothly contacts the wafer bump and the substrate pad smoothly; when the flip-chip is pressed too much, the plating layer on the surface of the conductive ball is easily broken, resulting in electrical softness and thus the operating parameter range. (ie, the process window) appears to be narrow, so the coverage rate and product reliability need to be further improved. Referring to FIG. 1, a conventional anisotropic conductive flip chip device 100 includes a substrate 11 , a bumped wafer 12 , and an anisotropic conductive film 130 . The substrate 110 has a 111, a lower surface 112, and a plurality of the upper surface of the pad 1 1 3 » the bumped wafer i 2 〇 a back surface 122 ′, wherein the active surface 121 is formed with a plurality of different Square conductive film! 3 The 〇 system is placed on the k 邋 wafer summer: a posture and no electrical connection. If there are half of the conductive film, there is no power path, the bonding and the surface connection, and a gap between the 123 〇 and the 5 1-332254 substrate 1 10 , the anisotropic conductive film 13 〇 contains a plurality of The conductive ball 131 of the ball diameter. The conductive balls 131 are required to be uniformly dispersed in the anisotropic conductive film 丨3 , in order to achieve longitudinal anisotropy conduction, resulting in a relatively high process difficulty and high cost. When some of the conductive balls 131 are abnormally gathered, a short circuit between the bumps 123 is caused. In addition, generally, the ball system of the conductive balls 133 is an insulating resin ball, and a metal layer 132 is plated on the outer peripheral surface of the ball. When the flip chip is bonded, the conductive balls 131 are pressed between the bumps 123 and the bonding pads 113, and the excessive wafer bonding strength causes the metal layers of the conductive balls 131 to be extruded. The cracks are generated and even cause an electrical break between the bumps 123 and the bond pads 113. SUMMARY OF THE INVENTION The main object of the present invention is to provide an anisotropic conductive bonding flip chip device in which a plurality of conductive pillars are regularly arranged equidistantly and encapsulated in a resin as an anisotropic conductive The film prevents the abnormal conduction of the conductive balls and causes short circuit between the two adjacent bumps, and can improve the flip chip bonding yield and reduce the anisotropy conduction cost. A second object of the present invention is to provide an anisotropic conductive bonding flip chip device. Since the conductive pillar can be bent or puncture into the bump, a good anisotropic conductive bonding success rate can be ensured, and the conventional anisotropy is solved. The rupture of the electroplated layer on the surface of the conductive ball in the conductive film causes a problem of electrical disconnection. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, an anisotropic conductive bonding flip chip device mainly comprises a substrate, a bumped wafer and an anisotropic conductive 6 1332254 Å film. One of the surfaces of the substrate is formed with a plurality of bonding pads. The bumped wafer is formed with a plurality of bumps on a surface. The anisotropic conductive film is interposed between the substrate and the bumped wafer, and the anisotropic conductive film comprises a plurality of conductive pillars, wherein the conductive pillars are regularly arranged equidistantly It is sealed in a resin. When the bumped wafer is bonded to the substrate such that the gap between the bumps and the corresponding bonding pads is smaller than the pillar height of the conductive pillars, the two ends of the conductive pillars are electrically connected to the bumps and Corresponding to the bonding pads. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing flip chip device, at least three conductive posts may be connected between each bump and the corresponding bonding pad. In the foregoing flip chip device, a portion of the conductive pillars between the bumps and the corresponding bonding pads may be bent. In the above flip chip device, one end of a portion of the conductive posts between the bumps and the corresponding bond pads can be punctured into the bumps. In the above-mentioned flip chip device, the remaining conductive pillars outside the bumps and the corresponding bonding pads may be equally spaced, equal in length, and arranged in parallel. In the above-mentioned flip chip device, the lengths of the conductive pillars are larger than the gap between the bumps and the corresponding bonding pads and smaller than the gap between the bumping wafer and the substrate. In the foregoing flip chip device, the above-mentioned bumps and the corresponding 7 1332254
些接合墊之外的其餘導電柱係可為電性獨立並提供該 晶片至該基板之熱耦合路徑。 在前述的覆晶裝置中’該些導電柱係可為電鑄微導 體。 在前述的覆晶裝置中’該些導電柱之材質係可選自 金、銅、鎳與上述任一組成合金之其中之一。 在前述的覆晶裝置中’該基板係可為一玻璃線路板。 在前述的覆晶裝置中’該基板係可為一電路薄膜或 一印刷電路板。 在前述的覆晶裝置中’該基板係可為一晶片或一半 導體線路板。 【實施方式】 依據本發明之第一具體實施例，揭示一種異方性導 電接合之覆晶裝置。第2圖係為該覆晶裝置之截面示意 圖。第3圖係為該覆晶裝置中複數個導電柱之位置分布 示意圖。第4A至4B圖係為該覆晶裝置於製程中一凸 塊化晶片之截面示意圖。請參閱第2圖所示，一種異方 性導電接合之覆晶裝置2 00主要包含一基板210、一凸 塊化晶片220以及一異方性導電膠膜230。 如第2圖所示，該基板210係具有一上表面211及 一下表面212。該基板210之該上表面211係形成有複 數個接合塾213。該基板210係可為一玻璃線路板、一 電路薄膜、一印刷電路板或是一導線架。依運用領域不 同該基板210亦可為另一晶片或一半導體線路板。 8 1332254 如第2圖所示，該凸塊化晶片220係具有一主動面 221及一背面222。該凸塊化晶片220之該主動面221 係形成有積體電路元件以及對外電性連接之複數個凸 塊223°通常該些凸塊223係為金凸塊，其形狀係為柱 狀。 如第2圖所示，該異方性導電膠膜23〇係介設於該 基板210與s亥凸塊化晶片220之間。該異方性導電朦膜 • 230係包含有複數個導電柱231A與231B，其中該些導 電柱2 3 1 A與2 3 1 B係為規則化等距排列並封設於一樹 脂232内。其中，如第2及3圖所示，該些導電枉231八 係指為在該些凸塊223與對應之該些接合塾213之間的 部分導電枉’以供有效電性連接。該些導電柱231B係 指在該些&塊223與對應之該些接合墊213之外的其餘 導電柱’不作為電性互連但具有散熱之功效。 當該凸塊化晶片220接合至該基板210以致使該些 凸塊223與對應之該些接合塾2 1 3之間隙小於該些導電 柱231A與231B之柱高時，部分導電柱（即231A)之兩 端係電性連接該些凸塊223與對應之該些接合墊213。 在本實施例中，配合參閱第3圖所示，在每—&塊223 與對應之接合塾2 1 3之間係可連接有至少三個導電枉 23 1Α，以大幅降低在熱應力作用下該凸塊化晶片220 與該基板2 1 0之間可能發生的電性斷路。 此外，在本實施例中’導電柱231Α與231Β的金屬 硬度可小於該些凸塊223，上述該些凸塊223與對應之 9 1332254 柱2 3 1 A係將可產生彎 該些接合墊2 1 3之間的部分導電The remaining conductive pillars other than the bond pads can be electrically independent and provide a thermal coupling path for the wafer to the substrate. In the foregoing flip chip device, the conductive pillars may be electroformed microconductors. In the above-mentioned flip chip device, the material of the conductive pillars may be selected from one of gold, copper, nickel and any of the above-mentioned alloys. In the foregoing flip chip device, the substrate may be a glass wiring board. In the foregoing flip chip device, the substrate may be a circuit film or a printed circuit board. In the foregoing flip chip device, the substrate may be a wafer or a half conductor circuit board. [Embodiment] According to a first embodiment of the present invention, a flip chip device for anisotropic conductive bonding is disclosed. Fig. 2 is a schematic cross-sectional view of the flip chip device. Figure 3 is a schematic view showing the position distribution of a plurality of conductive columns in the flip chip device. 4A to 4B are schematic cross-sectional views of a bumper wafer in the process of the flip chip device. Referring to FIG. 2, an anisotropic conductive bonding flip chip device 200 mainly includes a substrate 210, a bump wafer 220, and an anisotropic conductive film 230. As shown in Fig. 2, the substrate 210 has an upper surface 211 and a lower surface 212. The upper surface 211 of the substrate 210 is formed with a plurality of joints 213. The substrate 210 can be a glass circuit board, a circuit film, a printed circuit board or a lead frame. The substrate 210 may be another wafer or a semiconductor circuit board depending on the field of application. 8 1332254 As shown in FIG. 2, the bumped wafer 220 has an active surface 221 and a back surface 222. The active surface 221 of the bumped wafer 220 is formed with an integrated circuit element and a plurality of bumps 223 electrically connected to each other. Usually, the bumps 223 are gold bumps and have a columnar shape. As shown in Fig. 2, the anisotropic conductive film 23 is interposed between the substrate 210 and the swelled wafer 220. The anisotropic conductive ruthenium film • The 230 series includes a plurality of conductive pillars 231A and 231B, wherein the conductive pillars 2 3 1 A and 2 3 1 B are regularly arranged equidistantly and enclosed in a resin 232. As shown in Figures 2 and 3, the conductive pads 231 are referred to as a portion of the conductive pads 223 between the bumps 223 and the corresponding pads 213 for effective electrical connection. The conductive pillars 231B refer to the other conductive pillars except the corresponding bonding pads 213, which are not electrically interconnected but have the effect of dissipating heat. When the bumped wafer 220 is bonded to the substrate 210 such that the gap between the bumps 223 and the corresponding joints 213 is smaller than the pillars of the conductive pillars 231A and 231B, a portion of the conductive pillars (ie, 231A) The two ends of the two are electrically connected to the bumps 223 and the corresponding bonding pads 213. In this embodiment, as shown in FIG. 3, at least three conductive turns 23 1Α may be connected between each of the & block 223 and the corresponding joint 塾 2 1 3 to greatly reduce the thermal stress. An electrical disconnection that may occur between the bumped wafer 220 and the substrate 210. In addition, in the present embodiment, the metal hardness of the conductive pillars 231Α and 231Β may be smaller than the bumps 223, and the bumps 223 and the corresponding 9 1332254 pillars 2 3 1 A system may bend the joint pads 2 Partially conductive between 1 3
曲形變’造成該凸塊化晶片220與該基板210之間的電 陳互連更確實’ 1¾些凸& 223之間仍不會有電性橋接的 問題4目較於S知導電球表面電鍍層易遭受壓破裂。使 用本發明之異方性導電膠膜23()能採用於覆晶接合更 大作業參數範圍（即更彈性的製程窗）。而上述在該些凸 塊223與對應之該些接合墊213之外的其餘導電柱 23 1B係仍可為等間距、等長且平行排列。故其餘導電 柱23 1B係可為電性獨立並提供該晶片至該基板21〇之 …、耦σ路k具有散熱增益之功效。通常該些導電柱 231 A與231B的長度係大於該些凸塊223與對應之該些 接合墊2 1 3的間隙且小於該凸塊化晶片22〇與該基板 2 10的間隙：’可避免該凸塊化晶μ 22〇與該基板被 刺傷。The curved shape 'causes the electrical interconnection between the bumped wafer 220 and the substrate 210 to be more reliable. There is still no problem of electrical bridging between the convex and the 223. The plating layer is susceptible to pressure cracking. The use of the anisotropic conductive film 23() of the present invention can be employed in flip-chip bonding to a greater range of operating parameters (i.e., a more flexible process window). The remaining conductive pillars 23 1B outside the bumps 223 and the corresponding bonding pads 213 may still be equally spaced, equal in length, and arranged in parallel. Therefore, the remaining conductive pillars 23 1B can be electrically independent and provide the wafer to the substrate 21, and the coupling σ path k has the heat dissipation gain effect. Generally, the lengths of the conductive pillars 231 A and 231B are larger than the gap between the bumps 223 and the corresponding bonding pads 21 and less than the gap between the bumped wafer 22 and the substrate 2 10: The bumped crystal μ 22 is stabbed with the substrate.
較佳地’該些導電柱231Α與231Β係可為電鑄微導 體，以供低成本製作並可符合等間距、等長且平行排列 的要求。而該些導電柱231八與2313之材質係可選自 金、銅、鎳與上述任一組成合金之其中之一。 第4Α至4C圖係用以說明根據本發明之第—具體實 施例之該覆晶裝置200之製造方法。首先，請參閱$ 4Α圖所示’提供一凸塊化晶片220，其係且右 〆、匁一主動面 221及一背面222且在該主動面221係形成有複數個 塊 223。 之後’請參閱第4Β圓所示，貼覆一異方性導電膠膜 10 1332254 230於該凸塊化晶片220之該主動面221。該異方性導 電膠膜230係包含有複數個導電桎231Α與231Β，該些 導電柱2 3 1 Α與2 3 1 Β係為規則化等距排列並封設於〆 樹脂232内。該異方性導電膠膜23〇另包含有一保護膠 帶233’其係覆蓋該些導電柱231人與231B之一端以及 該樹脂232之一表面，用以防止該些導電柱231a與 231B之一端面被該樹脂232過度遮蓋。 # 最後，請參閲第4C圖所示，撕除該保護膠帶233 並將已貼附有該異方性導電膠膜23〇之該晶片22〇接合 至—基板210。該基板210係具有一上表面211、一下 表面212及複數個形成於該上表面211之接合塾213。 在接合該凸塊化晶片220與該基板210時，該些接合墊 2 1 3與該些凸塊223之間係相互對準，而該異方性導電 膠膜230則元全不需要作對位調整。並藉由該樹脂232 _ 將該凸塊化晶片220與該基板2 1 〇黏合。當該些凸塊 2 2 3與對應之該些接合塾2 1 3之間隙小於該些導電柱 23 1A與23 1B之柱高時，部分導電柱231A之兩端係電 性連接該些凸塊223與對應之該些接合塾213。 在本發明之第二具體實施例，揭示另一種異方性導 電接合之覆晶裝置。請參閱第5圖所示，該覆晶裝置 3〇〇主要包含一基板310、一凸塊化晶片320以及一異 方性導電膠膜330。該基板310係具有一上表面311與 ''下表面312’該基板310之該上表面311係形成有複 數個接合墊313。該凸塊化晶片320係具有一主動面321 11 1332254 及一背面322。該凸塊化晶片320之該主動面321係形 成有複數個凸塊323。 該異方性導電膠膜330係介設於該基板310與該凸 塊化晶片3 2 0之間’該異方性導電膠膜3 3 0係包含有複 數個導電柱331A與331B，其中該些導電桎331A與 3 3 1 B係為規則化等距排列並封設於一樹脂3 3 2内。 S該凸塊化晶片320接合至該基板310以致使該些Preferably, the conductive posts 231 and 231 can be electroformed micro-conductors for low cost fabrication and can meet the requirements of equal spacing, equal length and parallel alignment. The materials of the conductive pillars 231 and 2313 may be selected from one of gold, copper, nickel and any of the above alloys. The fourth to fourth embodiments are for explaining the manufacturing method of the flip chip device 200 according to the first embodiment of the present invention. First, a bumped wafer 220 is provided as shown in the figure of FIG. 4, which is a right side, an active surface 221 and a back surface 222, and a plurality of blocks 223 are formed on the active surface 221. Thereafter, as shown in the fourth circle, an anisotropic conductive film 10 1332254 230 is attached to the active surface 221 of the bumped wafer 220. The anisotropic conductive film 230 comprises a plurality of conductive electrodes 231 Α and 231 Β. The conductive columns 2 3 1 Α and 2 3 1 Β are regularly arranged equidistantly and encapsulated in the ruthenium resin 232. The anisotropic conductive film 23 〇 further includes a protective tape 233 ′ covering one end of the conductive pillars 231 and 231B and a surface of the resin 232 for preventing one end surface of the conductive pillars 231 a and 231B . It is over-covered by the resin 232. # Finally, referring to FIG. 4C, the protective tape 233 is peeled off and the wafer 22 to which the anisotropic conductive film 23 is attached is bonded to the substrate 210. The substrate 210 has an upper surface 211, a lower surface 212, and a plurality of joints 213 formed on the upper surface 211. When the bumped wafer 220 and the substrate 210 are bonded, the bonding pads 2 1 3 and the bumps 223 are aligned with each other, and the anisotropic conductive film 230 does not need to be aligned. Adjustment. The bumped wafer 220 is bonded to the substrate 2 1 by the resin 232 _ . When the gap between the bumps 2 2 3 and the corresponding joints 1 2 1 3 is smaller than the pillars of the conductive pillars 23 1A and 23 1B, the two ends of the conductive pillars 231A are electrically connected to the bumps. 223 and corresponding joints 213. In a second embodiment of the invention, another anisotropic conductive bonding flip chip device is disclosed. Referring to FIG. 5, the flip chip device 3A mainly comprises a substrate 310, a bump wafer 320 and an anisotropic conductive film 330. The substrate 310 has an upper surface 311 and a 'lower surface 312'. The upper surface 311 of the substrate 310 is formed with a plurality of bonding pads 313. The bumped wafer 320 has an active surface 321 11 1332254 and a back surface 322. The active surface 321 of the bumped wafer 320 is formed with a plurality of bumps 323. The anisotropic conductive film 330 is interposed between the substrate 310 and the bumped wafer 320. The anisotropic conductive film 305 includes a plurality of conductive pillars 331A and 331B. The conductive crucibles 331A and 3 3 1 B are regularly arranged equidistantly and encapsulated in a resin 3 3 2 . S the bumped wafer 320 is bonded to the substrate 310 to cause the
凸塊3 23與對應之該些接合墊3丨3之間隙小於該些導電 柱331A與3318之柱高時，部分導電柱331A之兩端係 電性連接該些凸塊323與對應之該些接合墊3。。 在本實施例中，該些導電柱331A與331B之硬度係 大於該些凸塊323之硬度^上述在該些凸力⑵與對 -之省』接合》3 i 3之間的部分導電柱⑶A之一端係 :穿刺入該些凸塊323。因此，能達到低成本且高耐用 度的異方性導電接合效果When the gap between the bumps 3 23 and the corresponding bonding pads 3丨3 is smaller than the pillars of the conductive pillars 331A and 3318, the two ends of the conductive pillars 331A are electrically connected to the bumps 323 and corresponding thereto. Bonding pad 3. . In this embodiment, the hardness of the conductive pillars 331A and 331B is greater than the hardness of the bumps 323, and the partial conductive pillars (3) A between the convex force (2) and the opposite-state bond 3 3 3 One end system: punctures into the bumps 323. Therefore, the low-cost and high-durability anisotropic conductive bonding effect can be achieved.
1上所述’僅是本發明的赫社奋；U 月的較佳實施例而已，並非對 本發明作任何形式上的& ^ 例描+ (制，雖然本發明已以較佳實施 例揭路如上，然而並非用 香L 限疋本發明，任何孰悉本專 業的技術人員，在不，“不寻 利用 本發明技術方案範圍内，當可 才J用上；4揭示的技術内 變彳作出些許更動或修飾為等同 容，媸 疋未脫-本發明技術方案的内 各依據本發明的技術實質> 單修改'等同變化_飾A 所作的任何簡 範圍内。 >飾’均仍屬於本發明技術方案的 1332254· 【圖式簡單說明】 笫1圖：一種習知異方性導電接合之覆晶裝置之截面示 意圖。 第2圖：依據本發明之第一具體實施例，一種異方性導 電接合之覆晶裝置之截面示意圖。 第3圖：依據本發明之第一具體實施例，該異方性導電 接合之覆晶裝置中複數個導電柱之位置分布 示意圖。 第4A至4C圖：依據本發明之第一具體實施例，該異 方性導電接合之覆晶裝置於製程中一凸塊化 晶片之截面示意圖。 第5圖：依據本發明之第二具體實施例，另一種異方性 導電接合之覆晶裝置之截面示意圖。 【主要元 件 符號說明】 100 覆晶裝 置 110 基板 111 上表 面 112 下 表 面 113 接合墊 120 凸塊化 晶 片 121 主動 面 122 背 面 123 凸塊 130 異方性 導 電膠膜 131 導 電 球 132 金屬層 200 覆晶裝 置 210 基板 211 上表 面 212 下 表 面 213 接合墊 13 1332254' 220 凸塊化晶片 221 主動 面 222 背面 223 凸塊 230 異方性導電膠膜 231A導電柱 231B導電柱 232 樹脂 233 保護膠帶 300 覆晶裝置 310 基板 311 上表 面 312 下表面 313 接合墊 320 凸塊化晶片 321 主動 面 322 背面 323 凸塊 330 異方性導電膠膜 331A導電柱 331B導電柱 332 樹脂1 is merely a preferred embodiment of the present invention; U is a preferred embodiment of the present invention, and is not intended to be in any form of the present invention, although the invention has been disclosed in the preferred embodiment. The road is as above, but it is not limited to the invention. Anyone skilled in the art will not, "do not use the technical solution of the present invention, when it can be used; Make some changes or modifications to the equivalent, and do not take off - the technical essence of the present invention is in accordance with the technical essence of the present invention > single modification 'equivalent change _ decoration A is made in any simple range. 1332254 according to the technical solution of the present invention. [Simplified description of the drawings] FIG. 1 is a schematic cross-sectional view of a conventional flip-chip device for electrically conductive bonding. FIG. 2 is a cross-sectional view of a first embodiment according to the present invention. Schematic diagram of a cross-section of a square-shaped conductive bonding flip-chip device. FIG. 3 is a schematic view showing the position distribution of a plurality of conductive pillars in the anisotropic conductive bonding flip-chip device according to the first embodiment of the present invention. 4A to 4C Figure: In a first embodiment of the present invention, a cross-sectional view of a bumped wafer in the process of the anisotropic conductive bonding is performed. Figure 5: Another anisotropy in accordance with the second embodiment of the present invention Schematic diagram of the conductive bonding flip chip device. [Main component symbol description] 100 Flip chip device 110 Substrate 111 Upper surface 112 Lower surface 113 Bond pad 120 Bump wafer 121 Active surface 122 Back surface 123 Bump 130 Anisotropic conductive adhesive Film 131 Conductive ball 132 Metal layer 200 Flip chip device 210 Substrate 211 Upper surface 212 Lower surface 213 Bond pad 13 1332254' 220 Bump wafer 221 Active surface 222 Back surface 223 Bump 230 Anisotropic conductive film 231A Conductive column 231B Conductive Column 232 Resin 233 Protective Tape 300 Flip Chip Device 310 Substrate 311 Upper Surface 312 Lower Surface 313 Bonding Pad 320 Bumped Wafer 321 Active Surface 322 Back Side 323 Bump 330 Anisotropic Conductive Film 331A Conductive Post 331B Conductive Post 332 Resin
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