CN111554582B - Chip packaging method and chip packaging device - Google Patents
Chip packaging method and chip packaging device Download PDFInfo
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- CN111554582B CN111554582B CN202010532022.8A CN202010532022A CN111554582B CN 111554582 B CN111554582 B CN 111554582B CN 202010532022 A CN202010532022 A CN 202010532022A CN 111554582 B CN111554582 B CN 111554582B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
- H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
- H01L2021/60045—Pre-treatment step of the bump connectors prior to bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60277—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the use of conductive adhesives
Abstract
The application discloses a chip packaging method and a chip packaging device, and belongs to the technical field of packaging. According to the chip packaging method, the metal lug is formed at the position of the pad on the functional surface of the chip, then the insulating layer is formed on the periphery of the metal lug, the surface, away from the functional surface, of the insulating layer is lower than the surface, away from the functional surface, of the metal lug, and then the surface, away from the pad, of one side of the metal lug is electrically connected with the conductive part on the surface of the substrate through the conductive adhesive. After the electrical connection, at least part of the resin material and the insulating layer in the conductive adhesive wrap the side wall of the metal bump, so that the probability of the lateral conduction of the side wall of the metal bump and other metal bumps or other devices outside the chip packaging device is reduced, the probability of short circuit inside the chip packaging device is reduced, and the reliability of the electrical connection inside the chip packaging device is improved.
Description
Technical Field
The present disclosure relates to the field of packaging technologies, and in particular, to a chip packaging method and a chip packaging device.
Background
In the chip packaging process flow, the fabrication of the metal bump structure is one of the key processes, and the metal bump is used for realizing the electrical connection between the chip and the substrate in the chip packaging device. The specific packaging process comprises the following steps: forming a metal bump at a bonding pad position of the chip by using an electroplating process; and then electrically connecting the chip with the conductive part on the surface of the substrate by using the metal bump in a flip chip manner.
In the packaging process, the side wall of the metal bump may be transversely conducted with other metal bumps or other devices except the chip packaging device, or even short circuit occurs, so that the reliability of the internal electrical connection of the chip packaging device is reduced.
Disclosure of Invention
The technical problem mainly solved by the application is to provide a chip packaging method and a chip packaging device, which can reduce the probability of transverse conduction between a metal bump on a chip and other metal bumps or other devices outside the chip packaging device.
In order to solve the technical problem, the application adopts a technical scheme that:
a chip packaging method is provided, which comprises the following steps: respectively forming a metal bump at each bonding pad position on the chip functional surface; forming an insulating layer on the periphery of the metal bump, wherein the surface of the insulating layer, which is far away from the functional surface, is lower than the surface of the metal bump, which is far away from the functional surface; and electrically connecting the surface of one side, far away from the bonding pad, of the metal bump with a conductive part on the surface of the substrate by using conductive adhesive, wherein at least part of resin material in the conductive adhesive and the insulating layer wrap the side wall of the metal bump.
And the surface of one side of the metal bump, which is far away from the bonding pad, is flat.
A first passivation layer is arranged on the functional surface of the chip, and a first through hole is formed in the position, corresponding to the bonding pad, of the first passivation layer; the forming of the metal bumps at each pad position on the chip functional surface respectively comprises: respectively forming a first metal layer at each first through hole of the first passivation layer by electroplating; and forming a second metal layer on the side wall of the first metal layer and the surface of one side far away from the bonding pad by using a deposition mode, wherein the surface of one side of the second metal layer far away from the bonding pad is smooth, and the first metal layer and the second metal layer form the metal bump.
The insulating layer is an organic insulating layer, and the height of the organic insulating layer is greater than half of the height of the metal bump and less than the height of the metal bump.
The step of electrically connecting the surface of one side, far away from the pad, of the metal bump with the conductive part on the surface of the substrate by using the conductive adhesive comprises the following steps of: arranging the conductive adhesive at the position of the conductive part on the surface of the substrate, wherein the conductive adhesive comprises the resin material and conductive particles, and the conductive particles are dispersed in the resin material; aligning and attaching the surface of one side, far away from the bonding pad, of the metal lug with the conductive part, setting bonding temperature and applying bonding pressure to the non-functional surface of the chip so as to enable the organic insulating layer to be heated and flow to the surface of the substrate and extrude the conductive adhesive, enable the conductive particles, the metal lug and the conductive part to be electrically connected, and enable the organic insulating layer and part of the resin material to wrap the side wall of the metal lug.
Wherein the viscosity coefficient of the organic insulating layer is smaller than that of the conductive adhesive.
Wherein the diameter of the conductive particles is 1 micron to 5 microns, the standard deviation of the diameters of the conductive particles is 0.5 micron to 0.8 micron, and the number of the conductive particles at each metal bump position is less than or equal to 18.
Wherein, after the step of aligning and attaching the surface of one side of the metal bump away from the bonding pad and the conductive part, setting the bonding temperature and applying the bonding pressure on the non-functional surface of the chip, the method further comprises: and gradually releasing the bonding pressure and gradually reducing the bonding temperature until the curing degrees of the organic insulating layer and the conductive adhesive are within a preset range.
In order to solve the technical problem, the other technical scheme adopted by the application is as follows:
there is provided a chip packaging device including: the substrate, the surface of said substrate has conductive parts; the chip is provided with bonding pads on a functional surface, and the bonding pads correspond to the conductive parts one by one; the metal bump is arranged at the position of the bonding pad; the insulating layer is arranged on the periphery of the metal bump, and the height of the insulating layer is smaller than that of the metal bump; the conductive adhesive is arranged between the surface of one side, far away from the bonding pad, of the metal lug and the conductive part and electrically connects the metal lug and the conductive part; and at least part of the resin material in the conductive adhesive and the insulating layer wrap the side wall of the metal bump.
And the surface of one side of the metal bump, which is far away from the bonding pad, is flat.
The beneficial effect of this application is: different from the situation of the prior art, the chip packaging method provided by the application forms the metal bump at the pad position on the functional surface of the chip, then forms the insulating layer at the periphery of the metal bump, the surface of the insulating layer far away from the functional surface is lower than the surface of the metal bump far away from the functional surface, and then electrically connects the surface of one side of the metal bump far away from the pad with the conductive part on the surface of the substrate by using the conductive adhesive. After the electrical connection, at least part of the resin material and the insulating layer in the conductive adhesive wrap the side wall of the metal bump, so that the probability of the lateral conduction of the side wall of the metal bump and other metal bumps or other devices outside the chip packaging device is reduced, the probability of short circuit inside the chip packaging device is reduced, and the reliability of the electrical connection inside the chip packaging device is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings may be obtained according to these drawings without creative efforts. Wherein:
FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a chip packaging method according to the present application;
FIG. 2a is a schematic structural diagram of an embodiment corresponding to step S11 in FIG. 1;
FIG. 2b is a schematic structural diagram of an embodiment corresponding to step S12 in FIG. 1;
FIG. 2c is a schematic structural diagram of an embodiment corresponding to step S13 in FIG. 1;
FIG. 3 is a schematic flow chart illustrating one embodiment of the step included in step S11 in FIG. 1;
FIG. 4 is a schematic structural diagram of an embodiment corresponding to step S21 in FIG. 3;
FIG. 5 is a schematic flow chart diagram illustrating another embodiment of a chip packaging method according to the present application;
FIG. 6a is a schematic structural diagram of an embodiment corresponding to step S31 in FIG. 5;
FIG. 6b is a schematic structural diagram of an embodiment corresponding to step S32 in FIG. 5;
FIG. 6c is a schematic structural diagram of an embodiment corresponding to step S33 in FIG. 5;
fig. 7 is a schematic structural diagram of an embodiment corresponding to step S34 in fig. 5.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments that can be obtained by a person skilled in the art without making any inventive step based on the embodiments in the present application belong to the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating an embodiment of a chip packaging method according to the present application, the method including the following steps:
and S11, forming a metal bump at each bonding pad position on the functional surface of the chip respectively.
Specifically, referring to fig. 2a, fig. 2a is a schematic structural diagram of an embodiment corresponding to step S11 in fig. 1. In this embodiment, a first passivation layer 14 is disposed on the functional surface of the chip 11, the first passivation layer 14 is made of an insulating material such as a silicon oxide layer and silicon nitride, a first through hole (not shown) is disposed at a position of the first passivation layer 14 corresponding to the pad 111, and a size of the first through hole is smaller than or equal to a size of the pad 111. The present embodiment first forms a metal bump 12 at each pad 111 position on the functional surface of the chip 11, and the metal bump 12 is located at the first through hole position of the first passivation layer 14. Specifically, a patterned photoresist coating may be formed on the functional surface of the chip 11, a through hole is formed on the photoresist coating at a position corresponding to the pad 111 to expose the surface of the pad 111, a metal bump 12 is formed at the through hole of the photoresist coating, and then the photoresist coating is removed. Fig. 2a schematically shows the case of one pad 211 on the functional side of the chip 11.
If the metal bump is formed by a one-time electroplating process, due to the characteristics of the electroplating process, the surface of one side of the metal bump, which is far away from the pad 111, is recessed, and when the subsequent metal bump is electrically connected with the conductive part on the substrate, the recessed area makes the contact area between the metal bump and the conductive part smaller, which may cause the electrical problem of open circuit, and may also cause the mechanical problems of bubbles, delamination and even fracture at the interface of the electrical connection. The application preferably further processes the metal bump with the recessed surface to obtain a metal bump 12 with a flat surface a on the side away from the pad 111. The side surface a of the metal bump 12 away from the pad 111 may be planarized by, for example, grinding. For another example, the surface a of the side of the metal bump 12 away from the pad 111 may be planarized by stacking a plurality of metal layers, which will be described later.
And S12, forming an insulating layer on the periphery of the metal bump, wherein the surface of the insulating layer far away from the functional surface is lower than the surface of the metal bump far away from the functional surface.
Specifically, please refer to fig. 2b in conjunction with fig. 2a, and fig. 2b is a schematic structural diagram of an embodiment corresponding to step S12 in fig. 1. After the metal bump 12 with a flat surface is formed, an insulating layer 15 is formed on the periphery of the metal bump 12, and the surface of the insulating layer 15 away from the functional surface of the chip 11 is lower than the surface of the metal bump 12 away from the functional surface. Preferably, the insulating layer 15 is an organic insulating layer, and a distance h between a surface of the insulating layer 15 away from the functional surface of the chip 11 and the functional surface1Is less than the height h of the metal bump 122While being greater than the height h of the metal bump 122Half of (0.5 h)2<h1<h2. The material of the organic insulating layer may be polyimide, polytetrafluoroethylene, or polycarbonate.
And S13, electrically connecting the surface of one side of the metal bump, which is far away from the pad, with the conductive part on the surface of the substrate by using conductive adhesive, wherein at least part of the resin material and the insulating layer in the conductive adhesive wrap the side wall of the metal bump.
Specifically, please refer to fig. 2c in conjunction with fig. 2b, wherein fig. 2c is a schematic structural diagram of an embodiment corresponding to step S13 in fig. 1. After forming the insulating layer 15 on the periphery of the metal bump 12 with a flat surface, the chip 11 is turned over, and then the conductive adhesive 13 is used to electrically connect the surface a of one side of the metal bump 12 away from the pad 111 with the conductive part 100 on the surface of the substrate 200. The conductive paste 13 includes a resin material 131 and conductive particles 132 (e.g., silver-based conductive particles, gold-based conductive particles, copper-based conductive particles, etc.), and the conductive particles 132 are dispersed in the resin material 131. In the electrical connection process, the conductive particles 132 may form an electrical path between the surrounding metal bumps 12 and the conductive portion 100 by a tunneling effect, so as to achieve electrical connection. During the electrical connection, at least a portion of the resin material 131 flows to the sidewalls of the metal bump 12, and wraps the sidewalls of the metal bump 12 and the conductive part 100 together with the insulating layer 15.
In the conductive adhesive 13 of the present embodiment, at least a portion of the resin material 131 and the insulating layer 15 wraps the metal bump 12 and the side wall of the conductive part 100, so as to reduce the probability of lateral conduction between the side wall of the metal bump 12 and other metal bumps or other devices except the chip-packaged device, reduce the probability of short circuit inside the chip-packaged device, and improve the reliability of electrical connection inside the chip-packaged device.
In the above embodiment, in order to flatten the surface a of the metal bump 12 away from the pad 111, the metal bump 12 may be formed by the following steps, specifically referring to fig. 3, where fig. 3 is a flowchart of an embodiment of the step included in step S11 in fig. 1.
And S21, forming a first metal layer at each first through hole position of the first passivation layer by using an electroplating method.
Specifically, referring to fig. 4, fig. 4 is a schematic structural diagram of an embodiment corresponding to step S21 in fig. 3. First, a first metal layer 121 is formed at each first via hole of the first passivation layer 14 by electroplating. The thickness of the first metal layer 121 is greater than that of the first passivation layer 14, so as to facilitate the subsequent electrical connection with the conductive portion on the substrate. Before the first metal layer 121 is formed by an electroplating process, an under bump metal layer and an electroplating seed layer (not shown) may be formed by sputtering in the first through hole of the first passivation layer 14, for example, a titanium-tungsten alloy layer is used as the under bump metal layer to improve adhesion between the first metal layer 121 and the pad 111, and for example, a gold layer is used as the electroplating seed layer to improve quality of the first metal layer 121 formed by the electroplating process.
And S22, forming a second metal layer on the side wall of the first metal layer and the surface of one side far away from the pad by using a deposition mode, wherein the surface of one side far away from the pad of the second metal layer is flat, and the first metal layer and the second metal layer form a metal bump.
Specifically, please continue to refer to fig. 2 a. After the first metal layer 121 is formed by electroplating, a recessed region exists on a surface of the first metal layer 121 away from the pad 111 due to a characteristic of the electroplating process. In order to form the metal bump with a flat surface, the second metal layer 122 is formed on the sidewall of the first metal layer 121 and the surface of the side far away from the pad 111 by deposition, and the first metal layer 121 and the second metal layer 122 form the metal bump 12. For example, the second metal layer 122 may be formed by using a chemical vapor deposition process, an atomic layer deposition process, and the like, and then the second metal layer 122 on the surface of the first passivation layer 14 is removed by using a photolithography process and an etching process, so that the sidewall of the first metal layer 121 and the second metal layer 122 on the surface of the side far from the pad 111 are remained. Because the second metal layer 122 formed by the deposition process has a flat surface, the surface a of the metal bump 12 on the side away from the pad 111 is also flat.
In other embodiments, more metal layers may be sequentially formed to form the metal bump, for example, a copper layer is formed first, a nickel layer is formed next, a gold layer is formed next, and the three layers of copper, nickel and gold are combined to form the metal bump, which is similar to the steps S21-S22 and will not be described herein again.
In this embodiment, the surface a of the side of the metal bump 12 away from the pad 111 is flat, and there is no recessed area, when the metal bump 12 is electrically connected to the conductive part 100 on the substrate 200, the contact area between the metal bump 12 and the conductive part 100 is significantly increased compared to the recessed area, so as to improve the reliability of the connection between the metal bump 12 and the conductive part 100, reduce the probability of an open circuit at the electrical connection between the metal bump 12 and the conductive part 100 on the substrate 200, improve the mechanical connection strength between the metal bump 12 and the conductive part 100, and reduce the probability of bubbles, delamination or fracture at the connection.
In another embodiment, please refer to fig. 5, wherein fig. 5 is a schematic flowchart illustrating another embodiment of a chip packaging method according to the present application, the method including the following steps:
and S31, forming a metal bump at each bonding pad position on the functional surface of the chip respectively.
Specifically, referring to fig. 6a, fig. 6a is a schematic structural diagram of an embodiment corresponding to step S31 in fig. 5. In this embodiment, a first passivation layer 34 is disposed on the functional surface of the chip 31, the first passivation layer 34 is made of an insulating material such as a silicon oxide layer and silicon nitride, a first through hole (not shown) is disposed at a position of the first passivation layer 34 corresponding to the pad 311, and a size of the first through hole is smaller than or equal to a size of the pad 311. In the present embodiment, a metal bump 32 is first formed at each pad 311 on the functional surface of the chip 31, and the metal bump 32 is located at the first through hole on the first passivation layer 34, as described in the above embodiments, the metal bump 32 can be formed at the pad 311 by using a plating process in combination with a grinding process or a deposition process, so as to flatten the surface D of the side away from the pad 311. Fig. 6a schematically shows the case of two pads 311 on the functional side of the chip 31.
And S32, forming an insulating layer on the periphery of the metal bump, wherein the surface of the insulating layer far away from the functional surface is lower than the surface of the metal bump far away from the functional surface.
Specifically, please refer to fig. 6b in combination with fig. 6a, wherein fig. 6b is a schematic structural diagram of an embodiment corresponding to step S32 in fig. 5. After the metal bump 32 with a flat surface is formed, an insulating layer 35 is formed on the periphery of the metal bump 32, and the surface of the insulating layer 35 away from the functional surface of the chip 31 is lower than the surface of the metal bump 32 away from the functional surface. Preferably, the insulating layer 35 is an organic insulating layer, and the distance h from the surface of one side of the functional surface of the chip 31 to the functional surface is3Is less than the height h of the metal bump 324While being greater than the height h of the metal bump 324Half of (0.5 h)4<h3<h4. The material of the organic insulating layer may be polyimide, polytetrafluoroethylene, or polycarbonate.
And S33, arranging conductive adhesive at the conductive part position on the surface of the substrate, wherein the conductive adhesive comprises a resin material and conductive particles, and the conductive particles are dispersed in the resin material.
Specifically, please refer to fig. 6c in combination with fig. 6b, wherein fig. 6c is a schematic structural diagram of an embodiment corresponding to step S33 in fig. 5. At the same time of forming the insulating layer 35 at the periphery of the metal bump 32, a conductive adhesive 33 is disposed at the position of the conductive part 100 on the surface of the substrate 200, the conductive adhesive 33 includes a resin material 331 and conductive particles 332, and the conductive particles 332 are dispersed in the resin material 331.
Wherein the insulating layer 35 has a viscosity coefficient of eta1The viscosity coefficient of the conductive adhesive 33 is eta2The viscosity coefficient of the resin material 331 is eta0The three satisfy the following relations:
η1＜η2，
wherein r is the radius of the conductive particles, κ is the conductivity of the conductive particles, ε is the dielectric constant, ζ is the Zeta potential, and Φ is the volume fraction of the conductive particles.
The diameter of the conductive particles 332 is 1 micron to 5 microns, such as 1 micron, 3 microns, 5 microns, etc., that is, the diameter of the conductive particles 332 is much smaller than the diameter of the metal bump 32, and then a plurality of conductive particles 332 can be distributed between the metal bump 32 and the conductive portion 100 by using the tunneling effect to form an electrical path.
S34, aligning and attaching the surface of one side of the metal bump, which is far away from the bonding pad, with the conductive part, setting bonding temperature and applying bonding pressure on the non-functional surface of the chip so as to enable the organic insulating layer to be heated and flow to the surface of the substrate and extrude the conductive adhesive, enable the conductive particles, the metal bump and the conductive part to be electrically connected, and enable the organic insulating layer and part of the resin material to wrap the side wall of the metal bump.
Specifically, please refer to fig. 7 in conjunction with fig. 6c, and fig. 7 is a schematic structural diagram of an embodiment corresponding to step S34 in fig. 5. After the conductive adhesive 33 is disposed, the chip 31 is turned over, a side surface D of the metal bump 32 away from the pad 311 is aligned and attached to the conductive portion 100, a bonding temperature is set, and a bonding pressure is applied to the non-functional surface of the chip 31, so that the insulating layer 35 is heated to flow to the surface of the substrate 200 and squeeze the conductive adhesive 33, the conductive particles 332, the metal bump 32 and the conductive portion 100 are electrically connected, and the insulating layer 35 and a part of the resin material 331 wrap the side walls of the metal bump 32 and the conductive portion 100. It is preferable to set the bonding pressure to 1000-1200 μ N (e.g., 1000 μ N, 1128 μ N, 1200 μ N, etc.), the bonding temperature to 145-165 ℃ (e.g., 145 ℃, 156 ℃, 165 ℃, etc.), and the time for applying the bonding pressure to 5-10s (e.g., 5s, 8s, 10s, etc.).
In this embodiment, the resin material 331 includes at least one of Polyethylene (PE), polyvinyl chloride (PVC), Polystyrene (PS), and polypropylene (PP), the conductive particles 332 includes at least one of gold nanoparticles and copper nanoparticles provided with an organic coating, and the organic coating can protect the copper nanoparticles from oxidation and loss of conductivity. Under the subsequent pressing action, the organic coating layer at the periphery of the copper nanoparticles is broken, so that the copper nanoparticles are in contact with the surrounding metal bumps 32 and the conductive parts 100.
Due to the viscosity coefficient eta of the organic insulating layer 351Less than the viscosity coefficient eta of the conductive adhesive 332The conductive paste 33 is formed by dispersing the conductive particles 332 in the resin material 331, and has a charge-sticking effect, and after the bonding temperature is applied, the organic insulating layer 35 expands due to heat, has fluidity, and flows down to the surface of the substrate 200. Then, the conductive paste 33 is also heated and has fluidity, and is pressed by the organic insulating layer 35, and the conductive particles 332 and a part of the resin material 331 are held between the metal bumps 32 and the conductive portions 100 to absorb stress, so that the conductive particles 332, the metal bumps 32, and the conductive portions 100 are electrically connected. Preferably, the number of the conductive particles 332 at the position of each metal bump 32 is less than or equal to 18, and the connection resistance is at this timeLower, higher resistivity. The remaining portion of the resin material 331 flows to the sidewalls of the metal bumps 32, and wraps the metal bumps 32 and the sidewalls of the conductive portions 100 together with the organic insulating layer 35.
In the present embodiment, when the conductive adhesive 33 is used to electrically connect the metal bump 32 and the conductive part 100, the insulating layer 35 pre-disposed at the periphery of the metal bump 32 is heated to expand and extrude the conductive adhesive 33, so as to improve the capturing capability of the metal bump 32 on the conductive particles 332, so that the conductive particles 332 are distributed between the metal bump 32 and the conductive part 100 to form electrical connection, thereby improving the reliability of the electrical connection. Moreover, the surface of the side of the metal bump 32 away from the pad 311 is flat, no concave area exists, and the contact area between the metal bump 32 and the conductive part 100 is large, so that the connection reliability of the electrical connection between the metal bump 32 and the conductive part 100 is further improved, and the mechanical connection strength between the metal bump 32 and the conductive part 100 can also be improved. Further, the insulating layer 35 and a portion of the resin material 331 wrap the periphery of the metal bump 32, so that the metal bump 32 can be prevented from being laterally conducted, and the reliability of electrical connection can be further improved.
In another embodiment, after the step S34, that is, after the steps of aligning and attaching the surface of the metal bump away from the pad to the conductive portion, setting the bonding temperature and applying the bonding pressure to the non-functional surface of the chip, the method may further include the following steps:
the bonding pressure is gradually released and the bonding temperature is gradually decreased until the curing degree of the insulating layer 35 and the conductive adhesive 33 is within a preset range, preferably between 85% and 92%, such as 85%, 88%, 92%, etc. The bonding pressure is slowly released and the bonding temperature is gradually cooled to room temperature, so that elastic recovery of organic matters, resin, metal bumps or conductive particles caused by sudden pressure and temperature release can be prevented, and larger cracks are generated between the metal bumps and the conductive part, and further larger connection resistance is caused.
The present application further provides a chip package device formed by the above chip package method, please continue to refer to fig. 7, where fig. 7 is a schematic structural diagram of an embodiment of the chip package device of the present application, and the chip package device includes: substrate 200, chip 31, metal bumps 32, insulating layer 35, and conductive paste 33. Wherein, the surface of the substrate 200 is provided with the conductive part 100; pads 311 are arranged on the functional surface of the chip 31, and the pads 311 correspond to the conductive parts 100 one by one; the metal bump 32 is disposed at the pad 311; the insulating layer 35 is disposed on the periphery of the metal bump 32, and the insulating layer 35 fills the space between the chip 31 and the substrate 200; the conductive adhesive 33 is disposed between the conductive portion 100 and a surface of the metal bump 32 away from the pad 311, electrically connecting the metal bump 32 with the conductive portion 100, and at least a portion of the resin material 331 and the insulating layer 35 in the conductive adhesive 33 wraps a sidewall of the metal bump 32. A first passivation layer 34 is disposed on the functional surface of the chip 31, a first through hole (not labeled) is disposed at a position corresponding to the pad 311, the metal bump 32 is disposed at the first through hole, and a surface of a side of the metal bump 32 away from the pad 311 is flat.
Further, in this embodiment, the metal bump 32 includes a first metal layer 321 and a second metal layer 322, the first metal layer 321 is formed by an electroplating process and corresponds to the bonding pads 311 one to one, a recessed area exists on a surface of one side of the first metal layer 321, which is far away from the bonding pads 311, and the second metal layer 322 is formed by a deposition process and has a flat surface on a side of the second metal layer 322, which is far away from the bonding pads 311, so that a surface of one side of the metal bump 32, which is far away from the bonding pads 311, is also flat.
Further, the conductive paste 33 in this embodiment includes a resin material 331 and conductive particles 332, the conductive particles 332 are located between the metal bump 32 and the conductive portion 100, at least a portion of the resin material 331 is located between the metal bump 32 and the conductive portion 100, and the rest of the resin material 331 is located between the insulating layer 35 and the sidewall of the metal bump 32, and wraps the metal bump 32 and the sidewall of the conductive portion 100 together with the insulating layer 35. Wherein the conductive particles 332 comprise at least one of gold nanoparticles and copper nanoparticles.
In the present embodiment, the surface of the side of the metal bump 32 away from the pad 311 is flat, and there is no recessed area, when the metal bump 32 is electrically connected to the conductive part 100 on the substrate 200, the contact area between the metal bump 32 and the conductive part 100 is significantly increased compared to the recessed area, so as to improve the connection reliability of the electrical connection between the metal bump 32 and the conductive part 100, reduce the probability of an open circuit at the electrical connection between the metal bump 32 and the conductive part 100, and simultaneously improve the mechanical connection strength between the metal bump 32 and the conductive part 100, and reduce the probability of bubbles, delamination or fracture at the connection. Moreover, the insulating layer 35 and the resin material 331 are wrapped around the metal bump 32, so that the metal bump 32 can be prevented from being laterally conducted, and the reliability of electrical connection can be further improved.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (8)
1. A method of chip packaging, comprising:
respectively forming a metal bump at each bonding pad position on the chip functional surface; a first passivation layer is arranged on the chip functional surface, and a first through hole is formed in the position, corresponding to the bonding pad, of the first passivation layer;
forming an insulating layer on the periphery of the metal bump, wherein the surface of the insulating layer, far away from the functional surface, is lower than the surface of the metal bump, far away from the functional surface;
electrically connecting the surface of one side, far away from the bonding pad, of the metal bump with a conductive part on the surface of the substrate by using conductive adhesive, wherein at least part of resin material in the conductive adhesive and the insulating layer wrap the side wall of the metal bump;
wherein, the step of respectively forming the metal bump at each bonding pad position on the chip functional surface comprises the following steps:
respectively forming a first metal layer at each first through hole of the first passivation layer by electroplating;
and forming a second metal layer on the side wall of the first metal layer and the surface of one side far away from the bonding pad by using a deposition mode, wherein the surface of one side of the second metal layer far away from the bonding pad is smooth, and the first metal layer and the second metal layer form the metal bump.
2. The chip packaging method according to claim 1,
the insulating layer is an organic insulating layer, and the height of the organic insulating layer is greater than half of the height of the metal bump and less than the height of the metal bump.
3. The chip packaging method according to claim 2, wherein the step of electrically connecting the surface of the metal bump on the side away from the pad with the conductive part on the surface of the substrate by using the conductive adhesive comprises:
arranging the conductive adhesive at the conductive part position on the surface of the substrate, wherein the conductive adhesive comprises the resin material and conductive particles, and the conductive particles are dispersed in the resin material;
aligning and attaching the surface of one side, far away from the bonding pad, of the metal lug with the conductive part, setting bonding temperature and applying bonding pressure to the non-functional surface of the chip so as to enable the organic insulating layer to be heated and flow to the surface of the substrate and extrude the conductive adhesive, enable the conductive particles, the metal lug and the conductive part to be electrically connected, and enable the organic insulating layer and part of the resin material to wrap the side wall of the metal lug.
4. The chip packaging method according to claim 3, wherein the viscosity coefficient of the organic insulating layer is smaller than that of the conductive adhesive.
5. The chip packaging method according to claim 3,
the conductive particles have a diameter of 1-5 microns, a standard deviation of the diameters of the conductive particles is 0.5-0.8 microns, and the number of conductive particles at each metal bump location is less than or equal to 18.
6. The chip packaging method according to claim 3, wherein the step of aligning and attaching the surface of the metal bump away from the pad to the conductive portion, setting a bonding temperature and applying a bonding pressure to the non-functional surface of the chip further comprises:
and gradually releasing the bonding pressure and gradually reducing the bonding temperature until the curing degrees of the organic insulating layer and the conductive adhesive are within a preset range.
7. A chip packaging device, comprising:
a substrate, a surface of which is provided with a conductive portion;
the chip comprises a chip, wherein a functional surface of the chip is provided with bonding pads, the bonding pads are in one-to-one correspondence with the conductive parts, a first passivation layer is arranged on the functional surface of the chip, and a first through hole is formed in the position, corresponding to the bonding pads, of the first passivation layer;
the metal bump is arranged at the position of the bonding pad and comprises a first metal layer and a second metal layer, the first metal layer is positioned at the position of each first through hole, and the first metal layer is formed in an electroplating mode; the second metal layer is positioned on the side wall of the first metal layer and the surface of one side far away from the bonding pad, the surface of one side of the second metal layer far away from the bonding pad is smooth, and the second metal layer is formed in a deposition mode;
the insulating layer is arranged at the periphery of the metal bump and fills the space between the chip and the substrate;
and the conductive adhesive is arranged between the surface of one side of the metal lug, which is far away from the bonding pad, and the conductive part, and is used for electrically connecting the metal lug with the conductive part, and at least part of resin material in the conductive adhesive and the insulating layer wrap the side wall of the metal lug.
8. The chip packaging device according to claim 7, wherein a side of the metal bump away from the pad is planarized.
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