JP3929154B2 - Mounting structure of semiconductor device and mounting method thereof - Google Patents

Mounting structure of semiconductor device and mounting method thereof Download PDF

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JP3929154B2
JP3929154B2 JP01548198A JP1548198A JP3929154B2 JP 3929154 B2 JP3929154 B2 JP 3929154B2 JP 01548198 A JP01548198 A JP 01548198A JP 1548198 A JP1548198 A JP 1548198A JP 3929154 B2 JP3929154 B2 JP 3929154B2
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semiconductor device
metal film
film
conductive particles
substrate
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JPH11214420A (en
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正義 菊地
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Citizen Watch Co Ltd
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Citizen Watch Co Ltd
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8134—Bonding interfaces of the bump connector
    • H01L2224/81345—Shape, e.g. interlocking features
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8336—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/83365—Shape, e.g. interlocking features
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
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    • H01L2224/92—Specific sequence of method steps
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    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、ＴＶやコンピューターなどの情報機器の表示体として使用される液晶表示装置基板に半導体装置を実装したチップオングラス（ＣＯＧ）方式、および電子機器に内蔵され制御を行う基板に半導体装置を実装したチップオンボード（ＣＯＢ）方式による半導体装置の実装構造およびその実装方法に関する。
【０００２】
【従来の技術】
以下液晶表示基板へ半導体装置を実装したＣＯＧ方式を用いて本発明の従来技術を説明する。
【０００３】
半導体装置を異方性導電フィルムを介して基板上に実装した従来技術を図６と図７と図８を用いて説明する。
図６は半導体装置を異方性導電フィルムを介して基板上に設けたことを示す断面図である。図７は半導体装置のアルミパッド上に設けるストレートウォール型のバンプを示す断面図である。図８は半導体装置のアルミパッド上に設けるマッシュルーム型のバンプを示す断面図である。
【０００４】
まずはじめに、図６にしめした半導体装置の実装構造の従来技術について説明する。
図６にしめすように、基板６０の上に設ける配線７０と、基板６０上に設ける導電性粒子９０を有する異方性導電フィルム８０と、基板６０上に設けるバンプ４５を有する半導体装置１０とで構成され、半導体装置１０と基板６０との間には異方性導電フィルム８０を挟み、配線７０とバンプ４５との間には異方性導電性フィルム８０中の導電性粒子９０を挟み電気的に接続し、隣接したバンプ４５間では導電性粒子９０を挟まないために絶縁性をもつ。
【０００５】
半導体装置１０はアルミパッド２０とアルミパッド２０上に開口部を有する絶縁膜３０とを有し、開口部のアルミパッドと絶縁膜３０上にまたがって共通電極膜４２を設け、共通電極膜上にバンプ４５を設ける。
【０００６】
図６にしめす導電性粒子９０は有機高分子樹脂の表面にＮｉ＋Ａｕを形成したもので直径５μｍ〜１０μｍの間のものを用いる。
【０００７】
図６には図示はしていないが、１Ω以下の電気的導通を得るために、基板６０の配線７０とバンプ４５との間に挟む導電性粒子９０は少なくとも１０個程度必要である。直径５μｍの導電性粒子９０を用いた場合、バンプ４５上面の面積は３０００μｍ2 以上必要である。
【０００８】
図６にしめす従来技術の実装構造での半導体装置１０に設けたバンプ４５の高さは、導電性粒子９０をバンプ４５上に効率よく捕捉し、さらに異方性導電フィルム８０の樹脂で半導体装置１０と基板６０との間を充填するために、１０μｍ〜２０μｍの間で設計するのが望ましい。
【０００９】
図７にしめすように、半導体装置１０はアルミパッド２０とアルミパッド２０上に開口部を有する絶縁膜３０とを有し、開口部のアルミパッドと絶縁膜３０上にまたがって共通電極膜４２を設け、共通電極膜上にストレートウォール型のバンプ４５を設ける。
【００１０】
図７にしめす従来技術は、半導体装置１０上にストレートウォール型のバンプ４５を設ける例で、高さは１０〜２０μｍの間で設ける。また、バンプ４５上面の面積が３０００μｍ2 以上必要なため、仮に接続ピッチ８０μｍでバンプ間ギャップ２０μｍの設計にすると、バンプサイズは６０μｍ×５０μｍとなる。
【００１１】
図７にしめしたストレートウォール型のバンプ４５は主にＡｕでメッキ法により設ける。バンプ４５下部には半導体装置１０のアルミパッド２０とバンプ４５の材質であるＡｕとの相互拡散を防ぐための金属と、バンプ４５の密着性を保つ機能をもつ金属との、少なくとも２層の共通電極膜４２を設けることが一般的である。
【００１２】
図６にしめす構造では、図７で説明した半導体装置を用いた例であり、直径５μｍの導電性粒子９０とストレートウォール型バンプ４５とを用いた場合、接続ピッチは５０μｍまで対応することが可能である。
【００１３】
図８にしめすように、半導体装置１０はアルミパッド２０とアルミパッド２０上に開口部を有する絶縁膜３０とを有し、開口部のアルミパッドと絶縁膜３０上にまたがって共通電極膜４２を設け、共通電極膜上にマッシュルーム型のバンプ４５を設ける。
【００１４】
図８にしめしたマッシュルーム型バンプ４５はＡｕあるいはＣｕ＋Ａｕでメッキ法により設ける。ストレートウォール型バンプと同様にバンプ４５下部には半導体装置１０のアルミパッド２０とバンプ４５のＡｕとの相互拡散を防ぐための金属と、バンプ４５の密着性を保つ機能をもつ金属との少なくとも２層の共通電極膜４２を設けるのが一般的である。
【００１５】
図６で説明した半導体装置の替わりに、図８にしめす半導体装置を用いてもよく、直径５μｍの導電性粒子９０とマッシュルーム型バンプ４５とを用いた実装構造の場合、接続ピッチは８０μｍまで対応することが可能である。
【００１６】
メッキ法によりストレートウォール型バンプやマッシュルーム型バンプは設けるが、バンプ高さ４５のバラツキは１５μｍバンプにおいて４μｍ（±２μｍ）発生する。
【００１７】
【発明が解決しようとする課題】
液晶表示装置は、年々高精細表示が要求されており、画素ピッチが２０μｍ〜４０μｍのものが出てきている。
【００１８】
半導体装置１０のバンプ４５の接続ピッチは直径５μｍの導電性粒子９０を有する異方性導電フィルム８０とストレートウォール型のバンプ４５とを用いた実装構造の場合５０μｍピッチが最小である。
【００１９】
したがって、画素ピッチを広げて半導体装置１０を実装するエリアに設計しなければならない。画素ピッチを広げることで、液晶表示装置の額縁面積を大きくしなければならず、液晶表示装置の商品価値を落とすことになる。
【００２０】
直径５μｍより小さい導電性粒子９０を有する異方性導電フィルム８０を用いれば、接続ピッチとしては２０μｍ〜４０μｍに対応したバンプ設計が可能であるが、メッキ法によるバンプ高さバラツキが４μｍ（±２μｍ）あるために、バンプ高さが４μｍ低いと基板６０の配線７０とバンプ４５との電気的接続が不安定となり液晶表示装置の表示不良を招く。
【００２１】
また、画素ピッチ２０μｍに対応したバンプ接続ピッチ２０μｍを得るためには、ストレートウォール型バンプの形成において厚さ１０μｍ〜２０μｍのレジストの開口幅を１０μｍ以下で形成せねばならず、アスペクト比が厳しくなりレジストの安定した形成が困難となる。
【００２２】
図８にしめす半導体装置１０の接続ピッチは直径５μｍの導電性粒子９０を有する異方性導電フィルム８０とマッシュルーム型のバンプ４５とを用いた実装構造においては８０μｍピッチが最小である。
【００２３】
したがって、ストレートウォール型よりも、さらに画素ピッチを広げて半導体装置１０を実装するエリアに設計しなければならない。画素ピッチを広げることで、液晶表示装置の額縁面積を大きくしなければならず、ストレートウォール型と同様に液晶表示装置の商品価値を落とすことになる。
【００２４】
接続ピッチ２０μｍに対応する、高さ１０μｍ〜２０μｍのマッシュルーム型バンプ４５の形成は、傘をもつ構造上形成不可能である。
【００２５】
（発明の目的）上記課題を解決するために、本発明では導電性粒子９０を用いて、高さバラツキのない電極４０を提供し、液晶表示装置の画素ピッチに対応する半導体装置の実装構造およびその実装方法を提供することを目的とする。
【００２６】
【課題を解決するための手段】
上記目的を達成するために、本発明は以下に示した半導体装置とその製造方法およびその実装構造を採用する。
【００２７】
本発明の半導体装置の実装構造は、アルミパッド上に開口部を有する絶縁膜と、開口部内のアルミパッド上と絶縁膜とにまたがって設けた複数の層からなる金属膜と、その金属膜上に設けられ絶縁膜の開口部より大きく形成されている感光性樹脂とを有する半導体装置を、基板上の配線と接続する半導体装置の実装構造であって、金属膜は感光性樹脂をマスクとしてマスクの開口部の金属膜を除去することによって形成されており、感光性樹脂を残したまま半導体装置と基板との間に導電性粒子を分散した絶縁性樹脂を設け、金属膜の膜厚を導電性粒子の０．５倍から２倍の範囲に設定し、絶縁性樹脂で半導体装置と基板とを接着し、かつ導電性粒子のうち、金属膜と配線との間に挟み込まれた導電性粒子によって、金属膜と配線とを電気的に導通させたことを特徴とする。
【００２８】
本発明の半導体装置の実装構造は、感光性樹脂の厚さが０．１μｍより大きく導電粒子の直径の８０％を越えないことを特徴とする。
【００２９】
本発明の半導体装置の実装方法は、半導体装置を導電性粒子を分散した絶縁性樹脂を介して基板上の配線と接続する半導体装置の実装方法において、半導体装置上に設けるアルミパッド上に開口部を有する絶縁膜を形成する工程と、開口部内のアルミパッド上と絶縁膜とにまたがって複数の層からなる金属膜を形成する工程と、金属膜上に絶縁膜の開口部より大きい感光性樹脂からなるマスクを形成する工程と、マスクの開口部の金属膜をエッチング除去する工程と、絶縁性樹脂を基板上に加熱して貼り付ける工程と、基板上に設ける配線と半導体装置に設ける金属膜とを位置合わせして半導体装置の裏面側から加圧加熱し、絶縁性樹脂を硬化させる工程とを有し、感光性樹脂を残したまま絶縁性樹脂で半導体装置と基板とを接着し、かつ導電性粒子のうち、金属膜と配線との間に挟み込まれた導電性粒子によって、金属膜と配線とを電気的に導通させたことを特徴とする。
【００３０】
本発明の半導体装置の実装方法は、感光性樹脂の厚さが０．１μｍより大きく導電粒子の直径の８０％を越えないことを特徴とする。
【００３１】
（作用）
本発明の半導体装置は電極を金属膜で設けるために、金属膜の高さバラツキ範囲が従来のメッキ法と比較して０．５μｍ以下と小さくすることができる。
さらに、金属膜の上に感光性樹脂を設けることで、金属膜と空気との接触を防止して金属膜表面の酸化進行を防止するため、安価で良導体であるＡｇやＣｕを用いることができる。
【００３２】
直径５μｍより小さい導電性粒子を有する異方性導電フィルムを適用でき、金属膜の上部面積を３０００μｍ２より小さくすることが可能となり、４０μｍより小さな接続ピッチに対応することができる。
【００３３】
上記構成により、液晶表示装置の画素ピッチ２０〜４０μｍに対応した接続ピッチにおいても、額縁幅を大きくすることなく、安定した接続を保つことが可能になる。
【００３４】
【発明の実施の形態】
以下に図面を用いて本発明を実施するための最適な実施形態における半導体装置とその製造方法およびその実装構造を説明する。本発明の実施形態を図１から図５を用いて説明する。
図１は半導体装置３０を配線２０を有する基板１０に異方性導電フィルム６０を設けた断面図である。図２〜図５は図１で用いた半導体装置の製造方法を工程順に説明する断面図である。
【００３５】
〔半導体装置の構造：図５〕
まずはじめに、図５を用いて、本発明の実施形態における半導体装置を説明する。
図５にしめすように、半導体装置１０はアルミパッド２０と絶縁膜３０と金属膜４０から構成され、絶縁膜３０はアルミパッド２０上に開口部を有し、アルミパッド２０と絶縁膜３０にまたがって金属膜４０を有し、金属膜上に感光性樹脂５０を設ける。絶縁膜３０はＳｉＮ膜からなり、金属膜４０はＣｒとＣｕの２層膜からなる。
【００３６】
〔実装構造：図１〕
つぎに、図１を用いて、本発明の実施形態における半導体装置の実装構造を説明する。
図１に示すように、基板６０上に設ける配線７０と、基板６０上に設けた異方性導電フィルム８０と、基板６０上に設ける金属膜４０を有する半導体装置１０とから構成され、半導体装置１０と基板６０の間には異方性導電フィルム８０を挟み、配線７０と金属膜４０のあいだには異方性導電フィルム８０中の導電性粒子９０を挟み電気的に接続し、隣接した金属膜４０間では導電性粒子９０を挟まないために絶縁性をもつ。
【００３７】
金属膜４０の周囲および金属膜４０と配線７０とのあいだには、金属膜の幅よりも大きく感光性樹脂５０を設け、感光性樹脂５０は配線７０に接触しない高さで設ける。
【００３８】
異方性導電フィルム８０は、絶縁性の樹脂に導電性粒子９０を分散したものを用いる。
導電性粒子９０は、高分子樹脂に有機高分子樹脂の表面にＮｉ＋Ａｕを形成したもので直径５μｍより小さいものを用いる。
【００３９】
半導体装置１０に設けた電極４０は高さが２μｍ〜１０μｍの間にあり、基板６０の配線７０と対応した位置で異方性導電フィルム８０を介して基板６０上に設ける。
【００４０】
金属膜４０と配線７０のあいだには導電性粒子９０を挟み、導電性粒子９０を５％〜５０％変形させた状態で異方性導電フィルム８０の樹脂を硬化させ、電気的導通をとる。
【００４１】
金属膜４０の厚さは、導電性粒子９０の直径の０．５倍〜２倍あれば良い。
０．５倍より小さい場合には、導電性粒子９０を５０％変形させる圧力条件で半導体装置１０を基板６０に実装した場合に、金属膜４０の無い部分において半導体装置１０と基板６０との間で導電性粒子９０がつぶれることになり、半導体装置１０に設けた絶縁膜３０にクラックを生じ好ましくない。
【００４２】
感光性樹脂５０の厚さは、電気的接続を担う導電性粒子９０の直径よりも小さいことが望ましい。
直径よりも厚い場合は、半導体装置１０を基板６０に位置合わせして加熱加圧したときに、金属膜４０上の感光性樹脂５０が基板側に接触して広がり、導電性粒子９０を金属膜４０の外側に押し出すことになり、金属膜４０上の導電性粒子９０の数を減らすこととなり好ましくない。
【００４３】
感光性樹脂５０を金属膜４０上に設けるために、金属膜表面と空気との接触を防止できる効果を有する。したがって、ＡｇやＣｕなどの比較的酸化されやすい金属を使用することが可能となり、コストを下げることができる。
【００４４】
金属膜の高さ寸法が１０μｍ以下のために、異方性導電フィルム８０を用いて半導体装置１０を圧着する際、導電性粒子９０が金属膜４０にすぐに捕捉されるため、金属膜４０上に効率的に導電性粒子９０を挟み込むことができる効果が得られる。
【００４５】
（製造方法：図２〜図５）
つぎに図２から図６を用いて半導体装置の製造方法を工程順に説明する。
図２に示すように、半導体装置１０に設けられたアルミパッド３０上に開口部を有する絶縁膜３０を厚さ０．５μｍ〜５μｍの間で形成する。
絶縁膜３０はＣＶＤ法によりＳｉＮ膜を形成し、フォトリソエッチングによりアルミパッド２０上に開口部を形成する。
【００４６】
つぎに図３に示すように、半導体装置１０の全面にスパッタリング法により、ＣｒとＣｕからなる金属膜４０を形成する。
金属膜４０の厚さは導電性粒子９０の直径の０．５〜２倍の間の厚さで形成する。
【００４７】
つぎに図４に示すように、絶縁膜３０の開口部よりも大きく、感光性樹脂５０をフォトリソにより形成する。絶縁膜３０の開口部の大きさと同じかあるいは小さい場合は、金属膜４０のエッチング除去の際アルミパッド２０を同時にエッチングして不良を起こすため、開口部より２μｍ以上大きくする。
感光性樹脂５０の厚さは０．１μｍ以上で導電性粒子９０の直径の８０％以下の間で設けるのが望ましい。
【００４８】
感光性樹脂５０の厚さが０．１μｍより小さい場合は、金属膜４０の表面の酸化防止効果が充分に得られない。また、感光性樹脂５０の厚さが導電性粒子９０の直径の８０％を越えた場合は半導体装置１０を基板６０に実装したときに感光性樹脂５０が配線７０と接触して広がり、導電性粒子９０を金属膜４０の外側へ押し出してしまい好ましくない。
【００４９】
最後に図５に示すように、感光性樹脂５０をマスクにして、金属膜４０をエッチングすることで感光性樹脂５０の開口部の金属膜４０を除去する。
【００５０】
従来技術のバンプではメッキ法により、バンプを１０μｍから２０μｍの高さで形成していたために高さバラツキが４μｍ（±２μｍ）発生していたが、金属膜４０だけで金属膜４０を形成するために高さバラツキが０．５μｍ以下と非常に小さくする効果が得られる。
【００５１】
金属膜４０上に感光性樹脂５０を設ける構造のため、金属膜４０と空気との接触を防止でき、金属膜４０の表面酸化進行を防止できるため、ＣｕやＡｇからなる金属を用いることが可能となり、コストを低減できる効果が得られる。
さらに、メッキ法のプロセスと感光性樹脂の剥離プロセスを必要としないために、従来技術よりも工程を短縮する効果が得られる。
【００５２】
〔実装方法説明〕
基板６０に異方性導電フィルム８０を温度９０℃で貼り付ける。基板６０の配線７０と半導体装置１０の金属膜４０とを位置合わせして半導体装置１０の裏面側から加圧加熱し、異方性導電フィルム８０を硬化させる。
【００５３】
加圧、加熱した時に、半導体装置１０に設けた金属膜４０と基板６０上に設けた配線７０との間に導電性粒子９０が挟み込まれる。図１にしめすように挟み込まれた導電性粒子９０は電気的に導通し、挟み込まれない導電性粒子９０は絶縁性をもつ。
【００５４】
【発明の効果】
以上の説明で明らかなように、本発明によれば、従来のバンプより高さ均一性の良い金属膜が得られるために、粒径の小さい導電性粒子９０を分散させた異方性導電フィルムを用いて、４０μｍを切る微細ピッチに対応した接続実装構造を得ることができる。
従来のバンプ形成工程よりも金属膜の形成工程は工数を短縮できるために、製造コストを低減することができる。
【００５５】
また、金属膜上に感光性樹脂を設ける構造のため、金属膜と空気との接触を防止でき、金属膜の表面酸化進行を防止できるため、ＣｕやＡｇからなる金属を用いることが可能となり、コストを低減できる効果が得られる。
【００５６】
バンプと異なり金属膜の高さが低いために、熱圧着した際に導電性粒子９０の流れを抑えることができ、金属膜上に効果的に導電性粒子９０を捕捉することができる。
【００５７】
従来技術のバンプではバンプをマスクとして共通電極膜のエッチングを行っていた。特にウェットエッチングではバンプ材質と共通電極膜材質との間で局部電池効果により共通電極膜のエッチングレートが速くなりエッチングマージンを大きく確保する必要があったが、本発明では感光性樹脂をマスクとして金属膜をエッチングするために局部電池効果が発生せず、エッチングマージンを広げることができる。
同じエッチングマージンを選択すれば従来技術よりも微細ピッチに対応した設計値に変更できる。
【図面の簡単な説明】
【図１】本発明の実施形態における半導体装置の実装構造を示す断面図である。
【図２】本発明の実施形態における半導体装置の製造方法を示す断面図である。
【図３】本発明の実施形態における半導体装置の製造方法を示す断面図である。
【図４】本発明の実施形態における半導体装置の製造方法を示す断面図である。
【図５】本発明の実施形態における半導体装置の製造方法を示す断面図である。
【図６】従来技術における半導体装置の実装構造を示す断面図である。
【図７】従来技術における半導体装置の構造を示す断面図である。
【図８】従来技術における半導体装置の構造を示す断面図である。
【符号の説明】
１０ 半導体装置
２０ アルミパッド
３０ 絶縁膜
４０ 金属膜
４２ 共通電極膜
４５ バンプ
５０ 感光性樹脂
６０ 基板
７０ 配線
８０ 異方性導電フィルム
９０ 導電性粒子[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a chip-on-glass (COG) system in which a semiconductor device is mounted on a liquid crystal display substrate used as a display body of information equipment such as a TV and a computer, and a semiconductor device incorporated in an electronic device to be controlled. The present invention relates to a mounted structure of a semiconductor device by a mounted chip-on-board (COB) method and a mounting method thereof .
[0002]
[Prior art]
The prior art of the present invention will be described below using a COG method in which a semiconductor device is mounted on a liquid crystal display substrate.
[0003]
A conventional technique in which a semiconductor device is mounted on a substrate via an anisotropic conductive film will be described with reference to FIGS. 6, 7, and 8. FIG.
FIG. 6 is a cross-sectional view showing that a semiconductor device is provided on a substrate via an anisotropic conductive film. FIG. 7 is a cross-sectional view showing a straight wall type bump provided on an aluminum pad of a semiconductor device. FIG. 8 is a cross-sectional view showing a mushroom-type bump provided on an aluminum pad of a semiconductor device.
[0004]
First, the prior art of the semiconductor device mounting structure shown in FIG. 6 will be described.
As shown in FIG. 6, the wiring 70 provided on the substrate 60, the anisotropic conductive film 80 having the conductive particles 90 provided on the substrate 60, and the semiconductor device 10 having the bump 45 provided on the substrate 60. The anisotropic conductive film 80 is sandwiched between the semiconductor device 10 and the substrate 60, and the conductive particles 90 in the anisotropic conductive film 80 are sandwiched between the wiring 70 and the bump 45. The conductive particles 90 are not sandwiched between the adjacent bumps 45 so that they have insulating properties.
[0005]
The semiconductor device 10 includes an aluminum pad 20 and an insulating film 30 having an opening on the aluminum pad 20. A common electrode film 42 is provided across the aluminum pad and the insulating film 30 in the opening, and the common electrode film is formed on the common electrode film. Bumps 45 are provided.
[0006]
The conductive particles 90 shown in FIG. 6 are obtained by forming Ni + Au on the surface of an organic polymer resin and having a diameter of 5 μm to 10 μm.
[0007]
Although not shown in FIG. 6, at least about 10 conductive particles 90 sandwiched between the wiring 70 and the bump 45 of the substrate 60 are necessary in order to obtain electrical conduction of 1Ω or less. When conductive particles 90 having a diameter of 5 μm are used, the area of the upper surface of the bump 45 needs to be 3000 μm 2 or more.
[0008]
The height of the bump 45 provided on the semiconductor device 10 in the conventional mounting structure shown in FIG. 6 is such that the conductive particles 90 are efficiently captured on the bump 45, and the resin of the anisotropic conductive film 80 is used for the semiconductor device. In order to fill the space between 10 and the substrate 60, it is desirable to design between 10 μm and 20 μm.
[0009]
As shown in FIG. 7, the semiconductor device 10 includes an aluminum pad 20 and an insulating film 30 having an opening on the aluminum pad 20, and a common electrode film 42 is formed across the aluminum pad in the opening and the insulating film 30. A straight wall type bump 45 is provided on the common electrode film.
[0010]
The prior art shown in FIG. 7 is an example in which a straight wall type bump 45 is provided on the semiconductor device 10, and the height is provided between 10 and 20 μm. Further, since the area of the upper surface of the bump 45 is required to be 3000 μm 2 or more, if the connection pitch is 80 μm and the gap between the bumps is 20 μm, the bump size is 60 μm × 50 μm.
[0011]
The straight wall type bumps 45 shown in FIG. 7 are mainly made of Au by plating. Under the bump 45, at least two layers of a metal for preventing mutual diffusion between the aluminum pad 20 of the semiconductor device 10 and Au which is a material of the bump 45 and a metal having a function of maintaining the adhesion of the bump 45 are common. Generally, an electrode film 42 is provided.
[0012]
The structure shown in FIG. 6 is an example using the semiconductor device described with reference to FIG. 7. When the conductive particles 90 having a diameter of 5 μm and the straight wall bumps 45 are used, the connection pitch can be up to 50 μm. It is.
[0013]
As shown in FIG. 8, the semiconductor device 10 has an aluminum pad 20 and an insulating film 30 having an opening on the aluminum pad 20, and a common electrode film 42 is formed across the aluminum pad and the insulating film 30 in the opening. The mushroom type bump 45 is provided on the common electrode film.
[0014]
The mushroom type bump 45 shown in FIG. 8 is provided by plating with Au or Cu + Au. Like the straight wall type bump, at least two of a metal for preventing mutual diffusion between the aluminum pad 20 of the semiconductor device 10 and Au of the bump 45 and a metal having a function of maintaining the adhesion of the bump 45 are provided below the bump 45. In general, a common electrode film 42 is provided.
[0015]
In place of the semiconductor device described in FIG. 6, the semiconductor device shown in FIG. 8 may be used. In the case of a mounting structure using conductive particles 90 having a diameter of 5 μm and mushroom type bumps 45, the connection pitch can be up to 80 μm. Is possible.
[0016]
Straight wall type bumps and mushroom type bumps are provided by plating, but the variation in bump height 45 is 4 μm (± 2 μm) at 15 μm bumps.
[0017]
[Problems to be solved by the invention]
The liquid crystal display devices are required to display with high definition year by year, and those with a pixel pitch of 20 μm to 40 μm have come out.
[0018]
The connection pitch of the bumps 45 of the semiconductor device 10 is 50 μm at the minimum in the case of a mounting structure using the anisotropic conductive film 80 having the conductive particles 90 having a diameter of 5 μm and the straight wall type bumps 45.
[0019]
Therefore, it is necessary to design the area where the semiconductor device 10 is mounted with the pixel pitch widened. By widening the pixel pitch, the frame area of the liquid crystal display device must be increased, and the commercial value of the liquid crystal display device is reduced.
[0020]
If an anisotropic conductive film 80 having conductive particles 90 having a diameter of less than 5 μm is used, bump design corresponding to a connection pitch of 20 μm to 40 μm is possible, but bump height variation by plating method is 4 μm (± 2 μm). Therefore, if the bump height is 4 μm lower, the electrical connection between the wiring 70 of the substrate 60 and the bump 45 becomes unstable, causing a display defect of the liquid crystal display device.
[0021]
In addition, in order to obtain a bump connection pitch of 20 μm corresponding to a pixel pitch of 20 μm, the opening width of the resist having a thickness of 10 μm to 20 μm must be formed with a thickness of 10 μm or less in the formation of the straight wall type bump, and the aspect ratio becomes severe. Stable formation of the resist becomes difficult.
[0022]
The connection pitch of the semiconductor device 10 shown in FIG. 8 is the smallest in the mounting structure using the anisotropic conductive film 80 having the conductive particles 90 having a diameter of 5 μm and the mushroom bumps 45.
[0023]
Therefore, it is necessary to design the area where the semiconductor device 10 is mounted with a wider pixel pitch than the straight wall type. By widening the pixel pitch, the frame area of the liquid crystal display device has to be increased, and the commercial value of the liquid crystal display device is reduced as in the straight wall type.
[0024]
Formation of mushroom-type bumps 45 having a height of 10 μm to 20 μm corresponding to a connection pitch of 20 μm is impossible due to the structure having an umbrella.
[0025]
(Object of the Invention) In order to solve the above-mentioned problems, in the present invention, the conductive particles 90 are used to provide an electrode 40 having no height variation, and a semiconductor device mounting structure corresponding to the pixel pitch of a liquid crystal display device and The purpose is to provide the implementation method .
[0026]
[Means for Solving the Problems]
In order to achieve the above object, the present invention employs a semiconductor device, a manufacturing method thereof, and a mounting structure thereof described below.
[0027]
A mounting structure of a semiconductor device according to the present invention includes an insulating film having an opening on an aluminum pad, a metal film including a plurality of layers provided over the aluminum pad and the insulating film in the opening, and the metal film A semiconductor device mounting structure for connecting a semiconductor device having a photosensitive resin formed larger than an opening of an insulating film to a wiring on a substrate, wherein the metal film is masked using the photosensitive resin as a mask An insulating resin in which conductive particles are dispersed is provided between the semiconductor device and the substrate while leaving the photosensitive resin, and the thickness of the metal film is increased. Conductivity is set between 0.5 and 2 times the conductive particles, the semiconductor device and the substrate are bonded with an insulating resin, and the conductive particles sandwiched between the metal film and the wiring among the conductive particles Particles electrically connect metal film and wiring Characterized in that were passed.
[0028]
The mounting structure of the semiconductor device of the present invention is characterized in that the thickness of the photosensitive resin is greater than 0.1 μm and does not exceed 80% of the diameter of the conductive particles.
[0029]
According to another aspect of the present invention, there is provided a method for mounting a semiconductor device in which a semiconductor device is connected to a wiring on a substrate through an insulating resin in which conductive particles are dispersed, and an opening is formed on an aluminum pad provided on the semiconductor device. A step of forming an insulating film having a plurality of layers, a step of forming a metal film composed of a plurality of layers over the aluminum pad in the opening and the insulating film, and a photosensitive resin larger than the opening of the insulating film on the metal film A step of forming a mask comprising: a step of etching and removing a metal film in an opening of the mask; a step of heating and attaching an insulating resin on the substrate; a wiring provided on the substrate; and a metal film provided on the semiconductor device And bonding the semiconductor device and the substrate with the insulating resin while leaving the photosensitive resin , and the step of curing the insulating resin by pressurizing and heating from the back side of the semiconductor device, and Guidance Of sex particles, the conductive particles sandwiched between the wiring and the metal film, characterized in that is electrically connected to the wiring metal film.
[0030]
The semiconductor device mounting method of the present invention is characterized in that the thickness of the photosensitive resin is greater than 0.1 μm and does not exceed 80% of the diameter of the conductive particles.
[0031]
(Function)
Since the semiconductor device of the present invention is provided with an electrode made of a metal film, the height variation range of the metal film can be reduced to 0.5 μm or less as compared with the conventional plating method.
Furthermore, since a photosensitive resin is provided on the metal film, contact between the metal film and air is prevented to prevent the progress of oxidation on the surface of the metal film, so that inexpensive and good conductors such as Ag and Cu can be used. .
[0032]
An anisotropic conductive film having conductive particles smaller than 5 μm in diameter can be applied, and the upper area of the metal film can be made smaller than 3000 μm 2, and a connection pitch smaller than 40 μm can be handled.
[0033]
With the above configuration, it is possible to maintain a stable connection without increasing the frame width even at a connection pitch corresponding to a pixel pitch of 20 to 40 μm of the liquid crystal display device.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a semiconductor device, a manufacturing method thereof, and a mounting structure thereof in an optimal embodiment for carrying out the present invention will be described with reference to the drawings. An embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a cross-sectional view of a semiconductor device 30 in which an anisotropic conductive film 60 is provided on a substrate 10 having wirings 20. 2 to 5 are cross-sectional views illustrating the method of manufacturing the semiconductor device used in FIG.
[0035]
[Structure of semiconductor device: FIG. 5]
First, a semiconductor device according to an embodiment of the present invention will be described with reference to FIG.
As shown in FIG. 5, the semiconductor device 10 includes an aluminum pad 20, an insulating film 30, and a metal film 40, and the insulating film 30 has an opening on the aluminum pad 20 and straddles the aluminum pad 20 and the insulating film 30. And a photosensitive resin 50 is provided on the metal film. The insulating film 30 is made of a SiN film, and the metal film 40 is made of a two-layer film of Cr and Cu.
[0036]
[Mounting structure: Fig. 1]
Next, a semiconductor device mounting structure according to an embodiment of the present invention will be described with reference to FIG.
As shown in FIG. 1, the semiconductor device includes a wiring 70 provided on a substrate 60, an anisotropic conductive film 80 provided on the substrate 60, and a semiconductor device 10 having a metal film 40 provided on the substrate 60. An anisotropic conductive film 80 is sandwiched between 10 and the substrate 60, and conductive particles 90 in the anisotropic conductive film 80 are sandwiched and electrically connected between the wiring 70 and the metal film 40. Since the conductive particles 90 are not sandwiched between the films 40, they have insulating properties.
[0037]
The photosensitive resin 50 is provided around the metal film 40 and between the metal film 40 and the wiring 70 so as to be larger than the width of the metal film, and the photosensitive resin 50 is provided at a height that does not contact the wiring 70.
[0038]
As the anisotropic conductive film 80, a film in which conductive particles 90 are dispersed in an insulating resin is used.
The conductive particles 90 are made of a polymer resin formed by forming Ni + Au on the surface of an organic polymer resin and having a diameter smaller than 5 μm.
[0039]
The electrode 40 provided in the semiconductor device 10 has a height of 2 μm to 10 μm, and is provided on the substrate 60 via the anisotropic conductive film 80 at a position corresponding to the wiring 70 of the substrate 60.
[0040]
The conductive particles 90 are sandwiched between the metal film 40 and the wiring 70, and the resin of the anisotropic conductive film 80 is cured in a state in which the conductive particles 90 are deformed by 5% to 50% to obtain electrical conduction.
[0041]
The thickness of the metal film 40 may be 0.5 to 2 times the diameter of the conductive particles 90.
In the case where it is smaller than 0.5 times, when the semiconductor device 10 is mounted on the substrate 60 under a pressure condition that deforms the conductive particles 90 by 50%, the portion between the semiconductor device 10 and the substrate 60 in the portion where the metal film 40 is not present. As a result, the conductive particles 90 are crushed, and the insulating film 30 provided in the semiconductor device 10 is cracked, which is not preferable.
[0042]
The thickness of the photosensitive resin 50 is desirably smaller than the diameter of the conductive particles 90 that are responsible for electrical connection.
When the thickness is larger than the diameter, when the semiconductor device 10 is aligned with the substrate 60 and heated and pressed, the photosensitive resin 50 on the metal film 40 spreads in contact with the substrate side, and the conductive particles 90 spread on the metal film. As a result, the number of conductive particles 90 on the metal film 40 is reduced.
[0043]
Since the photosensitive resin 50 is provided on the metal film 40, it has an effect of preventing contact between the metal film surface and air. Accordingly, it is possible to use a metal that is relatively easily oxidized, such as Ag and Cu, and the cost can be reduced.
[0044]
Since the height dimension of the metal film is 10 μm or less, the conductive particles 90 are immediately captured by the metal film 40 when the semiconductor device 10 is pressure-bonded using the anisotropic conductive film 80. The effect that the conductive particles 90 can be sandwiched efficiently is obtained.
[0045]
(Manufacturing method: FIGS. 2-5)
Next, a method for manufacturing a semiconductor device will be described in the order of steps with reference to FIGS.
As shown in FIG. 2, an insulating film 30 having an opening is formed on an aluminum pad 30 provided in the semiconductor device 10 so as to have a thickness of 0.5 μm to 5 μm.
As the insulating film 30, a SiN film is formed by a CVD method, and an opening is formed on the aluminum pad 20 by photolithography.
[0046]
Next, as shown in FIG. 3, a metal film 40 made of Cr and Cu is formed on the entire surface of the semiconductor device 10 by sputtering.
The metal film 40 is formed to have a thickness between 0.5 and 2 times the diameter of the conductive particles 90.
[0047]
Next, as shown in FIG. 4, the photosensitive resin 50 is formed by photolithography so as to be larger than the opening of the insulating film 30. When the size of the opening of the insulating film 30 is the same as or smaller than that of the opening, the aluminum pad 20 is etched simultaneously when the metal film 40 is removed by etching, so that a defect is caused.
The thickness of the photosensitive resin 50 is preferably 0.1 μm or more and between 80% or less of the diameter of the conductive particles 90.
[0048]
When the thickness of the photosensitive resin 50 is smaller than 0.1 μm, the antioxidant effect on the surface of the metal film 40 cannot be sufficiently obtained. Further, when the thickness of the photosensitive resin 50 exceeds 80% of the diameter of the conductive particles 90, the photosensitive resin 50 spreads in contact with the wiring 70 when the semiconductor device 10 is mounted on the substrate 60, and the conductive property is increased. The particles 90 are pushed out of the metal film 40, which is not preferable.
[0049]
Finally, as shown in FIG. 5, the metal film 40 in the opening of the photosensitive resin 50 is removed by etching the metal film 40 using the photosensitive resin 50 as a mask.
[0050]
In the bumps of the prior art, the bumps were formed at a height of 10 μm to 20 μm by the plating method, and thus the height variation was 4 μm (± 2 μm). However, because the metal film 40 is formed only by the metal film 40. In addition, the effect of reducing the height variation to 0.5 μm or less can be obtained.
[0051]
Since the photosensitive resin 50 is provided on the metal film 40, contact between the metal film 40 and air can be prevented, and progress of surface oxidation of the metal film 40 can be prevented, so that a metal made of Cu or Ag can be used. Thus, the effect of reducing the cost can be obtained.
Furthermore, since the plating process and the photosensitive resin peeling process are not required, the effect of shortening the process compared to the prior art can be obtained.
[0052]
[Explanation of mounting method]
An anisotropic conductive film 80 is attached to the substrate 60 at a temperature of 90 ° C. The wiring 70 of the substrate 60 and the metal film 40 of the semiconductor device 10 are aligned and pressurized and heated from the back side of the semiconductor device 10 to cure the anisotropic conductive film 80.
[0053]
When pressurized and heated, the conductive particles 90 are sandwiched between the metal film 40 provided on the semiconductor device 10 and the wiring 70 provided on the substrate 60. The conductive particles 90 sandwiched as shown in FIG. 1 are electrically connected, and the conductive particles 90 not sandwiched have an insulating property.
[0054]
【The invention's effect】
As is apparent from the above description, according to the present invention, an anisotropic conductive film in which conductive particles 90 having a small particle diameter are dispersed is obtained in order to obtain a metal film having better height uniformity than conventional bumps. Can be used to obtain a connection mounting structure corresponding to a fine pitch of less than 40 μm.
Since the number of steps can be reduced in the metal film forming process compared with the conventional bump forming process, the manufacturing cost can be reduced.
[0055]
In addition, since the photosensitive resin is provided on the metal film, the contact between the metal film and air can be prevented, and the progress of surface oxidation of the metal film can be prevented, so that a metal made of Cu or Ag can be used. An effect of reducing the cost can be obtained.
[0056]
Since the height of the metal film is low unlike the bump, the flow of the conductive particles 90 can be suppressed when the thermocompression bonding is performed, and the conductive particles 90 can be effectively captured on the metal film.
[0057]
In the conventional bump, the common electrode film is etched using the bump as a mask. In particular, in wet etching, the etching rate of the common electrode film was increased due to the local battery effect between the bump material and the common electrode film material, and it was necessary to secure a large etching margin. Since the film is etched, the local battery effect does not occur, and the etching margin can be widened.
If the same etching margin is selected, the design value can be changed to correspond to a fine pitch as compared with the prior art.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a mounting structure of a semiconductor device in an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a method for manufacturing a semiconductor device in an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a method for manufacturing a semiconductor device in an embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a method for manufacturing a semiconductor device in an embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a method for manufacturing a semiconductor device in an embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a mounting structure of a semiconductor device in the prior art.
FIG. 7 is a cross-sectional view showing a structure of a semiconductor device in the prior art.
FIG. 8 is a cross-sectional view showing a structure of a semiconductor device in the prior art.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Semiconductor device 20 Aluminum pad 30 Insulating film 40 Metal film 42 Common electrode film 45 Bump 50 Photosensitive resin 60 Substrate 70 Wiring 80 Anisotropic conductive film 90 Conductive particle

Claims (4)

アルミパッド上に開口部を有する絶縁膜と、開口部内のアルミパッド上と絶縁膜とにまたがって設けた複数の層からなる金属膜と、その金属膜上に設けられ前記絶縁膜の開口部より大きく形成されている感光性樹脂とを有する半導体装置を、基板上の配線と接続する半導体装置の実装構造であって、
前記金属膜は前記感光性樹脂をマスクとして前記マスクの開口部の金属膜を除去することによって形成されており、前記感光性樹脂を残したまま前記半導体装置と前記基板との間に導電性粒子を分散した絶縁性樹脂を設け、前記金属膜の膜厚を前記導電性粒子の０．５倍から２倍の範囲に設定し、前記絶縁性樹脂で前記半導体装置と前記基板とを接着し、かつ前記導電性粒子のうち、前記金属膜と前記配線との間に挟み込まれた導電性粒子によって、前記金属膜と前記配線とを電気的に導通させたことを特徴とする半導体装置の実装構造。An insulating film having an opening on the aluminum pad, a metal film composed of a plurality of layers provided over the aluminum pad and the insulating film in the opening, and an opening of the insulating film provided on the metal film A semiconductor device mounting structure for connecting a semiconductor device having a large photosensitive resin to a wiring on a substrate,
The metal film is formed by removing the metal film at the opening of the mask using the photosensitive resin as a mask, and is conductive between the semiconductor device and the substrate while leaving the photosensitive resin . An insulating resin in which particles are dispersed is provided, the film thickness of the metal film is set in a range of 0.5 to 2 times that of the conductive particles, and the semiconductor device and the substrate are bonded with the insulating resin. And mounting the semiconductor device, wherein the metal film and the wiring are electrically connected by the conductive particles sandwiched between the metal film and the wiring among the conductive particles. Construction. 前記感光性樹脂の厚さが０．１μｍより大きく前記導電粒子の直径の８０％を越えないことを特徴とする請求項１に記載の半導体装置の実装構造。  2. The semiconductor device mounting structure according to claim 1, wherein the thickness of the photosensitive resin is greater than 0.1 [mu] m and does not exceed 80% of the diameter of the conductive particles. 半導体装置を導電性粒子を分散した絶縁性樹脂を介して基板上の配線と接続する半導体装置の実装方法において、
半導体装置上に設けるアルミパッド上に開口部を有する絶縁膜を形成する工程と、該開口部内のアルミパッド上と絶縁膜とにまたがって複数の層からなる金属膜を形成する工程と、該金属膜上に前記絶縁膜の開口部より大きい感光性樹脂からなるマスクを形成する工程と、該マスクの開口部の金属膜をエッチング除去する工程と、前記絶縁性樹脂を基板上に加熱して貼り付ける工程と、前記基板上に設ける配線と前記半導体装置に設ける金属膜とを位置合わせして前記半導体装置の裏面側から加圧加熱し、前記絶縁性樹脂を硬化させる工程とを有し、
前記感光性樹脂を残したまま前記絶縁性樹脂で前記半導体装置と前記基板とを接着し、かつ前記導電性粒子のうち、前記金属膜と前記配線との間に挟み込まれた導電性粒子によって、前記金属膜と前記配線とを電気的に導通させたことを特徴とする半導体装置の実装方法。In a semiconductor device mounting method for connecting a semiconductor device to wiring on a substrate through an insulating resin in which conductive particles are dispersed,
Forming an insulating film having an opening on an aluminum pad provided on the semiconductor device; forming a metal film composed of a plurality of layers over the aluminum pad in the opening and the insulating film; and Forming a mask made of a photosensitive resin larger than the opening of the insulating film on the film; etching removing the metal film in the opening of the mask; and heating and pasting the insulating resin on the substrate. And a step of aligning a wiring provided on the substrate and a metal film provided on the semiconductor device, pressurizing and heating from the back side of the semiconductor device, and curing the insulating resin,
By adhering the semiconductor device and the substrate with the insulating resin while leaving the photosensitive resin , and among the conductive particles, the conductive particles sandwiched between the metal film and the wiring, A mounting method of a semiconductor device, wherein the metal film and the wiring are electrically connected. 前記感光性樹脂の厚さが０．１μｍより大きく前記導電粒子の直径の８０％を越えないことを特徴とする請求項３に記載の半導体装置の実装方法。  4. The method for mounting a semiconductor device according to claim 3, wherein the thickness of the photosensitive resin is greater than 0.1 [mu] m and does not exceed 80% of the diameter of the conductive particles.
JP01548198A 1998-01-28 1998-01-28 Mounting structure of semiconductor device and mounting method thereof Expired - Fee Related JP3929154B2 (en)

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