TW200828530A - Stacked type chip package structure - Google Patents

Stacked type chip package structure Download PDF

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Publication number
TW200828530A
TW200828530A TW096107819A TW96107819A TW200828530A TW 200828530 A TW200828530 A TW 200828530A TW 096107819 A TW096107819 A TW 096107819A TW 96107819 A TW96107819 A TW 96107819A TW 200828530 A TW200828530 A TW 200828530A
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TW
Taiwan
Prior art keywords
wafer
stacked
substrate
circuit substrate
circuit
Prior art date
Application number
TW096107819A
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English (en)
Other versions
TWI333266B (en
Inventor
Hyeong-No Kim
Original Assignee
Advanced Semiconductor Eng
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Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Publication of TW200828530A publication Critical patent/TW200828530A/zh
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Publication of TWI333266B publication Critical patent/TWI333266B/zh

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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

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200828530 ASEK1883 22568twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種堆叠式晶 :於-種具有-射頻晶片(一之堆叠式晶= 【先前技術】 由於電子產業的蓬勃私嚴 輕量化和高軌的目標 頻曰…Γ::例如將射頻晶片與數位1C、射
DS；； (D^ ProceJ (Base Band, ΒΒ) ΰ . Μ聖化或咼速化的目標，惟由於射頻曰 片係為頻，因此必須進行電磁 員曰曰 以避免訊號之干擾。 g)慝理 言主表種堆疊式晶料裝結構之剖面示意圖。 』二：、:1式严片封裝結構100包括-載板110、一 110 Γ有二—第二晶片13G以及—金屬片14。。載板 配置;112以及一下表面114。第-晶片m 130之ί，击〇配置於弟—晶片120及第二晶片 Β亚連接至—接地端150,用以隔絕及防止第一晶 片2〇的，號對於射頻晶片之干擾。然而，設置於第一晶 片120與第二晶片130之間的金屬片140會使整個堆疊式 200828530 ASEK1883 22568twf.doc/n 日日乃封裝結構100的厚度择知， 之小型化、輕量化的要求。日 、法達到電子產品所需 【發明内容】 本發明是提供-種堆疊式晶片 結構係將-第二晶片（例如基頻晶片;=於 (例如射頻晶片）上’並利用電性連接之—接地二片 電溥膜或—中介基板保護射頻晶片免受訊 ，-導 射頻晶片是設置於線路基板之容置孔中，因、，並:此 加晶片封裝結構之總厚度。 w g % 本發明提出-種堆疊式晶片封裝 背板、-線路基板、m 主要包括— ^ 3b JL « ^ 第—日日片以及一導雷 涛膜。月板具有-線路層。線路基板位於背板之上" ^有-上絲以及與其相制之—下表面，且線路美板= 應於背板處具有-容置孔。第—晶片位於容置孔中，^ 一晶片透過背板之線路層與線路基板電性連接。第二曰= =於第—晶片之上，並與線路基板電性連接。^曰 之-接:端二;間’且導電薄媒與線路基板 在本發明之-實施例中，上述之線路基 配置於下表面上的焊球。 夕数们 晶片。 在本發明之-實施例中，上述之第—晶片包括一射 頻 曰曰 在本發明之-實施例中’上述之第—晶片係透過覆 接合方式(flip chip technique)與背板之線路層電性連接。 6 200828530 ASEK1883 22568twfdoc/n 在本發明之一實 丄K乐一晶片包括一數位 一 一 ——ug /η 積體電路，一數位訊號處理器或是一基頻晶片 在本發明之一實施例中，上述之第二晶片係透過打線 接合方式(wire bonding technique)或覆晶接合方式與線路
基板電性連接。 ^V 在本發明之-實施例中，上述之導電薄膜係由導電膠 所形成。 / 在本發明之-實施例中，堆疊式晶片封袭 一封裝膠體，其中封裝膠體是配置於線 二晶片，且填充於線路基板4= 本發明另提出—種晶片封裝結構，其主要包 反、：線職板、-第-晶片、-第二晶片以及一中介： 板。月板具有-線路層。線路基板 ^ ;有-上表面以及與其相對應之-下表面=板; f於，處具有-容置孔。第-晶片配置於容 晶片配置於第-晶片之=層與線路基板電性連接。第二 介基板配置於第—晶片基板電性連接。中 路基板之-接地端電性連^/a片之間’且中介基板與線 配置===种’取魏㈣括多數個 在本發明之一實施例中， 晶片 上述之第一晶片包括一射頻 7 200828530 ASEK1883 22568twf.doc/n 在本發明之-實施例中，上述之第一晶片是透過覆晶 接合方式與背板之線路層電性連接。 在本發明之-實施例中，上述之第二晶片包括一數位 積體電路、一數位訊號處理器或是一基頻晶片。 在本發明之-實施例中’上述H片是透過打線 接合方式與線路基板電性連接。 Γ 之—實施例中，堆疊式晶片難結構更包括 -封裝膠體，其中封裝賴是配置於線路基板之上表面 ΐ之=蓋第二晶片’且填充於線路基板、背板與第一晶 之rd 一實施例中，上述之中介基板與線路基板 且中介基板是透過覆晶接合方式或是打 、·、 &方式與線路基板之一接地端電性連接。一 在本發明之一實施例中，上述之中介 著材料固定於第U上。 k透過-黏 在本發明之一實施例中，上 著材料固·中介基板上。 4疋透過一黏 综上所述，本發明之堆疊式晶 晶片（例如基頻晶片）堆疊於第構係將-弟二 之上，並將配置於二Θ月門=列如射頻晶片） 帝W、查拉 、曰片之間的一 薄膜或一中介其拓 、Γ 接至—接地端。由於此導電薄膜或中八其4 3 土 、接至接地端，因此可將第二晶片所生電性 進而保護第-晶片免受訊號干擾。此外，=干擾消除’ 設置於線路基板之容置孔令，因此’並不會增力 8 200828530 ASHK1883 22568twf.doc/n 結構的整體厚度。 >為，本發明之上述特徵和優點能更明顯易懂，下文特 舉較佳貫施例，並配合所附圖式，作詳細說明如下。 【實施方式】 c 圖2緣示為根據本發明之第-實施綱-種堆疊式晶 片封裝結構的剖面示意圖。請參關2，本實施例之堆= 式晶片封裝結構200主要包括一背板21〇、一線路基 2=、一第一晶片230、一第二晶片24〇及一導電薄膜25〇。 背板210具有-線路層212，此線路層212是位於背板加 之上表面。線路基板220位於背板21〇之上方，且具有一 上表面220a以及與其相對應之一下表面22%。線路美 220對應於背板21〇處具有一容置孔222，用以容置第一晶 片230。線路基板22〇可以印刷電路板(pCB)、晶片载板等 取代。此外，線路基板220包括多數個選擇性配置於下表 面220b上的焊球224，如此，堆疊式晶片封裝結構2〇〇 ^ 透過焊球224與其它電子設備電性連接 第一晶片230包括一射頻晶片，且是配置於背板 之合置孔222中。第-晶片230透過背板21〇之線路層212 ，與線路基板220電性連接。在本實施例中，第一晶片23〇 疋透過覆晶接合方式與背板210之線路層212電性連 第二;片24〇是位於第-晶片230之上方，立與線^板 220电性連接。在本實施例令，第二晶片24〇包括—數位 積體電路、-數他號處理器或是―基頻晶片，且第二晶 片240是透過打線接合方式與線路基板22〇電性連接。= 9 200828530 3 22568twf.doc/n /ιοηινιοο 而，第二晶片240亦可透過其它方 連接，例如覆晶接合方式。本發_第复路=220電性 路基板220之間電性連接的方式不作任二片:4:與線 250係配置於第-晶片·與第二 薄膜250是電性連接於線路基板220之—=亡導電 以保護射頻晶片务A其相曰μ 接地鳊224a，用 25〇係由導電膠所^：^片=號的影響。導電薄膜 將第-曰電性環氧樹脂’且可用以 將弟-日日片24GH1定於第—晶片⑽的上方。 此外，堆疊式晶片封裝結構·更包括 260。’封褒膠體26〇是配置於線路基板2%之上表=二 上。此封裝膠體260覆蓋住第_曰g 94λ
Ail- 99n ,傻皿伍弟一日日片240，且填充於線路 基:月板210與第一晶片23〇之間，用以保護上述 2^0 ίΓΓ潮及找°由於導電薄膜250是透過線路基板 (例it日224at性連接’因此，可消除第二晶片· 土頻晶片）所產生電磁干擾，進而保護第一晶片23〇 (列如射頻晶片）免受第二晶片之訊號的影響。 圖3繪示為根據本發明之第二實施例的一種堆疊式晶 =封裝結構的剖面示意圖。請參照圖3，堆疊式晶片封裝 …構200,大致上圖2所示之堆疊式晶片封裴結構2〇〇雷 同，而二者不同之處在於：此堆疊式晶片封裝結構2〇〇，是 利=中介基板270以取代圖2中所示之導電薄膜25〇。在 本實施例中，中介基板270是位於第一晶片23〇與第二晶 片240之間。更進一步而言，中介基板27〇與線路基板22〇 之間存在一距離，且中介基板27〇是透過打線接合方式與 200828530 ASEK1883 22568twf.doc/n 線路基板220之-接地端（圖中未示）電性 ^所示，中介基板謂亦可使用導電凸塊齡= =之-接地端電性連接。本發明對於中介基板27〇J 線路基板22G之間電性連接的方式不作任何限制。-此外，在此實施例中，中介基板27〇
=定於第一晶片230上，且第二晶片_是透C 於中介基板270上。再者，如圖5所示， 右弟-日日片230之厚度較薄時，背板21〇盘中介 =分別抵靠於線路基板22G的下表面22%及土上表面 度。a以更進-步減少堆疊式晶片封裝結構，的整體厚 片，本發明之堆疊式晶#封裝結構係將第二晶 並2= 堆疊於第一晶片(例如射頻晶片)上， 連接—間的—導電薄臈或是—中介基板電性 將;^ 疋於線路基板的容置孔中，因此， 、有助於減少晶片封裝結構的整體厚度。 雖然本發明較佳實蝴聽如上，鉢並 脫iir月，任何所屬技術領域中具有通f知識者，在不 因此二當可作些許之更動與潤·， 本么月之保遵耗圍當視後附之申請專利範圍所界定者 【圖式簡單說明】 11 200828530 ASEK1883 22568twf.doc/n 圖1繪示為習知之一種堆疊式晶片封裝結構剖面示意 圖。 圖2繪示為根據本發明之第一實施例的一種堆疊式晶 片封裝結構的剖面示意圖。 圖3繪示為根據本發明之第二實施例的一種堆疊式晶 片封裝結構的剖面示意圖。 圖4繪示為根據本發明之另一實施例的一種堆疊式晶 片封裝結構的剖面示意圖。 圖5繪示為根據本發明之另一實施例的一種堆疊式晶 片封裝結構的剖面示意圖。 【主要元件符號說明】 100、200、200’ ：堆疊式晶片封裝結構 110 :載板 112 ··上表面 114 :下表面 120 :第一晶片 130 :第二晶片 140 :金屬片 150 :接地端 210 :背板 212 :線路層 220 :線路基板 220a :上表面 12 200828530 Αί>ϋκΐδδ^ 22568twf.doc/n 220b :下表面 224 :焊球 224a :接地端 230 :第一晶片 240 :第二晶片 250 :導電薄膜 260 :封裝膠體 270 :中介基板 280 :導電凸塊 290 :黏著材料 292 :黏著材料

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  1. 200828530 ▲ *一一—w—» 22568twf,doc/n 十、申請專利範圍： 1·一種堆疊式晶片封裝結構，包括： 一背板，具有一線路層； —線路基板，位於該背板之上方，其中該線 下表一‘對 板電:::晶:及位於該第一晶片之上方’且與該線路基 且料ί電薄膜，配置於該第—晶片與該第二晶片之門， 且^^ _無線路基板之—接地端電性^片之間 構，其中範圍第1項所述之堆疊式晶片封裝結 3·如;t專基^f/數個配置於該下表面上的焊球。 構’其中匕日=弟1項所述之堆疊式晶片封褒結 ^弟一日日片包括一射頻晶片。 構，其第1項所述之堆疊式晶片封裝結 路層電性連接。㈤讀過覆晶接合方式與·板之該線 構，其中圍第1項所述之堆疊式晶片封裝結 理器或是」基^^包括—數位積體電路、—數位訊號處 構，6其圍第1項所述之堆疊式晶片封裝結 “潯膜係由導電膠所形成。 14 \ 22568twf.doc/n 200828530 7·如申請專利範圍第1項所述之堆疊式晶片封參、会士 構，更包括一封裝膠體，其中該封裝膠體是配置於該 基板之該上表面上，以覆蓋該第二晶片，且填充於該線路 基板、該背板與該第一晶片之間。 ' 8·—種堆疊式晶片封裝結構，包括： 一背板’具有一線路層； 一線路基板，位於該背板之上方，其中該線路基板具
    有一上表面以及與其相對應之一下表面，且該線路基板對 應於該背板處具有一容置孔； 土 、 此一第一晶片，位於該容置孔中，且該第一晶片透過該 背板之該線路層而與該線路基板電性連接； 一第二晶片，位於該第一晶片之上方，且與該線路基 板電性連接；以及 二一中介基板，配置於該第一晶片與該第二晶片之間， 且該中介基板與該線路基板之一接地端電性連接。 9·如申請專利範圍第8項所述之堆疊式晶片封裂結 構’其中該線路基板包括多數個配置於該下表面上的焊^口。 10·如申請專利範圍第8項所述之堆疊式晶片封裝結 構’其中該第-晶片包括—射頻晶片。 接申請專利範圍第8項所述之堆疊式晶片封褒結 靜第—晶片是透過覆日日日接合方式與該背板之該線 路層電性連接。 堪申請專利範圍第8項所述之堆疊式晶片封裝結 ’、5玄月板與該中介基板分別抵靠於該線路基板之該 15 J 22568twf.doc/n 200828530 下表面與該上表面。 13·如申請專利範圍第8項所述之堆疊式晶片封裝結 構，其中该苐一晶片包括一數位積體電路、一數位訊號處 理器或是一基頻晶片。 14·如申請專利範圍第8項所述之堆疊式晶片封裝結 構，其中该第二晶片是透過打線接合方式與該線路基板帝 性連接。 ％
    15 ·如申請專利範圍第8項所述之堆疊式晶片封裝結 構，更包括一封裝膠體，其中該封裝膠體是配置於該線路 ΐΐ之面上’以覆蓋該第二晶片，且填充於:線路 基板、邊月板與該第一晶片之間。 •曱知專利範圍第8項所述之堆疊式晶片封 中該中介基板與該線路基板之間具有—距離，^^ =基板是透過覆晶接合方式或是打線接合方式與ς 基板之该接地端電性連接。 X、、、路 播請專利範圍第8項所述之堆疊式晶片封驗 上/、〃中介基板是透過—黏著材料固定於該第—晶片 構第8項所述之堆疊式晶片封裝結 上。4疋透過—黏著材料固定於該中介基板 16
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Publication number Priority date Publication date Assignee Title
CN103915418A (zh) * 2013-01-08 2014-07-09 矽品精密工业股份有限公司 半导体封装件及其制法
TWI550816B (zh) * 2013-01-08 2016-09-21 矽品精密工業股份有限公司 半導體封裝件及其製法
CN103915418B (zh) * 2013-01-08 2017-11-10 矽品精密工业股份有限公司 半导体封装件及其制法

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US7701046B2 (en) 2010-04-20

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